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Wolfram Sang9135bac2018-08-22 00:02:23 +02001// SPDX-License-Identifier: GPL-2.0
Magnus Damm8051eff2009-11-26 11:10:05 +00002/*
3 * SuperH MSIOF SPI Master Interface
4 *
5 * Copyright (c) 2009 Magnus Damm
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +02006 * Copyright (C) 2014 Renesas Electronics Corporation
7 * Copyright (C) 2014-2017 Glider bvba
Magnus Damm8051eff2009-11-26 11:10:05 +00008 */
9
Magnus Damm8051eff2009-11-26 11:10:05 +000010#include <linux/bitmap.h>
11#include <linux/clk.h>
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +010012#include <linux/completion.h>
13#include <linux/delay.h>
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +020014#include <linux/dma-mapping.h>
15#include <linux/dmaengine.h>
Magnus Dammac48eee2010-01-20 13:49:45 -070016#include <linux/err.h>
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +010017#include <linux/gpio.h>
Geert Uytterhoevenb8761432017-12-13 20:05:12 +010018#include <linux/gpio/consumer.h>
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +010019#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/kernel.h>
Paul Gortmakerd7614de2011-07-03 15:44:29 -040022#include <linux/module.h>
Bastian Hechtcf9c86e2012-12-12 12:54:48 +010023#include <linux/of.h>
Geert Uytterhoeven50a7e232014-02-25 11:21:09 +010024#include <linux/of_device.h>
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +010025#include <linux/platform_device.h>
26#include <linux/pm_runtime.h>
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +020027#include <linux/sh_dma.h>
Magnus Damm8051eff2009-11-26 11:10:05 +000028
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +010029#include <linux/spi/sh_msiof.h>
Magnus Damm8051eff2009-11-26 11:10:05 +000030#include <linux/spi/spi.h>
Magnus Damm8051eff2009-11-26 11:10:05 +000031
Magnus Damm8051eff2009-11-26 11:10:05 +000032#include <asm/unaligned.h>
33
Geert Uytterhoeven50a7e232014-02-25 11:21:09 +010034struct sh_msiof_chipdata {
35 u16 tx_fifo_size;
36 u16 rx_fifo_size;
Geert Uytterhoevenbeb74bb2014-02-25 11:21:10 +010037 u16 master_flags;
Vladimir Zapolskiy51093cb2018-04-13 15:44:17 +030038 u16 min_div_pow;
Geert Uytterhoeven50a7e232014-02-25 11:21:09 +010039};
40
Magnus Damm8051eff2009-11-26 11:10:05 +000041struct sh_msiof_spi_priv {
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +020042 struct spi_master *master;
Magnus Damm8051eff2009-11-26 11:10:05 +000043 void __iomem *mapbase;
44 struct clk *clk;
45 struct platform_device *pdev;
46 struct sh_msiof_spi_info *info;
47 struct completion done;
Geert Uytterhoeven08ba7ae2018-06-13 10:41:15 +020048 struct completion done_txdma;
Koji Matsuokafe78d0b2015-06-15 02:25:05 +090049 unsigned int tx_fifo_size;
50 unsigned int rx_fifo_size;
Vladimir Zapolskiy51093cb2018-04-13 15:44:17 +030051 unsigned int min_div_pow;
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +020052 void *tx_dma_page;
53 void *rx_dma_page;
54 dma_addr_t tx_dma_addr;
55 dma_addr_t rx_dma_addr;
Geert Uytterhoevenb8761432017-12-13 20:05:12 +010056 unsigned short unused_ss;
Geert Uytterhoeven7ff0b532017-12-13 20:05:10 +010057 bool native_cs_inited;
58 bool native_cs_high;
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +020059 bool slave_aborted;
Magnus Damm8051eff2009-11-26 11:10:05 +000060};
61
Geert Uytterhoeven9cce8822017-12-13 20:05:11 +010062#define MAX_SS 3 /* Maximum number of native chip selects */
63
Geert Uytterhoeven01cfef52014-02-20 15:43:03 +010064#define TMDR1 0x00 /* Transmit Mode Register 1 */
65#define TMDR2 0x04 /* Transmit Mode Register 2 */
66#define TMDR3 0x08 /* Transmit Mode Register 3 */
67#define RMDR1 0x10 /* Receive Mode Register 1 */
68#define RMDR2 0x14 /* Receive Mode Register 2 */
69#define RMDR3 0x18 /* Receive Mode Register 3 */
70#define TSCR 0x20 /* Transmit Clock Select Register */
71#define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
72#define CTR 0x28 /* Control Register */
73#define FCTR 0x30 /* FIFO Control Register */
74#define STR 0x40 /* Status Register */
75#define IER 0x44 /* Interrupt Enable Register */
76#define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
77#define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
78#define TFDR 0x50 /* Transmit FIFO Data Register */
79#define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
80#define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
81#define RFDR 0x60 /* Receive FIFO Data Register */
Magnus Damm8051eff2009-11-26 11:10:05 +000082
Geert Uytterhoeven01cfef52014-02-20 15:43:03 +010083/* TMDR1 and RMDR1 */
84#define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
85#define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
86#define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
87#define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
88#define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
89#define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
Yoshihiro Shimoda31106282014-12-19 17:15:53 +090090#define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
91#define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
Yoshihiro Shimoda6d405302015-01-06 19:01:26 +090092#define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
Geert Uytterhoeven01cfef52014-02-20 15:43:03 +010093#define MDR1_FLD_SHIFT 2
94#define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
95/* TMDR1 */
96#define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
Geert Uytterhoeven9cce8822017-12-13 20:05:11 +010097#define TMDR1_SYNCCH_MASK 0xc000000 /* Synchronization Signal Channel Select */
98#define TMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
Magnus Damm8051eff2009-11-26 11:10:05 +000099
Geert Uytterhoeven01cfef52014-02-20 15:43:03 +0100100/* TMDR2 and RMDR2 */
101#define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
102#define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
103#define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
104
105/* TSCR and RSCR */
106#define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
107#define SCR_BRPS(i) (((i) - 1) << 8)
108#define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
109#define SCR_BRDV_DIV_2 0x0000
110#define SCR_BRDV_DIV_4 0x0001
111#define SCR_BRDV_DIV_8 0x0002
112#define SCR_BRDV_DIV_16 0x0003
113#define SCR_BRDV_DIV_32 0x0004
114#define SCR_BRDV_DIV_1 0x0007
115
116/* CTR */
117#define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
118#define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
119#define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
120#define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
121#define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
122#define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
123#define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
124#define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
125#define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
126#define CTR_TXDIZ_LOW 0x00000000 /* 0 */
127#define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
128#define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
129#define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
130#define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
131#define CTR_TXE 0x00000200 /* Transmit Enable */
132#define CTR_RXE 0x00000100 /* Receive Enable */
133
Geert Uytterhoeven2e2b3682014-06-20 12:16:16 +0200134/* FCTR */
135#define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */
136#define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */
137#define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */
138#define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */
139#define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */
140#define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */
141#define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */
142#define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */
143#define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */
144#define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */
145#define FCTR_TFUA_SHIFT 20
146#define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT)
147#define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */
148#define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */
149#define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */
150#define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */
151#define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */
152#define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */
153#define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */
154#define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */
155#define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */
156#define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */
157#define FCTR_RFUA_SHIFT 4
158#define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT)
159
160/* STR */
161#define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */
162#define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */
Geert Uytterhoeven01cfef52014-02-20 15:43:03 +0100163#define STR_TEOF 0x00800000 /* Frame Transmission End */
Geert Uytterhoeven2e2b3682014-06-20 12:16:16 +0200164#define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */
165#define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */
166#define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */
167#define STR_RFFUL 0x00002000 /* Receive FIFO Full */
168#define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */
Geert Uytterhoeven01cfef52014-02-20 15:43:03 +0100169#define STR_REOF 0x00000080 /* Frame Reception End */
Geert Uytterhoeven2e2b3682014-06-20 12:16:16 +0200170#define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */
171#define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */
172#define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */
173
174/* IER */
175#define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */
176#define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */
177#define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */
178#define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */
179#define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */
180#define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */
181#define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */
182#define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */
183#define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */
184#define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */
185#define IER_REOFE 0x00000080 /* Frame Reception End Enable */
186#define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */
187#define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */
188#define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */
Geert Uytterhoeven01cfef52014-02-20 15:43:03 +0100189
Magnus Damm8051eff2009-11-26 11:10:05 +0000190
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +0100191static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
Magnus Damm8051eff2009-11-26 11:10:05 +0000192{
193 switch (reg_offs) {
194 case TSCR:
195 case RSCR:
196 return ioread16(p->mapbase + reg_offs);
197 default:
198 return ioread32(p->mapbase + reg_offs);
199 }
200}
201
202static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +0100203 u32 value)
Magnus Damm8051eff2009-11-26 11:10:05 +0000204{
205 switch (reg_offs) {
206 case TSCR:
207 case RSCR:
208 iowrite16(value, p->mapbase + reg_offs);
209 break;
210 default:
211 iowrite32(value, p->mapbase + reg_offs);
212 break;
213 }
214}
215
216static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +0100217 u32 clr, u32 set)
Magnus Damm8051eff2009-11-26 11:10:05 +0000218{
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +0100219 u32 mask = clr | set;
220 u32 data;
Magnus Damm8051eff2009-11-26 11:10:05 +0000221 int k;
222
223 data = sh_msiof_read(p, CTR);
224 data &= ~clr;
225 data |= set;
226 sh_msiof_write(p, CTR, data);
227
228 for (k = 100; k > 0; k--) {
229 if ((sh_msiof_read(p, CTR) & mask) == set)
230 break;
231
232 udelay(10);
233 }
234
235 return k > 0 ? 0 : -ETIMEDOUT;
236}
237
238static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
239{
240 struct sh_msiof_spi_priv *p = data;
241
242 /* just disable the interrupt and wake up */
243 sh_msiof_write(p, IER, 0);
244 complete(&p->done);
245
246 return IRQ_HANDLED;
247}
248
Vladimir Zapolskiy51093cb2018-04-13 15:44:17 +0300249static const u32 sh_msiof_spi_div_array[] = {
250 SCR_BRDV_DIV_1, SCR_BRDV_DIV_2, SCR_BRDV_DIV_4,
251 SCR_BRDV_DIV_8, SCR_BRDV_DIV_16, SCR_BRDV_DIV_32,
Magnus Damm8051eff2009-11-26 11:10:05 +0000252};
253
254static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
Geert Uytterhoeven6a85fc52014-02-20 15:43:02 +0100255 unsigned long parent_rate, u32 spi_hz)
Magnus Damm8051eff2009-11-26 11:10:05 +0000256{
Vladimir Zapolskiy51093cb2018-04-13 15:44:17 +0300257 unsigned long div;
Nobuhiro Iwamatsu65d56652015-01-30 15:11:54 +0900258 u32 brps, scr;
Vladimir Zapolskiy51093cb2018-04-13 15:44:17 +0300259 unsigned int div_pow = p->min_div_pow;
Magnus Damm8051eff2009-11-26 11:10:05 +0000260
Vladimir Zapolskiy51093cb2018-04-13 15:44:17 +0300261 if (!spi_hz || !parent_rate) {
262 WARN(1, "Invalid clock rate parameters %lu and %u\n",
263 parent_rate, spi_hz);
264 return;
Magnus Damm8051eff2009-11-26 11:10:05 +0000265 }
266
Vladimir Zapolskiy51093cb2018-04-13 15:44:17 +0300267 div = DIV_ROUND_UP(parent_rate, spi_hz);
268 if (div <= 1024) {
269 /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
270 if (!div_pow && div <= 32 && div > 2)
271 div_pow = 1;
Magnus Damm8051eff2009-11-26 11:10:05 +0000272
Vladimir Zapolskiy51093cb2018-04-13 15:44:17 +0300273 if (div_pow)
274 brps = (div + 1) >> div_pow;
275 else
276 brps = div;
277
278 for (; brps > 32; div_pow++)
279 brps = (brps + 1) >> 1;
280 } else {
281 /* Set transfer rate composite divisor to 2^5 * 32 = 1024 */
282 dev_err(&p->pdev->dev,
283 "Requested SPI transfer rate %d is too low\n", spi_hz);
284 div_pow = 5;
285 brps = 32;
286 }
287
288 scr = sh_msiof_spi_div_array[div_pow] | SCR_BRPS(brps);
Nobuhiro Iwamatsu65d56652015-01-30 15:11:54 +0900289 sh_msiof_write(p, TSCR, scr);
Geert Uytterhoevena6802cc2016-06-22 14:50:03 +0200290 if (!(p->master->flags & SPI_MASTER_MUST_TX))
Nobuhiro Iwamatsu65d56652015-01-30 15:11:54 +0900291 sh_msiof_write(p, RSCR, scr);
Magnus Damm8051eff2009-11-26 11:10:05 +0000292}
293
Yoshihiro Shimoda31106282014-12-19 17:15:53 +0900294static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
295{
296 /*
297 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
298 * b'000 : 0
299 * b'001 : 100
300 * b'010 : 200
301 * b'011 (SYNCDL only) : 300
302 * b'101 : 50
303 * b'110 : 150
304 */
305 if (dtdl_or_syncdl % 100)
306 return dtdl_or_syncdl / 100 + 5;
307 else
308 return dtdl_or_syncdl / 100;
309}
310
311static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
312{
313 u32 val;
314
315 if (!p->info)
316 return 0;
317
318 /* check if DTDL and SYNCDL is allowed value */
319 if (p->info->dtdl > 200 || p->info->syncdl > 300) {
320 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
321 return 0;
322 }
323
324 /* check if the sum of DTDL and SYNCDL becomes an integer value */
325 if ((p->info->dtdl + p->info->syncdl) % 100) {
326 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
327 return 0;
328 }
329
330 val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
331 val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
332
333 return val;
334}
335
Geert Uytterhoeven9cce8822017-12-13 20:05:11 +0100336static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss,
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +0100337 u32 cpol, u32 cpha,
Takashi Yoshii50a77992013-12-02 03:19:15 +0900338 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
Magnus Damm8051eff2009-11-26 11:10:05 +0000339{
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +0100340 u32 tmp;
Magnus Damm8051eff2009-11-26 11:10:05 +0000341 int edge;
342
343 /*
Markus Pietreke8708ef2010-02-02 11:29:15 +0900344 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
345 * 0 0 10 10 1 1
346 * 0 1 10 10 0 0
347 * 1 0 11 11 0 0
348 * 1 1 11 11 1 1
Magnus Damm8051eff2009-11-26 11:10:05 +0000349 */
Geert Uytterhoeven01cfef52014-02-20 15:43:03 +0100350 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
351 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
352 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
Yoshihiro Shimoda31106282014-12-19 17:15:53 +0900353 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
Geert Uytterhoeven9cce8822017-12-13 20:05:11 +0100354 if (spi_controller_is_slave(p->master)) {
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +0200355 sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON);
Geert Uytterhoeven9cce8822017-12-13 20:05:11 +0100356 } else {
357 sh_msiof_write(p, TMDR1,
358 tmp | MDR1_TRMD | TMDR1_PCON |
359 (ss < MAX_SS ? ss : 0) << TMDR1_SYNCCH_SHIFT);
360 }
Geert Uytterhoevena6802cc2016-06-22 14:50:03 +0200361 if (p->master->flags & SPI_MASTER_MUST_TX) {
Geert Uytterhoevenbeb74bb2014-02-25 11:21:10 +0100362 /* These bits are reserved if RX needs TX */
363 tmp &= ~0x0000ffff;
364 }
Geert Uytterhoeven01cfef52014-02-20 15:43:03 +0100365 sh_msiof_write(p, RMDR1, tmp);
Magnus Damm8051eff2009-11-26 11:10:05 +0000366
Geert Uytterhoeven01cfef52014-02-20 15:43:03 +0100367 tmp = 0;
368 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
369 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
Magnus Damm8051eff2009-11-26 11:10:05 +0000370
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +0100371 edge = cpol ^ !cpha;
Magnus Damm8051eff2009-11-26 11:10:05 +0000372
Geert Uytterhoeven01cfef52014-02-20 15:43:03 +0100373 tmp |= edge << CTR_TEDG_SHIFT;
374 tmp |= edge << CTR_REDG_SHIFT;
375 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
Magnus Damm8051eff2009-11-26 11:10:05 +0000376 sh_msiof_write(p, CTR, tmp);
377}
378
379static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
380 const void *tx_buf, void *rx_buf,
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +0100381 u32 bits, u32 words)
Magnus Damm8051eff2009-11-26 11:10:05 +0000382{
Geert Uytterhoeven01cfef52014-02-20 15:43:03 +0100383 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
Magnus Damm8051eff2009-11-26 11:10:05 +0000384
Geert Uytterhoevena6802cc2016-06-22 14:50:03 +0200385 if (tx_buf || (p->master->flags & SPI_MASTER_MUST_TX))
Magnus Damm8051eff2009-11-26 11:10:05 +0000386 sh_msiof_write(p, TMDR2, dr2);
387 else
Geert Uytterhoeven01cfef52014-02-20 15:43:03 +0100388 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
Magnus Damm8051eff2009-11-26 11:10:05 +0000389
390 if (rx_buf)
391 sh_msiof_write(p, RMDR2, dr2);
Magnus Damm8051eff2009-11-26 11:10:05 +0000392}
393
394static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
395{
Hiromitsu Yamasaki31a5fae2018-09-05 10:49:37 +0200396 sh_msiof_write(p, STR,
397 sh_msiof_read(p, STR) & ~(STR_TDREQ | STR_RDREQ));
Magnus Damm8051eff2009-11-26 11:10:05 +0000398}
399
400static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
401 const void *tx_buf, int words, int fs)
402{
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +0100403 const u8 *buf_8 = tx_buf;
Magnus Damm8051eff2009-11-26 11:10:05 +0000404 int k;
405
406 for (k = 0; k < words; k++)
407 sh_msiof_write(p, TFDR, buf_8[k] << fs);
408}
409
410static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
411 const void *tx_buf, int words, int fs)
412{
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +0100413 const u16 *buf_16 = tx_buf;
Magnus Damm8051eff2009-11-26 11:10:05 +0000414 int k;
415
416 for (k = 0; k < words; k++)
417 sh_msiof_write(p, TFDR, buf_16[k] << fs);
418}
419
420static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
421 const void *tx_buf, int words, int fs)
422{
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +0100423 const u16 *buf_16 = tx_buf;
Magnus Damm8051eff2009-11-26 11:10:05 +0000424 int k;
425
426 for (k = 0; k < words; k++)
427 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
428}
429
430static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
431 const void *tx_buf, int words, int fs)
432{
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +0100433 const u32 *buf_32 = tx_buf;
Magnus Damm8051eff2009-11-26 11:10:05 +0000434 int k;
435
436 for (k = 0; k < words; k++)
437 sh_msiof_write(p, TFDR, buf_32[k] << fs);
438}
439
440static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
441 const void *tx_buf, int words, int fs)
442{
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +0100443 const u32 *buf_32 = tx_buf;
Magnus Damm8051eff2009-11-26 11:10:05 +0000444 int k;
445
446 for (k = 0; k < words; k++)
447 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
448}
449
Guennadi Liakhovetski9dabb3f2011-01-21 16:56:42 +0100450static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
451 const void *tx_buf, int words, int fs)
452{
453 const u32 *buf_32 = tx_buf;
454 int k;
455
456 for (k = 0; k < words; k++)
457 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
458}
459
460static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
461 const void *tx_buf, int words, int fs)
462{
463 const u32 *buf_32 = tx_buf;
464 int k;
465
466 for (k = 0; k < words; k++)
467 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
468}
469
Magnus Damm8051eff2009-11-26 11:10:05 +0000470static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
471 void *rx_buf, int words, int fs)
472{
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +0100473 u8 *buf_8 = rx_buf;
Magnus Damm8051eff2009-11-26 11:10:05 +0000474 int k;
475
476 for (k = 0; k < words; k++)
477 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
478}
479
480static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
481 void *rx_buf, int words, int fs)
482{
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +0100483 u16 *buf_16 = rx_buf;
Magnus Damm8051eff2009-11-26 11:10:05 +0000484 int k;
485
486 for (k = 0; k < words; k++)
487 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
488}
489
490static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
491 void *rx_buf, int words, int fs)
492{
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +0100493 u16 *buf_16 = rx_buf;
Magnus Damm8051eff2009-11-26 11:10:05 +0000494 int k;
495
496 for (k = 0; k < words; k++)
497 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
498}
499
500static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
501 void *rx_buf, int words, int fs)
502{
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +0100503 u32 *buf_32 = rx_buf;
Magnus Damm8051eff2009-11-26 11:10:05 +0000504 int k;
505
506 for (k = 0; k < words; k++)
507 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
508}
509
510static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
511 void *rx_buf, int words, int fs)
512{
Guennadi Liakhovetskie2dbf5e2011-01-21 16:56:37 +0100513 u32 *buf_32 = rx_buf;
Magnus Damm8051eff2009-11-26 11:10:05 +0000514 int k;
515
516 for (k = 0; k < words; k++)
517 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
518}
519
Guennadi Liakhovetski9dabb3f2011-01-21 16:56:42 +0100520static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
521 void *rx_buf, int words, int fs)
522{
523 u32 *buf_32 = rx_buf;
524 int k;
525
526 for (k = 0; k < words; k++)
527 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
528}
529
530static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
531 void *rx_buf, int words, int fs)
532{
533 u32 *buf_32 = rx_buf;
534 int k;
535
536 for (k = 0; k < words; k++)
537 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
538}
539
Geert Uytterhoeven8d195342014-02-20 15:43:04 +0100540static int sh_msiof_spi_setup(struct spi_device *spi)
Magnus Damm8051eff2009-11-26 11:10:05 +0000541{
Geert Uytterhoeven8d195342014-02-20 15:43:04 +0100542 struct device_node *np = spi->master->dev.of_node;
Magnus Damm8051eff2009-11-26 11:10:05 +0000543 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
Geert Uytterhoeven7ff0b532017-12-13 20:05:10 +0100544 u32 clr, set, tmp;
Hisashi Nakamura015760562014-12-15 23:01:11 +0900545
Geert Uytterhoeven8d195342014-02-20 15:43:04 +0100546 if (!np) {
547 /*
548 * Use spi->controller_data for CS (same strategy as spi_gpio),
549 * if any. otherwise let HW control CS
550 */
551 spi->cs_gpio = (uintptr_t)spi->controller_data;
Magnus Damm8051eff2009-11-26 11:10:05 +0000552 }
553
Geert Uytterhoevenb8761432017-12-13 20:05:12 +0100554 if (gpio_is_valid(spi->cs_gpio)) {
555 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
Geert Uytterhoeven7ff0b532017-12-13 20:05:10 +0100556 return 0;
557 }
Magnus Damm8051eff2009-11-26 11:10:05 +0000558
Geert Uytterhoeven7ff0b532017-12-13 20:05:10 +0100559 if (spi_controller_is_slave(p->master))
560 return 0;
Geert Uytterhoeven1bd6363bc02014-02-25 11:21:13 +0100561
Geert Uytterhoeven7ff0b532017-12-13 20:05:10 +0100562 if (p->native_cs_inited &&
563 (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))
564 return 0;
Hisashi Nakamura015760562014-12-15 23:01:11 +0900565
Geert Uytterhoeven7ff0b532017-12-13 20:05:10 +0100566 /* Configure native chip select mode/polarity early */
567 clr = MDR1_SYNCMD_MASK;
Geert Uytterhoeven0921e112018-05-23 11:02:04 +0200568 set = MDR1_SYNCMD_SPI;
Geert Uytterhoeven7ff0b532017-12-13 20:05:10 +0100569 if (spi->mode & SPI_CS_HIGH)
570 clr |= BIT(MDR1_SYNCAC_SHIFT);
571 else
572 set |= BIT(MDR1_SYNCAC_SHIFT);
573 pm_runtime_get_sync(&p->pdev->dev);
574 tmp = sh_msiof_read(p, TMDR1) & ~clr;
Geert Uytterhoeven0921e112018-05-23 11:02:04 +0200575 sh_msiof_write(p, TMDR1, tmp | set | MDR1_TRMD | TMDR1_PCON);
576 tmp = sh_msiof_read(p, RMDR1) & ~clr;
577 sh_msiof_write(p, RMDR1, tmp | set);
Geert Uytterhoevenc8935ef2015-01-07 16:37:25 +0100578 pm_runtime_put(&p->pdev->dev);
Geert Uytterhoeven7ff0b532017-12-13 20:05:10 +0100579 p->native_cs_high = spi->mode & SPI_CS_HIGH;
580 p->native_cs_inited = true;
Geert Uytterhoeven1bd6363bc02014-02-25 11:21:13 +0100581 return 0;
Geert Uytterhoeven8d195342014-02-20 15:43:04 +0100582}
583
Geert Uytterhoevenc833ff72014-02-25 11:21:11 +0100584static int sh_msiof_prepare_message(struct spi_master *master,
585 struct spi_message *msg)
586{
587 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
588 const struct spi_device *spi = msg->spi;
Geert Uytterhoevenb8761432017-12-13 20:05:12 +0100589 u32 ss, cs_high;
Geert Uytterhoevenc833ff72014-02-25 11:21:11 +0100590
Geert Uytterhoevenc833ff72014-02-25 11:21:11 +0100591 /* Configure pins before asserting CS */
Geert Uytterhoevenb8761432017-12-13 20:05:12 +0100592 if (gpio_is_valid(spi->cs_gpio)) {
593 ss = p->unused_ss;
594 cs_high = p->native_cs_high;
595 } else {
596 ss = spi->chip_select;
597 cs_high = !!(spi->mode & SPI_CS_HIGH);
598 }
599 sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL),
Geert Uytterhoevenc833ff72014-02-25 11:21:11 +0100600 !!(spi->mode & SPI_CPHA),
601 !!(spi->mode & SPI_3WIRE),
Geert Uytterhoevenb8761432017-12-13 20:05:12 +0100602 !!(spi->mode & SPI_LSB_FIRST), cs_high);
Geert Uytterhoevenc833ff72014-02-25 11:21:11 +0100603 return 0;
Magnus Damm8051eff2009-11-26 11:10:05 +0000604}
605
Geert Uytterhoeven76c02e72014-06-20 12:16:17 +0200606static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
607{
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +0200608 bool slave = spi_controller_is_slave(p->master);
609 int ret = 0;
Geert Uytterhoeven76c02e72014-06-20 12:16:17 +0200610
611 /* setup clock and rx/tx signals */
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +0200612 if (!slave)
613 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
Geert Uytterhoeven76c02e72014-06-20 12:16:17 +0200614 if (rx_buf && !ret)
615 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
616 if (!ret)
617 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
618
619 /* start by setting frame bit */
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +0200620 if (!ret && !slave)
Geert Uytterhoeven76c02e72014-06-20 12:16:17 +0200621 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
622
623 return ret;
624}
625
626static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
627{
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +0200628 bool slave = spi_controller_is_slave(p->master);
629 int ret = 0;
Geert Uytterhoeven76c02e72014-06-20 12:16:17 +0200630
631 /* shut down frame, rx/tx and clock signals */
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +0200632 if (!slave)
633 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
Geert Uytterhoeven76c02e72014-06-20 12:16:17 +0200634 if (!ret)
635 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
636 if (rx_buf && !ret)
637 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +0200638 if (!ret && !slave)
Geert Uytterhoeven76c02e72014-06-20 12:16:17 +0200639 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
640
641 return ret;
642}
643
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +0200644static int sh_msiof_slave_abort(struct spi_master *master)
645{
646 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
647
648 p->slave_aborted = true;
649 complete(&p->done);
Geert Uytterhoeven08ba7ae2018-06-13 10:41:15 +0200650 complete(&p->done_txdma);
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +0200651 return 0;
652}
653
Geert Uytterhoeven08ba7ae2018-06-13 10:41:15 +0200654static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p,
655 struct completion *x)
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +0200656{
657 if (spi_controller_is_slave(p->master)) {
Geert Uytterhoeven08ba7ae2018-06-13 10:41:15 +0200658 if (wait_for_completion_interruptible(x) ||
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +0200659 p->slave_aborted) {
660 dev_dbg(&p->pdev->dev, "interrupted\n");
661 return -EINTR;
662 }
663 } else {
Geert Uytterhoeven08ba7ae2018-06-13 10:41:15 +0200664 if (!wait_for_completion_timeout(x, HZ)) {
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +0200665 dev_err(&p->pdev->dev, "timeout\n");
666 return -ETIMEDOUT;
667 }
668 }
669
670 return 0;
671}
672
Magnus Damm8051eff2009-11-26 11:10:05 +0000673static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
674 void (*tx_fifo)(struct sh_msiof_spi_priv *,
675 const void *, int, int),
676 void (*rx_fifo)(struct sh_msiof_spi_priv *,
677 void *, int, int),
678 const void *tx_buf, void *rx_buf,
679 int words, int bits)
680{
681 int fifo_shift;
682 int ret;
683
684 /* limit maximum word transfer to rx/tx fifo size */
685 if (tx_buf)
686 words = min_t(int, words, p->tx_fifo_size);
687 if (rx_buf)
688 words = min_t(int, words, p->rx_fifo_size);
689
690 /* the fifo contents need shifting */
691 fifo_shift = 32 - bits;
692
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200693 /* default FIFO watermarks for PIO */
694 sh_msiof_write(p, FCTR, 0);
695
Magnus Damm8051eff2009-11-26 11:10:05 +0000696 /* setup msiof transfer mode registers */
697 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200698 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
Magnus Damm8051eff2009-11-26 11:10:05 +0000699
700 /* write tx fifo */
701 if (tx_buf)
702 tx_fifo(p, tx_buf, words, fifo_shift);
703
Wolfram Sang16735d02013-11-14 14:32:02 -0800704 reinit_completion(&p->done);
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +0200705 p->slave_aborted = false;
Geert Uytterhoeven76c02e72014-06-20 12:16:17 +0200706
707 ret = sh_msiof_spi_start(p, rx_buf);
Magnus Damm8051eff2009-11-26 11:10:05 +0000708 if (ret) {
709 dev_err(&p->pdev->dev, "failed to start hardware\n");
Geert Uytterhoeven75b82e22014-06-20 12:16:18 +0200710 goto stop_ier;
Magnus Damm8051eff2009-11-26 11:10:05 +0000711 }
712
713 /* wait for tx fifo to be emptied / rx fifo to be filled */
Geert Uytterhoeven08ba7ae2018-06-13 10:41:15 +0200714 ret = sh_msiof_wait_for_completion(p, &p->done);
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +0200715 if (ret)
Geert Uytterhoeven75b82e22014-06-20 12:16:18 +0200716 goto stop_reset;
Magnus Damm8051eff2009-11-26 11:10:05 +0000717
718 /* read rx fifo */
719 if (rx_buf)
720 rx_fifo(p, rx_buf, words, fifo_shift);
721
722 /* clear status bits */
723 sh_msiof_reset_str(p);
724
Geert Uytterhoeven76c02e72014-06-20 12:16:17 +0200725 ret = sh_msiof_spi_stop(p, rx_buf);
Magnus Damm8051eff2009-11-26 11:10:05 +0000726 if (ret) {
727 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
Geert Uytterhoeven75b82e22014-06-20 12:16:18 +0200728 return ret;
Magnus Damm8051eff2009-11-26 11:10:05 +0000729 }
730
731 return words;
732
Geert Uytterhoeven75b82e22014-06-20 12:16:18 +0200733stop_reset:
734 sh_msiof_reset_str(p);
735 sh_msiof_spi_stop(p, rx_buf);
736stop_ier:
Magnus Damm8051eff2009-11-26 11:10:05 +0000737 sh_msiof_write(p, IER, 0);
738 return ret;
739}
740
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200741static void sh_msiof_dma_complete(void *arg)
742{
Geert Uytterhoeven08ba7ae2018-06-13 10:41:15 +0200743 complete(arg);
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200744}
745
746static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
747 void *rx, unsigned int len)
748{
749 u32 ier_bits = 0;
750 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
751 dma_cookie_t cookie;
752 int ret;
753
Geert Uytterhoeven3e81b592014-08-06 14:59:03 +0200754 /* First prepare and submit the DMA request(s), as this may fail */
755 if (rx) {
756 ier_bits |= IER_RDREQE | IER_RDMAE;
757 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
Geert Uytterhoevenda779512018-03-21 09:07:23 +0100758 p->rx_dma_addr, len, DMA_DEV_TO_MEM,
Geert Uytterhoeven3e81b592014-08-06 14:59:03 +0200759 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Geert Uytterhoevena5e7c712014-08-07 14:07:42 +0200760 if (!desc_rx)
761 return -EAGAIN;
Geert Uytterhoeven3e81b592014-08-06 14:59:03 +0200762
763 desc_rx->callback = sh_msiof_dma_complete;
Geert Uytterhoeven08ba7ae2018-06-13 10:41:15 +0200764 desc_rx->callback_param = &p->done;
Geert Uytterhoeven3e81b592014-08-06 14:59:03 +0200765 cookie = dmaengine_submit(desc_rx);
Geert Uytterhoevena5e7c712014-08-07 14:07:42 +0200766 if (dma_submit_error(cookie))
767 return cookie;
Geert Uytterhoeven3e81b592014-08-06 14:59:03 +0200768 }
769
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200770 if (tx) {
771 ier_bits |= IER_TDREQE | IER_TDMAE;
Geert Uytterhoeven5dabcf22014-07-11 17:56:22 +0200772 dma_sync_single_for_device(p->master->dma_tx->device->dev,
773 p->tx_dma_addr, len, DMA_TO_DEVICE);
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200774 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
Geert Uytterhoevenda779512018-03-21 09:07:23 +0100775 p->tx_dma_addr, len, DMA_MEM_TO_DEV,
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200776 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Geert Uytterhoeven3e81b592014-08-06 14:59:03 +0200777 if (!desc_tx) {
778 ret = -EAGAIN;
779 goto no_dma_tx;
780 }
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200781
Geert Uytterhoeven08ba7ae2018-06-13 10:41:15 +0200782 desc_tx->callback = sh_msiof_dma_complete;
783 desc_tx->callback_param = &p->done_txdma;
Geert Uytterhoeven3e81b592014-08-06 14:59:03 +0200784 cookie = dmaengine_submit(desc_tx);
785 if (dma_submit_error(cookie)) {
786 ret = cookie;
787 goto no_dma_tx;
788 }
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200789 }
Geert Uytterhoeven279d2372014-07-09 12:26:23 +0200790
791 /* 1 stage FIFO watermarks for DMA */
792 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
793
794 /* setup msiof transfer mode registers (32-bit words) */
795 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
796
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200797 sh_msiof_write(p, IER, ier_bits);
798
799 reinit_completion(&p->done);
Geert Uytterhoeven08ba7ae2018-06-13 10:41:15 +0200800 if (tx)
801 reinit_completion(&p->done_txdma);
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +0200802 p->slave_aborted = false;
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200803
Geert Uytterhoeven3e81b592014-08-06 14:59:03 +0200804 /* Now start DMA */
Geert Uytterhoeven3e81b592014-08-06 14:59:03 +0200805 if (rx)
Geert Uytterhoeven7a9f9572014-08-07 14:07:43 +0200806 dma_async_issue_pending(p->master->dma_rx);
807 if (tx)
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200808 dma_async_issue_pending(p->master->dma_tx);
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200809
810 ret = sh_msiof_spi_start(p, rx);
811 if (ret) {
812 dev_err(&p->pdev->dev, "failed to start hardware\n");
Geert Uytterhoeven3e81b592014-08-06 14:59:03 +0200813 goto stop_dma;
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200814 }
815
Geert Uytterhoeven08ba7ae2018-06-13 10:41:15 +0200816 if (tx) {
817 /* wait for tx DMA completion */
818 ret = sh_msiof_wait_for_completion(p, &p->done_txdma);
819 if (ret)
820 goto stop_reset;
821 }
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200822
Geert Uytterhoeven08ba7ae2018-06-13 10:41:15 +0200823 if (rx) {
824 /* wait for rx DMA completion */
825 ret = sh_msiof_wait_for_completion(p, &p->done);
826 if (ret)
827 goto stop_reset;
Geert Uytterhoeven89434c32018-01-03 18:11:14 +0100828
Geert Uytterhoeven08ba7ae2018-06-13 10:41:15 +0200829 sh_msiof_write(p, IER, 0);
830 } else {
Geert Uytterhoeven89434c32018-01-03 18:11:14 +0100831 /* wait for tx fifo to be emptied */
Geert Uytterhoeven08ba7ae2018-06-13 10:41:15 +0200832 sh_msiof_write(p, IER, IER_TEOFE);
833 ret = sh_msiof_wait_for_completion(p, &p->done);
Geert Uytterhoeven89434c32018-01-03 18:11:14 +0100834 if (ret)
835 goto stop_reset;
836 }
837
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200838 /* clear status bits */
839 sh_msiof_reset_str(p);
840
841 ret = sh_msiof_spi_stop(p, rx);
842 if (ret) {
843 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
844 return ret;
845 }
846
847 if (rx)
Geert Uytterhoeven5dabcf22014-07-11 17:56:22 +0200848 dma_sync_single_for_cpu(p->master->dma_rx->device->dev,
849 p->rx_dma_addr, len,
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200850 DMA_FROM_DEVICE);
851
852 return 0;
853
854stop_reset:
855 sh_msiof_reset_str(p);
856 sh_msiof_spi_stop(p, rx);
Geert Uytterhoeven3e81b592014-08-06 14:59:03 +0200857stop_dma:
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200858 if (tx)
859 dmaengine_terminate_all(p->master->dma_tx);
Geert Uytterhoeven3e81b592014-08-06 14:59:03 +0200860no_dma_tx:
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200861 if (rx)
862 dmaengine_terminate_all(p->master->dma_rx);
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200863 sh_msiof_write(p, IER, 0);
864 return ret;
865}
866
867static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
868{
869 /* src or dst can be unaligned, but not both */
870 if ((unsigned long)src & 3) {
871 while (words--) {
872 *dst++ = swab32(get_unaligned(src));
873 src++;
874 }
875 } else if ((unsigned long)dst & 3) {
876 while (words--) {
877 put_unaligned(swab32(*src++), dst);
878 dst++;
879 }
880 } else {
881 while (words--)
882 *dst++ = swab32(*src++);
883 }
884}
885
886static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
887{
888 /* src or dst can be unaligned, but not both */
889 if ((unsigned long)src & 3) {
890 while (words--) {
891 *dst++ = swahw32(get_unaligned(src));
892 src++;
893 }
894 } else if ((unsigned long)dst & 3) {
895 while (words--) {
896 put_unaligned(swahw32(*src++), dst);
897 dst++;
898 }
899 } else {
900 while (words--)
901 *dst++ = swahw32(*src++);
902 }
903}
904
905static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
906{
907 memcpy(dst, src, words * 4);
908}
909
Geert Uytterhoeven1bd6363bc02014-02-25 11:21:13 +0100910static int sh_msiof_transfer_one(struct spi_master *master,
911 struct spi_device *spi,
912 struct spi_transfer *t)
Magnus Damm8051eff2009-11-26 11:10:05 +0000913{
Geert Uytterhoeven1bd6363bc02014-02-25 11:21:13 +0100914 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200915 void (*copy32)(u32 *, const u32 *, unsigned int);
Magnus Damm8051eff2009-11-26 11:10:05 +0000916 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
917 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
Geert Uytterhoeven0312d592014-06-20 12:16:19 +0200918 const void *tx_buf = t->tx_buf;
919 void *rx_buf = t->rx_buf;
920 unsigned int len = t->len;
921 unsigned int bits = t->bits_per_word;
922 unsigned int bytes_per_word;
923 unsigned int words;
Magnus Damm8051eff2009-11-26 11:10:05 +0000924 int n;
Guennadi Liakhovetski9dabb3f2011-01-21 16:56:42 +0100925 bool swab;
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200926 int ret;
Magnus Damm8051eff2009-11-26 11:10:05 +0000927
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200928 /* setup clocks (clock already enabled in chipselect()) */
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +0200929 if (!spi_controller_is_slave(p->master))
930 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200931
932 while (master->dma_tx && len > 15) {
933 /*
934 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
935 * words, with byte resp. word swapping.
936 */
Koji Matsuokafe78d0b2015-06-15 02:25:05 +0900937 unsigned int l = 0;
938
939 if (tx_buf)
940 l = min(len, p->tx_fifo_size * 4);
941 if (rx_buf)
942 l = min(len, p->rx_fifo_size * 4);
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200943
944 if (bits <= 8) {
945 if (l & 3)
946 break;
947 copy32 = copy_bswap32;
948 } else if (bits <= 16) {
Hiromitsu Yamasaki36735782017-11-02 10:32:36 +0100949 if (l & 3)
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200950 break;
951 copy32 = copy_wswap32;
952 } else {
953 copy32 = copy_plain32;
954 }
955
956 if (tx_buf)
957 copy32(p->tx_dma_page, tx_buf, l / 4);
958
959 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
Geert Uytterhoeven279d2372014-07-09 12:26:23 +0200960 if (ret == -EAGAIN) {
Geert Uytterhoeven5d8e6142017-11-30 14:38:50 +0100961 dev_warn_once(&p->pdev->dev,
962 "DMA not available, falling back to PIO\n");
Geert Uytterhoeven279d2372014-07-09 12:26:23 +0200963 break;
964 }
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +0200965 if (ret)
966 return ret;
967
968 if (rx_buf) {
969 copy32(rx_buf, p->rx_dma_page, l / 4);
970 rx_buf += l;
971 }
972 if (tx_buf)
973 tx_buf += l;
974
975 len -= l;
976 if (!len)
977 return 0;
978 }
Magnus Damm8051eff2009-11-26 11:10:05 +0000979
Hoan Nguyen An916d9802018-12-20 17:48:42 +0900980 if (bits <= 8 && len > 15) {
Guennadi Liakhovetski9dabb3f2011-01-21 16:56:42 +0100981 bits = 32;
982 swab = true;
983 } else {
984 swab = false;
985 }
986
Magnus Damm8051eff2009-11-26 11:10:05 +0000987 /* setup bytes per word and fifo read/write functions */
988 if (bits <= 8) {
989 bytes_per_word = 1;
990 tx_fifo = sh_msiof_spi_write_fifo_8;
991 rx_fifo = sh_msiof_spi_read_fifo_8;
992 } else if (bits <= 16) {
993 bytes_per_word = 2;
Geert Uytterhoeven0312d592014-06-20 12:16:19 +0200994 if ((unsigned long)tx_buf & 0x01)
Magnus Damm8051eff2009-11-26 11:10:05 +0000995 tx_fifo = sh_msiof_spi_write_fifo_16u;
996 else
997 tx_fifo = sh_msiof_spi_write_fifo_16;
998
Geert Uytterhoeven0312d592014-06-20 12:16:19 +0200999 if ((unsigned long)rx_buf & 0x01)
Magnus Damm8051eff2009-11-26 11:10:05 +00001000 rx_fifo = sh_msiof_spi_read_fifo_16u;
1001 else
1002 rx_fifo = sh_msiof_spi_read_fifo_16;
Guennadi Liakhovetski9dabb3f2011-01-21 16:56:42 +01001003 } else if (swab) {
1004 bytes_per_word = 4;
Geert Uytterhoeven0312d592014-06-20 12:16:19 +02001005 if ((unsigned long)tx_buf & 0x03)
Guennadi Liakhovetski9dabb3f2011-01-21 16:56:42 +01001006 tx_fifo = sh_msiof_spi_write_fifo_s32u;
1007 else
1008 tx_fifo = sh_msiof_spi_write_fifo_s32;
1009
Geert Uytterhoeven0312d592014-06-20 12:16:19 +02001010 if ((unsigned long)rx_buf & 0x03)
Guennadi Liakhovetski9dabb3f2011-01-21 16:56:42 +01001011 rx_fifo = sh_msiof_spi_read_fifo_s32u;
1012 else
1013 rx_fifo = sh_msiof_spi_read_fifo_s32;
Magnus Damm8051eff2009-11-26 11:10:05 +00001014 } else {
1015 bytes_per_word = 4;
Geert Uytterhoeven0312d592014-06-20 12:16:19 +02001016 if ((unsigned long)tx_buf & 0x03)
Magnus Damm8051eff2009-11-26 11:10:05 +00001017 tx_fifo = sh_msiof_spi_write_fifo_32u;
1018 else
1019 tx_fifo = sh_msiof_spi_write_fifo_32;
1020
Geert Uytterhoeven0312d592014-06-20 12:16:19 +02001021 if ((unsigned long)rx_buf & 0x03)
Magnus Damm8051eff2009-11-26 11:10:05 +00001022 rx_fifo = sh_msiof_spi_read_fifo_32u;
1023 else
1024 rx_fifo = sh_msiof_spi_read_fifo_32;
1025 }
1026
Magnus Damm8051eff2009-11-26 11:10:05 +00001027 /* transfer in fifo sized chunks */
Geert Uytterhoeven0312d592014-06-20 12:16:19 +02001028 words = len / bytes_per_word;
Magnus Damm8051eff2009-11-26 11:10:05 +00001029
Geert Uytterhoeven0312d592014-06-20 12:16:19 +02001030 while (words > 0) {
1031 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
Magnus Damm8051eff2009-11-26 11:10:05 +00001032 words, bits);
1033 if (n < 0)
Geert Uytterhoeven75b82e22014-06-20 12:16:18 +02001034 return n;
Magnus Damm8051eff2009-11-26 11:10:05 +00001035
Geert Uytterhoeven0312d592014-06-20 12:16:19 +02001036 if (tx_buf)
1037 tx_buf += n * bytes_per_word;
1038 if (rx_buf)
1039 rx_buf += n * bytes_per_word;
Magnus Damm8051eff2009-11-26 11:10:05 +00001040 words -= n;
Hoan Nguyen An916d9802018-12-20 17:48:42 +09001041
1042 if (words == 0 && (len % bytes_per_word)) {
1043 words = len % bytes_per_word;
1044 bits = t->bits_per_word;
1045 bytes_per_word = 1;
1046 tx_fifo = sh_msiof_spi_write_fifo_8;
1047 rx_fifo = sh_msiof_spi_read_fifo_8;
1048 }
Magnus Damm8051eff2009-11-26 11:10:05 +00001049 }
1050
Magnus Damm8051eff2009-11-26 11:10:05 +00001051 return 0;
1052}
1053
Geert Uytterhoeven50a7e232014-02-25 11:21:09 +01001054static const struct sh_msiof_chipdata sh_data = {
1055 .tx_fifo_size = 64,
1056 .rx_fifo_size = 64,
Geert Uytterhoevenbeb74bb2014-02-25 11:21:10 +01001057 .master_flags = 0,
Vladimir Zapolskiy51093cb2018-04-13 15:44:17 +03001058 .min_div_pow = 0,
Geert Uytterhoevenbeb74bb2014-02-25 11:21:10 +01001059};
1060
Geert Uytterhoeven61a8dec2017-07-12 12:26:01 +02001061static const struct sh_msiof_chipdata rcar_gen2_data = {
Geert Uytterhoevenbeb74bb2014-02-25 11:21:10 +01001062 .tx_fifo_size = 64,
Koji Matsuokafe78d0b2015-06-15 02:25:05 +09001063 .rx_fifo_size = 64,
Geert Uytterhoevenbeb74bb2014-02-25 11:21:10 +01001064 .master_flags = SPI_MASTER_MUST_TX,
Vladimir Zapolskiy51093cb2018-04-13 15:44:17 +03001065 .min_div_pow = 0,
Geert Uytterhoeven61a8dec2017-07-12 12:26:01 +02001066};
1067
1068static const struct sh_msiof_chipdata rcar_gen3_data = {
1069 .tx_fifo_size = 64,
1070 .rx_fifo_size = 64,
1071 .master_flags = SPI_MASTER_MUST_TX,
Vladimir Zapolskiy51093cb2018-04-13 15:44:17 +03001072 .min_div_pow = 1,
Geert Uytterhoeven50a7e232014-02-25 11:21:09 +01001073};
1074
1075static const struct of_device_id sh_msiof_match[] = {
Geert Uytterhoeven50a7e232014-02-25 11:21:09 +01001076 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
Fabrizio Castrobdacfc72017-09-25 09:54:19 +01001077 { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data },
1078 { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data },
Geert Uytterhoeven61a8dec2017-07-12 12:26:01 +02001079 { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data },
1080 { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data },
1081 { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data },
1082 { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data },
1083 { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data },
1084 { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
1085 { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data },
1086 { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
Simon Horman264c3e82016-12-20 11:21:16 +01001087 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */
Geert Uytterhoeven50a7e232014-02-25 11:21:09 +01001088 {},
1089};
1090MODULE_DEVICE_TABLE(of, sh_msiof_match);
1091
Bastian Hechtcf9c86e2012-12-12 12:54:48 +01001092#ifdef CONFIG_OF
1093static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1094{
1095 struct sh_msiof_spi_info *info;
1096 struct device_node *np = dev->of_node;
Geert Uytterhoeven32d3b2d2014-02-25 11:21:08 +01001097 u32 num_cs = 1;
Bastian Hechtcf9c86e2012-12-12 12:54:48 +01001098
1099 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
Jingoo Han1e8231b2014-04-29 17:21:25 +09001100 if (!info)
Bastian Hechtcf9c86e2012-12-12 12:54:48 +01001101 return NULL;
Bastian Hechtcf9c86e2012-12-12 12:54:48 +01001102
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +02001103 info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE
1104 : MSIOF_SPI_MASTER;
1105
Bastian Hechtcf9c86e2012-12-12 12:54:48 +01001106 /* Parse the MSIOF properties */
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +02001107 if (info->mode == MSIOF_SPI_MASTER)
1108 of_property_read_u32(np, "num-cs", &num_cs);
Bastian Hechtcf9c86e2012-12-12 12:54:48 +01001109 of_property_read_u32(np, "renesas,tx-fifo-size",
1110 &info->tx_fifo_override);
1111 of_property_read_u32(np, "renesas,rx-fifo-size",
1112 &info->rx_fifo_override);
Yoshihiro Shimoda31106282014-12-19 17:15:53 +09001113 of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1114 of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
Bastian Hechtcf9c86e2012-12-12 12:54:48 +01001115
1116 info->num_chipselect = num_cs;
1117
1118 return info;
1119}
1120#else
1121static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1122{
1123 return NULL;
1124}
1125#endif
1126
Geert Uytterhoevenb8761432017-12-13 20:05:12 +01001127static int sh_msiof_get_cs_gpios(struct sh_msiof_spi_priv *p)
1128{
1129 struct device *dev = &p->pdev->dev;
1130 unsigned int used_ss_mask = 0;
1131 unsigned int cs_gpios = 0;
1132 unsigned int num_cs, i;
1133 int ret;
1134
1135 ret = gpiod_count(dev, "cs");
1136 if (ret <= 0)
1137 return 0;
1138
1139 num_cs = max_t(unsigned int, ret, p->master->num_chipselect);
1140 for (i = 0; i < num_cs; i++) {
1141 struct gpio_desc *gpiod;
1142
1143 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1144 if (!IS_ERR(gpiod)) {
1145 cs_gpios++;
1146 continue;
1147 }
1148
1149 if (PTR_ERR(gpiod) != -ENOENT)
1150 return PTR_ERR(gpiod);
1151
1152 if (i >= MAX_SS) {
1153 dev_err(dev, "Invalid native chip select %d\n", i);
1154 return -EINVAL;
1155 }
1156 used_ss_mask |= BIT(i);
1157 }
1158 p->unused_ss = ffz(used_ss_mask);
1159 if (cs_gpios && p->unused_ss >= MAX_SS) {
1160 dev_err(dev, "No unused native chip select available\n");
1161 return -EINVAL;
1162 }
1163 return 0;
1164}
1165
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001166static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
1167 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
1168{
1169 dma_cap_mask_t mask;
1170 struct dma_chan *chan;
1171 struct dma_slave_config cfg;
1172 int ret;
1173
1174 dma_cap_zero(mask);
1175 dma_cap_set(DMA_SLAVE, mask);
1176
Geert Uytterhoevena6be4de2014-08-06 14:59:05 +02001177 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1178 (void *)(unsigned long)id, dev,
1179 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001180 if (!chan) {
Geert Uytterhoevena6be4de2014-08-06 14:59:05 +02001181 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001182 return NULL;
1183 }
1184
1185 memset(&cfg, 0, sizeof(cfg));
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001186 cfg.direction = dir;
Geert Uytterhoeven52fba2b2014-08-06 14:59:04 +02001187 if (dir == DMA_MEM_TO_DEV) {
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001188 cfg.dst_addr = port_addr;
Geert Uytterhoeven52fba2b2014-08-06 14:59:04 +02001189 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1190 } else {
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001191 cfg.src_addr = port_addr;
Geert Uytterhoeven52fba2b2014-08-06 14:59:04 +02001192 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1193 }
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001194
1195 ret = dmaengine_slave_config(chan, &cfg);
1196 if (ret) {
1197 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1198 dma_release_channel(chan);
1199 return NULL;
1200 }
1201
1202 return chan;
1203}
1204
1205static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1206{
1207 struct platform_device *pdev = p->pdev;
1208 struct device *dev = &pdev->dev;
1209 const struct sh_msiof_spi_info *info = dev_get_platdata(dev);
Geert Uytterhoevena6be4de2014-08-06 14:59:05 +02001210 unsigned int dma_tx_id, dma_rx_id;
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001211 const struct resource *res;
1212 struct spi_master *master;
Geert Uytterhoeven5dabcf22014-07-11 17:56:22 +02001213 struct device *tx_dev, *rx_dev;
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001214
Geert Uytterhoevena6be4de2014-08-06 14:59:05 +02001215 if (dev->of_node) {
1216 /* In the OF case we will get the slave IDs from the DT */
1217 dma_tx_id = 0;
1218 dma_rx_id = 0;
1219 } else if (info && info->dma_tx_id && info->dma_rx_id) {
1220 dma_tx_id = info->dma_tx_id;
1221 dma_rx_id = info->dma_rx_id;
1222 } else {
1223 /* The driver assumes no error */
1224 return 0;
1225 }
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001226
1227 /* The DMA engine uses the second register set, if present */
1228 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1229 if (!res)
1230 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1231
1232 master = p->master;
1233 master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
Geert Uytterhoevena6be4de2014-08-06 14:59:05 +02001234 dma_tx_id,
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001235 res->start + TFDR);
1236 if (!master->dma_tx)
1237 return -ENODEV;
1238
1239 master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
Geert Uytterhoevena6be4de2014-08-06 14:59:05 +02001240 dma_rx_id,
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001241 res->start + RFDR);
1242 if (!master->dma_rx)
1243 goto free_tx_chan;
1244
1245 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1246 if (!p->tx_dma_page)
1247 goto free_rx_chan;
1248
1249 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1250 if (!p->rx_dma_page)
1251 goto free_tx_page;
1252
Geert Uytterhoeven5dabcf22014-07-11 17:56:22 +02001253 tx_dev = master->dma_tx->device->dev;
1254 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001255 DMA_TO_DEVICE);
Geert Uytterhoeven5dabcf22014-07-11 17:56:22 +02001256 if (dma_mapping_error(tx_dev, p->tx_dma_addr))
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001257 goto free_rx_page;
1258
Geert Uytterhoeven5dabcf22014-07-11 17:56:22 +02001259 rx_dev = master->dma_rx->device->dev;
1260 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001261 DMA_FROM_DEVICE);
Geert Uytterhoeven5dabcf22014-07-11 17:56:22 +02001262 if (dma_mapping_error(rx_dev, p->rx_dma_addr))
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001263 goto unmap_tx_page;
1264
1265 dev_info(dev, "DMA available");
1266 return 0;
1267
1268unmap_tx_page:
Geert Uytterhoeven5dabcf22014-07-11 17:56:22 +02001269 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001270free_rx_page:
1271 free_page((unsigned long)p->rx_dma_page);
1272free_tx_page:
1273 free_page((unsigned long)p->tx_dma_page);
1274free_rx_chan:
1275 dma_release_channel(master->dma_rx);
1276free_tx_chan:
1277 dma_release_channel(master->dma_tx);
1278 master->dma_tx = NULL;
1279 return -ENODEV;
1280}
1281
1282static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1283{
1284 struct spi_master *master = p->master;
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001285
1286 if (!master->dma_tx)
1287 return;
1288
Geert Uytterhoeven5dabcf22014-07-11 17:56:22 +02001289 dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr,
1290 PAGE_SIZE, DMA_FROM_DEVICE);
1291 dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr,
1292 PAGE_SIZE, DMA_TO_DEVICE);
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001293 free_page((unsigned long)p->rx_dma_page);
1294 free_page((unsigned long)p->tx_dma_page);
1295 dma_release_channel(master->dma_rx);
1296 dma_release_channel(master->dma_tx);
1297}
1298
Magnus Damm8051eff2009-11-26 11:10:05 +00001299static int sh_msiof_spi_probe(struct platform_device *pdev)
1300{
1301 struct resource *r;
1302 struct spi_master *master;
Geert Uytterhoevena6802cc2016-06-22 14:50:03 +02001303 const struct sh_msiof_chipdata *chipdata;
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +02001304 struct sh_msiof_spi_info *info;
Magnus Damm8051eff2009-11-26 11:10:05 +00001305 struct sh_msiof_spi_priv *p;
Magnus Damm8051eff2009-11-26 11:10:05 +00001306 int i;
1307 int ret;
1308
Geert Uytterhoevenecb15962017-10-04 14:20:27 +02001309 chipdata = of_device_get_match_data(&pdev->dev);
1310 if (chipdata) {
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +02001311 info = sh_msiof_spi_parse_dt(&pdev->dev);
1312 } else {
1313 chipdata = (const void *)pdev->id_entry->driver_data;
1314 info = dev_get_platdata(&pdev->dev);
1315 }
1316
1317 if (!info) {
1318 dev_err(&pdev->dev, "failed to obtain device info\n");
1319 return -ENXIO;
1320 }
1321
1322 if (info->mode == MSIOF_SPI_SLAVE)
1323 master = spi_alloc_slave(&pdev->dev,
1324 sizeof(struct sh_msiof_spi_priv));
1325 else
1326 master = spi_alloc_master(&pdev->dev,
1327 sizeof(struct sh_msiof_spi_priv));
Geert Uytterhoevene7ad4a72017-01-04 11:15:08 +01001328 if (master == NULL)
Laurent Pinchartb4dd05de32013-11-28 02:39:42 +01001329 return -ENOMEM;
Magnus Damm8051eff2009-11-26 11:10:05 +00001330
1331 p = spi_master_get_devdata(master);
1332
1333 platform_set_drvdata(pdev, p);
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001334 p->master = master;
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +02001335 p->info = info;
Vladimir Zapolskiy51093cb2018-04-13 15:44:17 +03001336 p->min_div_pow = chipdata->min_div_pow;
Bastian Hechtcf9c86e2012-12-12 12:54:48 +01001337
Magnus Damm8051eff2009-11-26 11:10:05 +00001338 init_completion(&p->done);
Geert Uytterhoeven08ba7ae2018-06-13 10:41:15 +02001339 init_completion(&p->done_txdma);
Magnus Damm8051eff2009-11-26 11:10:05 +00001340
Laurent Pinchartb4dd05de32013-11-28 02:39:42 +01001341 p->clk = devm_clk_get(&pdev->dev, NULL);
Magnus Damm8051eff2009-11-26 11:10:05 +00001342 if (IS_ERR(p->clk)) {
Bastian Hecht078b6ea2012-11-07 12:40:04 +01001343 dev_err(&pdev->dev, "cannot get clock\n");
Magnus Damm8051eff2009-11-26 11:10:05 +00001344 ret = PTR_ERR(p->clk);
1345 goto err1;
1346 }
1347
Magnus Damm8051eff2009-11-26 11:10:05 +00001348 i = platform_get_irq(pdev, 0);
Laurent Pinchartb4dd05de32013-11-28 02:39:42 +01001349 if (i < 0) {
Sergei Shtylyovf34c6e62018-10-12 22:48:22 +03001350 dev_err(&pdev->dev, "cannot get IRQ\n");
1351 ret = i;
Laurent Pinchartb4dd05de32013-11-28 02:39:42 +01001352 goto err1;
Magnus Damm8051eff2009-11-26 11:10:05 +00001353 }
1354
Laurent Pinchartb4dd05de32013-11-28 02:39:42 +01001355 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1356 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
1357 if (IS_ERR(p->mapbase)) {
1358 ret = PTR_ERR(p->mapbase);
1359 goto err1;
1360 }
1361
1362 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1363 dev_name(&pdev->dev), p);
Magnus Damm8051eff2009-11-26 11:10:05 +00001364 if (ret) {
1365 dev_err(&pdev->dev, "unable to request irq\n");
Laurent Pinchartb4dd05de32013-11-28 02:39:42 +01001366 goto err1;
Magnus Damm8051eff2009-11-26 11:10:05 +00001367 }
1368
1369 p->pdev = pdev;
1370 pm_runtime_enable(&pdev->dev);
1371
Magnus Damm8051eff2009-11-26 11:10:05 +00001372 /* Platform data may override FIFO sizes */
Geert Uytterhoevena6802cc2016-06-22 14:50:03 +02001373 p->tx_fifo_size = chipdata->tx_fifo_size;
1374 p->rx_fifo_size = chipdata->rx_fifo_size;
Magnus Damm8051eff2009-11-26 11:10:05 +00001375 if (p->info->tx_fifo_override)
1376 p->tx_fifo_size = p->info->tx_fifo_override;
1377 if (p->info->rx_fifo_override)
1378 p->rx_fifo_size = p->info->rx_fifo_override;
1379
Geert Uytterhoevenb8761432017-12-13 20:05:12 +01001380 /* Setup GPIO chip selects */
1381 master->num_chipselect = p->info->num_chipselect;
1382 ret = sh_msiof_get_cs_gpios(p);
1383 if (ret)
1384 goto err1;
1385
Geert Uytterhoeven1bd6363bc02014-02-25 11:21:13 +01001386 /* init master code */
Magnus Damm8051eff2009-11-26 11:10:05 +00001387 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1388 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
Geert Uytterhoevena6802cc2016-06-22 14:50:03 +02001389 master->flags = chipdata->master_flags;
Magnus Damm8051eff2009-11-26 11:10:05 +00001390 master->bus_num = pdev->id;
Geert Uytterhoevenf7c05e82014-02-20 15:43:00 +01001391 master->dev.of_node = pdev->dev.of_node;
Geert Uytterhoeven8d195342014-02-20 15:43:04 +01001392 master->setup = sh_msiof_spi_setup;
Geert Uytterhoevenc833ff72014-02-25 11:21:11 +01001393 master->prepare_message = sh_msiof_prepare_message;
Hisashi Nakamuracf9e4782017-05-22 15:11:43 +02001394 master->slave_abort = sh_msiof_slave_abort;
Geert Uytterhoeven24162892014-02-25 11:21:12 +01001395 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
Geert Uytterhoevene2a0ba52014-03-11 10:59:11 +01001396 master->auto_runtime_pm = true;
Geert Uytterhoeven1bd6363bc02014-02-25 11:21:13 +01001397 master->transfer_one = sh_msiof_transfer_one;
Magnus Damm8051eff2009-11-26 11:10:05 +00001398
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001399 ret = sh_msiof_request_dma(p);
1400 if (ret < 0)
1401 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1402
Geert Uytterhoeven1bd6363bc02014-02-25 11:21:13 +01001403 ret = devm_spi_register_master(&pdev->dev, master);
1404 if (ret < 0) {
1405 dev_err(&pdev->dev, "spi_register_master error.\n");
1406 goto err2;
1407 }
Magnus Damm8051eff2009-11-26 11:10:05 +00001408
Geert Uytterhoeven1bd6363bc02014-02-25 11:21:13 +01001409 return 0;
Magnus Damm8051eff2009-11-26 11:10:05 +00001410
Geert Uytterhoeven1bd6363bc02014-02-25 11:21:13 +01001411 err2:
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001412 sh_msiof_release_dma(p);
Magnus Damm8051eff2009-11-26 11:10:05 +00001413 pm_runtime_disable(&pdev->dev);
Magnus Damm8051eff2009-11-26 11:10:05 +00001414 err1:
1415 spi_master_put(master);
Magnus Damm8051eff2009-11-26 11:10:05 +00001416 return ret;
1417}
1418
1419static int sh_msiof_spi_remove(struct platform_device *pdev)
1420{
Geert Uytterhoevenb0d0ce82014-06-30 12:10:24 +02001421 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1422
1423 sh_msiof_release_dma(p);
Geert Uytterhoeven1bd6363bc02014-02-25 11:21:13 +01001424 pm_runtime_disable(&pdev->dev);
Geert Uytterhoeven1bd6363bc02014-02-25 11:21:13 +01001425 return 0;
Magnus Damm8051eff2009-11-26 11:10:05 +00001426}
1427
Krzysztof Kozlowski3789c85202015-05-02 00:44:07 +09001428static const struct platform_device_id spi_driver_ids[] = {
Geert Uytterhoeven50a7e232014-02-25 11:21:09 +01001429 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
Bastian Hechtcf9c86e2012-12-12 12:54:48 +01001430 {},
1431};
Geert Uytterhoeven50a7e232014-02-25 11:21:09 +01001432MODULE_DEVICE_TABLE(platform, spi_driver_ids);
Bastian Hechtcf9c86e2012-12-12 12:54:48 +01001433
Gaku Inamiffa69d62018-09-05 10:49:36 +02001434#ifdef CONFIG_PM_SLEEP
1435static int sh_msiof_spi_suspend(struct device *dev)
1436{
Wolfram Sang07c7df32018-10-21 22:00:46 +02001437 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
Gaku Inamiffa69d62018-09-05 10:49:36 +02001438
1439 return spi_master_suspend(p->master);
1440}
1441
1442static int sh_msiof_spi_resume(struct device *dev)
1443{
Wolfram Sang07c7df32018-10-21 22:00:46 +02001444 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
Gaku Inamiffa69d62018-09-05 10:49:36 +02001445
1446 return spi_master_resume(p->master);
1447}
1448
1449static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend,
1450 sh_msiof_spi_resume);
1451#define DEV_PM_OPS &sh_msiof_spi_pm_ops
1452#else
1453#define DEV_PM_OPS NULL
1454#endif /* CONFIG_PM_SLEEP */
1455
Magnus Damm8051eff2009-11-26 11:10:05 +00001456static struct platform_driver sh_msiof_spi_drv = {
1457 .probe = sh_msiof_spi_probe,
1458 .remove = sh_msiof_spi_remove,
Geert Uytterhoeven50a7e232014-02-25 11:21:09 +01001459 .id_table = spi_driver_ids,
Magnus Damm8051eff2009-11-26 11:10:05 +00001460 .driver = {
1461 .name = "spi_sh_msiof",
Gaku Inamiffa69d62018-09-05 10:49:36 +02001462 .pm = DEV_PM_OPS,
Sachin Kamat691ee4e2013-03-14 15:31:51 +05301463 .of_match_table = of_match_ptr(sh_msiof_match),
Magnus Damm8051eff2009-11-26 11:10:05 +00001464 },
1465};
Grant Likely940ab882011-10-05 11:29:49 -06001466module_platform_driver(sh_msiof_spi_drv);
Magnus Damm8051eff2009-11-26 11:10:05 +00001467
1468MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
1469MODULE_AUTHOR("Magnus Damm");
1470MODULE_LICENSE("GPL v2");
1471MODULE_ALIAS("platform:spi_sh_msiof");