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Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001// SPDX-License-Identifier: GPL-2.0
Stefan Agner446e9c62014-05-14 23:45:58 +02002#include <dt-bindings/input/input.h>
3#include "tegra30.dtsi"
4
5/*
Marcel Ziswiler39ebbf62015-08-28 17:59:36 +02006 * Toradex Colibri T30 Module Device Tree
7 * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E; IT: V1.1A
Stefan Agner446e9c62014-05-14 23:45:58 +02008 */
9/ {
10 model = "Toradex Colibri T30";
11 compatible = "toradex,colibri_t30", "nvidia,tegra30";
12
Krzysztof Kozlowski48299762018-07-09 18:05:17 +020013 memory@80000000 {
Stefan Agner446e9c62014-05-14 23:45:58 +020014 reg = <0x80000000 0x40000000>;
15 };
16
17 host1x@50000000 {
18 hdmi@54280000 {
Marcel Ziswiler033519b2018-09-01 10:12:16 +020019 nvidia,ddc-i2c-bus = <&hdmiddc>;
Stefan Agner446e9c62014-05-14 23:45:58 +020020 nvidia,hpd-gpio =
21 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
Marcel Ziswiler584a9e52018-09-01 10:12:17 +020022 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
23 vdd-supply = <&reg_3v3_avdd_hdmi>;
Stefan Agner446e9c62014-05-14 23:45:58 +020024 };
25 };
26
27 pinmux@70000868 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&state_default>;
30
31 state_default: pinmux {
Marcel Ziswiler8948e742016-06-19 03:00:01 +020032 /* Analogue Audio (On-module) */
33 clk1_out_pw4 {
34 nvidia,pins = "clk1_out_pw4";
35 nvidia,function = "extperiph1";
36 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
37 nvidia,tristate = <TEGRA_PIN_DISABLE>;
38 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
39 };
40 dap3_fs_pp0 {
41 nvidia,pins = "dap3_fs_pp0",
42 "dap3_sclk_pp3",
43 "dap3_din_pp1",
44 "dap3_dout_pp2";
45 nvidia,function = "i2s2";
46 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
47 nvidia,tristate = <TEGRA_PIN_DISABLE>;
48 };
49
Stefan Agner446e9c62014-05-14 23:45:58 +020050 /* Colibri BL_ON */
51 pv2 {
52 nvidia,pins = "pv2";
53 nvidia,function = "rsvd4";
54 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
55 nvidia,tristate = <TEGRA_PIN_DISABLE>;
56 };
57
58 /* Colibri Backlight PWM<A> */
59 sdmmc3_dat3_pb4 {
Thierry Redingd5edc4e2015-09-15 10:29:57 +020060 nvidia,pins = "sdmmc3_dat3_pb4";
Stefan Agner446e9c62014-05-14 23:45:58 +020061 nvidia,function = "pwm0";
62 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
63 nvidia,tristate = <TEGRA_PIN_DISABLE>;
64 };
65
66 /* Colibri CAN_INT */
67 kb_row8_ps0 {
68 nvidia,pins = "kb_row8_ps0";
69 nvidia,function = "kbc";
70 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
71 nvidia,tristate = <TEGRA_PIN_DISABLE>;
72 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
73 };
74
75 /*
76 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
77 * todays display need DE, disable LCD_M1
78 */
79 lcd_m1_pw1 {
80 nvidia,pins = "lcd_m1_pw1";
81 nvidia,function = "rsvd3";
82 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
83 nvidia,tristate = <TEGRA_PIN_DISABLE>;
84 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
85 };
86
Stefan Agner446e9c62014-05-14 23:45:58 +020087 /* Colibri MMC */
88 kb_row10_ps2 {
89 nvidia,pins = "kb_row10_ps2";
90 nvidia,function = "sdmmc2";
91 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
92 nvidia,tristate = <TEGRA_PIN_DISABLE>;
93 };
94 kb_row11_ps3 {
Thierry Redingd5edc4e2015-09-15 10:29:57 +020095 nvidia,pins = "kb_row11_ps3",
96 "kb_row12_ps4",
97 "kb_row13_ps5",
98 "kb_row14_ps6",
99 "kb_row15_ps7";
Stefan Agner446e9c62014-05-14 23:45:58 +0200100 nvidia,function = "sdmmc2";
101 nvidia,pull = <TEGRA_PIN_PULL_UP>;
102 nvidia,tristate = <TEGRA_PIN_DISABLE>;
103 };
104
105 /* Colibri SSP */
106 ulpi_clk_py0 {
Thierry Redingd5edc4e2015-09-15 10:29:57 +0200107 nvidia,pins = "ulpi_clk_py0",
108 "ulpi_dir_py1",
109 "ulpi_nxt_py2",
110 "ulpi_stp_py3";
Stefan Agner446e9c62014-05-14 23:45:58 +0200111 nvidia,function = "spi1";
112 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
113 nvidia,tristate = <TEGRA_PIN_DISABLE>;
114 };
115 sdmmc3_dat6_pd3 {
Thierry Redingd5edc4e2015-09-15 10:29:57 +0200116 nvidia,pins = "sdmmc3_dat6_pd3",
117 "sdmmc3_dat7_pd4";
Stefan Agner446e9c62014-05-14 23:45:58 +0200118 nvidia,function = "spdif";
119 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
120 nvidia,tristate = <TEGRA_PIN_ENABLE>;
121 };
122
123 /* Colibri UART_A */
124 ulpi_data0 {
Thierry Redingd5edc4e2015-09-15 10:29:57 +0200125 nvidia,pins = "ulpi_data0_po1",
126 "ulpi_data1_po2",
127 "ulpi_data2_po3",
128 "ulpi_data3_po4",
129 "ulpi_data4_po5",
130 "ulpi_data5_po6",
131 "ulpi_data6_po7",
132 "ulpi_data7_po0";
Stefan Agner446e9c62014-05-14 23:45:58 +0200133 nvidia,function = "uarta";
134 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
135 nvidia,tristate = <TEGRA_PIN_DISABLE>;
136 };
137
138 /* Colibri UART_B */
139 gmi_a16_pj7 {
Thierry Redingd5edc4e2015-09-15 10:29:57 +0200140 nvidia,pins = "gmi_a16_pj7",
141 "gmi_a17_pb0",
142 "gmi_a18_pb1",
143 "gmi_a19_pk7";
Stefan Agner446e9c62014-05-14 23:45:58 +0200144 nvidia,function = "uartd";
145 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
146 nvidia,tristate = <TEGRA_PIN_DISABLE>;
147 };
148
149 /* Colibri UART_C */
150 uart2_rxd {
Thierry Redingd5edc4e2015-09-15 10:29:57 +0200151 nvidia,pins = "uart2_rxd_pc3",
152 "uart2_txd_pc2";
Stefan Agner446e9c62014-05-14 23:45:58 +0200153 nvidia,function = "uartb";
154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155 nvidia,tristate = <TEGRA_PIN_DISABLE>;
156 };
157
158 /* eMMC */
159 sdmmc4_clk_pcc4 {
Thierry Redingd5edc4e2015-09-15 10:29:57 +0200160 nvidia,pins = "sdmmc4_clk_pcc4",
161 "sdmmc4_rst_n_pcc3";
Stefan Agner446e9c62014-05-14 23:45:58 +0200162 nvidia,function = "sdmmc4";
163 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
164 nvidia,tristate = <TEGRA_PIN_DISABLE>;
165 };
166 sdmmc4_dat0_paa0 {
Thierry Redingd5edc4e2015-09-15 10:29:57 +0200167 nvidia,pins = "sdmmc4_dat0_paa0",
168 "sdmmc4_dat1_paa1",
169 "sdmmc4_dat2_paa2",
170 "sdmmc4_dat3_paa3",
171 "sdmmc4_dat4_paa4",
172 "sdmmc4_dat5_paa5",
173 "sdmmc4_dat6_paa6",
174 "sdmmc4_dat7_paa7";
Stefan Agner446e9c62014-05-14 23:45:58 +0200175 nvidia,function = "sdmmc4";
176 nvidia,pull = <TEGRA_PIN_PULL_UP>;
177 nvidia,tristate = <TEGRA_PIN_DISABLE>;
178 };
Marcel Ziswiler62bcaba2015-08-28 17:59:38 +0200179
Marcel Ziswilere48f6c0e2015-08-28 17:59:39 +0200180 /* Power I2C (On-module) */
181 pwr_i2c_scl_pz6 {
182 nvidia,pins = "pwr_i2c_scl_pz6",
183 "pwr_i2c_sda_pz7";
184 nvidia,function = "i2cpwr";
185 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
186 nvidia,tristate = <TEGRA_PIN_DISABLE>;
187 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
188 nvidia,lock = <TEGRA_PIN_DISABLE>;
189 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
190 };
191
Marcel Ziswiler62bcaba2015-08-28 17:59:38 +0200192 /*
193 * THERMD_ALERT#, unlatched I2C address pin of LM95245
194 * temperature sensor therefore requires disabling for
195 * now
196 */
197 lcd_dc1_pd2 {
198 nvidia,pins = "lcd_dc1_pd2";
199 nvidia,function = "rsvd3";
200 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
201 nvidia,tristate = <TEGRA_PIN_DISABLE>;
202 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
203 };
Marcel Ziswiler6456e9c2015-08-28 17:59:41 +0200204
205 /* TOUCH_PEN_INT# */
206 pv0 {
207 nvidia,pins = "pv0";
208 nvidia,function = "rsvd1";
209 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
210 nvidia,tristate = <TEGRA_PIN_DISABLE>;
211 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
212 };
Stefan Agner446e9c62014-05-14 23:45:58 +0200213 };
214 };
215
216 hdmiddc: i2c@7000c700 {
Marcel Ziswiler1c3389e2018-02-10 02:36:36 +0100217 clock-frequency = <10000>;
Stefan Agner446e9c62014-05-14 23:45:58 +0200218 };
219
220 /*
221 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
222 * touch screen controller
223 */
224 i2c@7000d000 {
225 status = "okay";
226 clock-frequency = <100000>;
227
Marcel Ziswiler8948e742016-06-19 03:00:01 +0200228 /* SGTL5000 audio codec */
229 sgtl5000: codec@a {
230 compatible = "fsl,sgtl5000";
231 reg = <0x0a>;
Marcel Ziswiler584a9e52018-09-01 10:12:17 +0200232 VDDA-supply = <&reg_module_3v3>;
233 VDDIO-supply = <&reg_module_3v3>;
Marcel Ziswiler8948e742016-06-19 03:00:01 +0200234 clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
235 };
236
Stefan Agner446e9c62014-05-14 23:45:58 +0200237 pmic: tps65911@2d {
238 compatible = "ti,tps65911";
239 reg = <0x2d>;
240
241 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
242 #interrupt-cells = <2>;
243 interrupt-controller;
244
245 ti,system-power-controller;
246
247 #gpio-cells = <2>;
248 gpio-controller;
249
Marcel Ziswiler584a9e52018-09-01 10:12:17 +0200250 vcc1-supply = <&reg_module_3v3>;
251 vcc2-supply = <&reg_module_3v3>;
252 vcc3-supply = <&reg_1v8_vio>;
253 vcc4-supply = <&reg_module_3v3>;
254 vcc5-supply = <&reg_module_3v3>;
255 vcc6-supply = <&reg_1v8_vio>;
256 vcc7-supply = <&reg_5v0_charge_pump>;
257 vccio-supply = <&reg_module_3v3>;
Stefan Agner446e9c62014-05-14 23:45:58 +0200258
259 regulators {
Stefan Agner446e9c62014-05-14 23:45:58 +0200260 vdd1_reg: vdd1 {
Marcel Ziswiler584a9e52018-09-01 10:12:17 +0200261 regulator-name = "+V1.35_VDDIO_DDR";
Stefan Agner446e9c62014-05-14 23:45:58 +0200262 regulator-min-microvolt = <1350000>;
263 regulator-max-microvolt = <1350000>;
264 regulator-always-on;
265 };
266
267 /* SW2: unused */
268
Stefan Agner446e9c62014-05-14 23:45:58 +0200269 vddctrl_reg: vddctrl {
Marcel Ziswiler584a9e52018-09-01 10:12:17 +0200270 regulator-name = "+V1.0_VDD_CPU";
Stefan Agner446e9c62014-05-14 23:45:58 +0200271 regulator-min-microvolt = <1150000>;
272 regulator-max-microvolt = <1150000>;
273 regulator-always-on;
274 };
275
Marcel Ziswiler584a9e52018-09-01 10:12:17 +0200276 reg_1v8_vio: vio {
277 regulator-name = "+V1.8";
Stefan Agner446e9c62014-05-14 23:45:58 +0200278 regulator-min-microvolt = <1800000>;
279 regulator-max-microvolt = <1800000>;
280 regulator-always-on;
281 };
282
283 /* LDO1: unused */
284
285 /*
286 * EN_+V3.3 switching via FET:
287 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
Marcel Ziswiler584a9e52018-09-01 10:12:17 +0200288 * see also +V3.3 fixed supply
Stefan Agner446e9c62014-05-14 23:45:58 +0200289 */
290 ldo2_reg: ldo2 {
Marcel Ziswiler584a9e52018-09-01 10:12:17 +0200291 regulator-name = "EN_+V3.3";
Stefan Agner446e9c62014-05-14 23:45:58 +0200292 regulator-min-microvolt = <3300000>;
293 regulator-max-microvolt = <3300000>;
294 regulator-always-on;
295 };
296
297 /* LDO3: unused */
298
Stefan Agner446e9c62014-05-14 23:45:58 +0200299 ldo4_reg: ldo4 {
Marcel Ziswiler584a9e52018-09-01 10:12:17 +0200300 regulator-name = "+V1.2_VDD_RTC";
Stefan Agner446e9c62014-05-14 23:45:58 +0200301 regulator-min-microvolt = <1200000>;
302 regulator-max-microvolt = <1200000>;
303 regulator-always-on;
304 };
305
306 /*
307 * +V2.8_AVDD_VDAC:
Marcel Ziswiler584a9e52018-09-01 10:12:17 +0200308 * only required for (unsupported) analog RGB
Stefan Agner446e9c62014-05-14 23:45:58 +0200309 */
310 ldo5_reg: ldo5 {
Marcel Ziswiler584a9e52018-09-01 10:12:17 +0200311 regulator-name = "+V2.8_AVDD_VDAC";
Stefan Agner446e9c62014-05-14 23:45:58 +0200312 regulator-min-microvolt = <2800000>;
313 regulator-max-microvolt = <2800000>;
314 regulator-always-on;
315 };
316
317 /*
318 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
319 * but LDO6 can't set voltage in 50mV
320 * granularity
321 */
322 ldo6_reg: ldo6 {
Marcel Ziswiler584a9e52018-09-01 10:12:17 +0200323 regulator-name = "+V1.05_AVDD_PLLE";
Stefan Agner446e9c62014-05-14 23:45:58 +0200324 regulator-min-microvolt = <1100000>;
325 regulator-max-microvolt = <1100000>;
326 };
327
Stefan Agner446e9c62014-05-14 23:45:58 +0200328 ldo7_reg: ldo7 {
Marcel Ziswiler584a9e52018-09-01 10:12:17 +0200329 regulator-name = "+V1.2_AVDD_PLL";
Stefan Agner446e9c62014-05-14 23:45:58 +0200330 regulator-min-microvolt = <1200000>;
331 regulator-max-microvolt = <1200000>;
332 regulator-always-on;
333 };
334
Stefan Agner446e9c62014-05-14 23:45:58 +0200335 ldo8_reg: ldo8 {
Marcel Ziswiler584a9e52018-09-01 10:12:17 +0200336 regulator-name = "+V1.0_VDD_DDR_HS";
Stefan Agner446e9c62014-05-14 23:45:58 +0200337 regulator-min-microvolt = <1000000>;
338 regulator-max-microvolt = <1000000>;
339 regulator-always-on;
340 };
341 };
342 };
343
Marcel Ziswiler737a7c22015-08-28 17:59:42 +0200344 /* STMPE811 touch screen controller */
345 stmpe811@41 {
346 compatible = "st,stmpe811";
Marcel Ziswiler737a7c22015-08-28 17:59:42 +0200347 reg = <0x41>;
348 interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
349 interrupt-parent = <&gpio>;
350 interrupt-controller;
351 id = <0>;
352 blocks = <0x5>;
353 irq-trigger = <0x1>;
354
355 stmpe_touchscreen {
356 compatible = "st,stmpe-ts";
Marcel Ziswiler737a7c22015-08-28 17:59:42 +0200357 /* 3.25 MHz ADC clock speed */
358 st,adc-freq = <1>;
359 /* 8 sample average control */
360 st,ave-ctrl = <3>;
361 /* 7 length fractional part in z */
362 st,fraction-z = <7>;
363 /*
364 * 50 mA typical 80 mA max touchscreen drivers
365 * current limit value
366 */
367 st,i-drive = <1>;
368 /* 12-bit ADC */
369 st,mod-12b = <1>;
370 /* internal ADC reference */
371 st,ref-sel = <0>;
372 /* ADC converstion time: 80 clocks */
373 st,sample-time = <4>;
374 /* 1 ms panel driver settling time */
375 st,settling = <3>;
376 /* 5 ms touch detect interrupt delay */
377 st,touch-det-delay = <5>;
378 };
379 };
380
Stefan Agner446e9c62014-05-14 23:45:58 +0200381 /*
382 * LM95245 temperature sensor
383 * Note: OVERT_N directly connected to PMIC PWRDN
384 */
385 temp-sensor@4c {
386 compatible = "national,lm95245";
387 reg = <0x4c>;
388 };
389
390 /* SW: +V1.2_VDD_CORE */
391 tps62362@60 {
392 compatible = "ti,tps62362";
393 reg = <0x60>;
394
395 regulator-name = "tps62362-vout";
396 regulator-min-microvolt = <900000>;
397 regulator-max-microvolt = <1400000>;
398 regulator-boot-on;
399 regulator-always-on;
400 ti,vsel0-state-low;
401 /* VSEL1: EN_CORE_DVFS_N low for DVFS */
402 ti,vsel1-state-low;
403 };
404 };
405
406 pmc@7000e400 {
407 nvidia,invert-interrupt;
408 nvidia,suspend-mode = <1>;
409 nvidia,cpu-pwr-good-time = <5000>;
410 nvidia,cpu-pwr-off-time = <5000>;
411 nvidia,core-pwr-good-time = <3845 3845>;
412 nvidia,core-pwr-off-time = <0>;
413 nvidia,core-power-req-active-high;
414 nvidia,sys-clock-req-active-high;
415 };
416
Marcel Ziswiler8948e742016-06-19 03:00:01 +0200417 ahub@70080000 {
418 i2s@70080500 {
419 status = "okay";
420 };
421 };
422
Marcel Ziswiler3791d1c2015-08-28 17:59:43 +0200423 /* eMMC */
424 sdhci@78000600 {
Stefan Agner446e9c62014-05-14 23:45:58 +0200425 status = "okay";
426 bus-width = <8>;
427 non-removable;
428 };
429
430 /* EHCI instance 1: USB2_DP/N -> AX88772B */
431 usb@7d004000 {
432 status = "okay";
Marcel Ziswilera5db2da2018-09-01 10:12:15 +0200433 #address-cells = <1>;
434 #size-cells = <0>;
435
436 asix@1 {
437 reg = <1>;
438 local-mac-address = [00 00 00 00 00 00];
439 };
Stefan Agner446e9c62014-05-14 23:45:58 +0200440 };
441
442 usb-phy@7d004000 {
443 status = "okay";
444 nvidia,is-wired = <1>;
445 };
446
447 clocks {
448 compatible = "simple-bus";
449 #address-cells = <1>;
450 #size-cells = <0>;
451
452 clk32k_in: clk@0 {
453 compatible = "fixed-clock";
Thierry Reding4ec2e602016-06-10 18:55:24 +0200454 reg = <0>;
Stefan Agner446e9c62014-05-14 23:45:58 +0200455 #clock-cells = <0>;
456 clock-frequency = <32768>;
457 };
458 };
459
Marcel Ziswiler584a9e52018-09-01 10:12:17 +0200460 reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
461 compatible = "regulator-fixed";
462 regulator-name = "+V1.8_AVDD_HDMI_PLL";
463 regulator-min-microvolt = <1800000>;
464 regulator-max-microvolt = <1800000>;
465 enable-active-high;
466 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
467 vin-supply = <&reg_1v8_vio>;
468 };
Stefan Agner446e9c62014-05-14 23:45:58 +0200469
Marcel Ziswiler584a9e52018-09-01 10:12:17 +0200470 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
471 compatible = "regulator-fixed";
472 regulator-name = "+V3.3_AVDD_HDMI";
473 regulator-min-microvolt = <3300000>;
474 regulator-max-microvolt = <3300000>;
475 enable-active-high;
476 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
477 vin-supply = <&reg_module_3v3>;
478 };
Marcel Ziswiler312d3732015-08-28 17:59:37 +0200479
Marcel Ziswiler584a9e52018-09-01 10:12:17 +0200480 reg_5v0_charge_pump: regulator-5v0-charge-pump {
481 compatible = "regulator-fixed";
482 regulator-name = "+V5.0";
483 regulator-min-microvolt = <5000000>;
484 regulator-max-microvolt = <5000000>;
485 regulator-always-on;
486 };
Marcel Ziswilercaa9eac2014-08-22 13:25:10 -0600487
Marcel Ziswiler584a9e52018-09-01 10:12:17 +0200488 reg_module_3v3: regulator-module-3v3 {
489 compatible = "regulator-fixed";
490 regulator-name = "+V3.3";
491 regulator-min-microvolt = <3300000>;
492 regulator-max-microvolt = <3300000>;
493 regulator-always-on;
Stefan Agner446e9c62014-05-14 23:45:58 +0200494 };
Marcel Ziswiler8948e742016-06-19 03:00:01 +0200495
496 sound {
497 compatible = "toradex,tegra-audio-sgtl5000-colibri_t30",
498 "nvidia,tegra-audio-sgtl5000";
499 nvidia,model = "Toradex Colibri T30";
500 nvidia,audio-routing =
501 "Headphone Jack", "HP_OUT",
502 "LINE_IN", "Line In Jack",
503 "MIC_IN", "Mic Jack";
504 nvidia,i2s-controller = <&tegra_i2s2>;
505 nvidia,audio-codec = <&sgtl5000>;
506 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
507 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
508 <&tegra_car TEGRA30_CLK_EXTERN1>;
509 clock-names = "pll_a", "pll_a_out0", "mclk";
510 };
Stefan Agner446e9c62014-05-14 23:45:58 +0200511};