blob: 6857cec8382d01f1c6f2c49a03ba533b08ff4f34 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -06001/dts-v1/;
2
Grant Likely8e267f32011-07-19 17:26:54 -06003/include/ "tegra20.dtsi"
4
5/ {
6 model = "NVIDIA Tegra2 Harmony evaluation board";
7 compatible = "nvidia,harmony", "nvidia,tegra20";
8
Grant Likely8e267f32011-07-19 17:26:54 -06009 memory@0 {
10 reg = < 0x00000000 0x40000000 >;
11 };
12
Stephen Warrenecc295b2012-03-15 16:27:36 -060013 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma", "gme";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
32 "spia", "spib", "spic";
33 nvidia,function = "gmi";
34 };
35 cdev1 {
36 nvidia,pins = "cdev1";
37 nvidia,function = "plla_out";
38 };
39 cdev2 {
40 nvidia,pins = "cdev2";
41 nvidia,function = "pllp_out4";
42 };
43 crtp {
44 nvidia,pins = "crtp";
45 nvidia,function = "crt";
46 };
47 csus {
48 nvidia,pins = "csus";
49 nvidia,function = "vi_sensor_clk";
50 };
51 dap1 {
52 nvidia,pins = "dap1";
53 nvidia,function = "dap1";
54 };
55 dap2 {
56 nvidia,pins = "dap2";
57 nvidia,function = "dap2";
58 };
59 dap3 {
60 nvidia,pins = "dap3";
61 nvidia,function = "dap3";
62 };
63 dap4 {
64 nvidia,pins = "dap4";
65 nvidia,function = "dap4";
66 };
67 ddc {
68 nvidia,pins = "ddc";
69 nvidia,function = "i2c2";
70 };
71 dta {
72 nvidia,pins = "dta", "dtd";
73 nvidia,function = "sdio2";
74 };
75 dtb {
76 nvidia,pins = "dtb", "dtc", "dte";
77 nvidia,function = "rsvd1";
78 };
79 dtf {
80 nvidia,pins = "dtf";
81 nvidia,function = "i2c3";
82 };
83 gmc {
84 nvidia,pins = "gmc";
85 nvidia,function = "uartd";
86 };
87 gpu7 {
88 nvidia,pins = "gpu7";
89 nvidia,function = "rtck";
90 };
91 gpv {
92 nvidia,pins = "gpv", "slxa", "slxk";
93 nvidia,function = "pcie";
94 };
95 hdint {
96 nvidia,pins = "hdint", "pta";
97 nvidia,function = "hdmi";
98 };
99 i2cp {
100 nvidia,pins = "i2cp";
101 nvidia,function = "i2cp";
102 };
103 irrx {
104 nvidia,pins = "irrx", "irtx";
105 nvidia,function = "uarta";
106 };
107 kbca {
108 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
109 "kbce", "kbcf";
110 nvidia,function = "kbc";
111 };
112 lcsn {
113 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
114 "ld3", "ld4", "ld5", "ld6", "ld7",
115 "ld8", "ld9", "ld10", "ld11", "ld12",
116 "ld13", "ld14", "ld15", "ld16", "ld17",
117 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
118 "lhs", "lm0", "lm1", "lpp", "lpw0",
119 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
120 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
121 "lvs";
122 nvidia,function = "displaya";
123 };
124 owc {
125 nvidia,pins = "owc", "spdi", "spdo", "uac";
126 nvidia,function = "rsvd2";
127 };
128 pmc {
129 nvidia,pins = "pmc";
130 nvidia,function = "pwr_on";
131 };
132 rm {
133 nvidia,pins = "rm";
134 nvidia,function = "i2c1";
135 };
136 sdb {
137 nvidia,pins = "sdb", "sdc", "sdd";
138 nvidia,function = "pwm";
139 };
140 sdio1 {
141 nvidia,pins = "sdio1";
142 nvidia,function = "sdio1";
143 };
144 slxc {
145 nvidia,pins = "slxc", "slxd";
146 nvidia,function = "spdif";
147 };
148 spid {
149 nvidia,pins = "spid", "spie", "spif";
150 nvidia,function = "spi1";
151 };
152 spig {
153 nvidia,pins = "spig", "spih";
154 nvidia,function = "spi2_alt";
155 };
156 uaa {
157 nvidia,pins = "uaa", "uab", "uda";
158 nvidia,function = "ulpi";
159 };
160 uad {
161 nvidia,pins = "uad";
162 nvidia,function = "irda";
163 };
164 uca {
165 nvidia,pins = "uca", "ucb";
166 nvidia,function = "uartc";
167 };
168 conf_ata {
169 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
Stephen Warren563da212012-04-13 16:35:20 -0600170 "cdev1", "cdev2", "dap1", "dtb", "gma",
171 "gmb", "gmc", "gmd", "gme", "gpu7",
172 "gpv", "i2cp", "pta", "rm", "slxa",
173 "slxk", "spia", "spib", "uac";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600174 nvidia,pull = <0>;
175 nvidia,tristate = <0>;
176 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600177 conf_ck32 {
178 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
179 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
180 nvidia,pull = <0>;
181 };
Stephen Warren563da212012-04-13 16:35:20 -0600182 conf_csus {
183 nvidia,pins = "csus", "spid", "spif";
184 nvidia,pull = <1>;
185 nvidia,tristate = <1>;
186 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600187 conf_crtp {
188 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
189 "dtc", "dte", "dtf", "gpu", "sdio1",
190 "slxc", "slxd", "spdi", "spdo", "spig",
Stephen Warren563da212012-04-13 16:35:20 -0600191 "uda";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600192 nvidia,pull = <0>;
193 nvidia,tristate = <1>;
194 };
195 conf_ddc {
196 nvidia,pins = "ddc", "dta", "dtd", "kbca",
197 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
198 "sdc";
199 nvidia,pull = <2>;
200 nvidia,tristate = <0>;
201 };
202 conf_hdint {
203 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
204 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
205 "lvp0", "owc", "sdb";
206 nvidia,tristate = <1>;
207 };
208 conf_irrx {
209 nvidia,pins = "irrx", "irtx", "sdd", "spic",
210 "spie", "spih", "uaa", "uab", "uad",
211 "uca", "ucb";
212 nvidia,pull = <2>;
213 nvidia,tristate = <1>;
214 };
215 conf_lc {
216 nvidia,pins = "lc", "ls";
217 nvidia,pull = <2>;
218 };
219 conf_ld0 {
220 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
221 "ld5", "ld6", "ld7", "ld8", "ld9",
222 "ld10", "ld11", "ld12", "ld13", "ld14",
223 "ld15", "ld16", "ld17", "ldi", "lhp0",
224 "lhp1", "lhp2", "lhs", "lm0", "lpp",
225 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
226 "lvs", "pmc";
227 nvidia,tristate = <0>;
228 };
229 conf_ld17_0 {
230 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
231 "ld23_22";
232 nvidia,pull = <1>;
233 };
234 };
235 };
236
Stephen Warrend17adfd2012-01-25 14:43:27 -0700237 pmc@7000f400 {
238 nvidia,invert-interrupt;
239 };
240
Grant Likely8e267f32011-07-19 17:26:54 -0600241 i2c@7000c000 {
242 clock-frequency = <400000>;
243
Stephen Warren797acf72012-01-11 16:09:57 -0700244 wm8903: wm8903@1a {
Grant Likely8e267f32011-07-19 17:26:54 -0600245 compatible = "wlf,wm8903";
246 reg = <0x1a>;
Stephen Warren797acf72012-01-11 16:09:57 -0700247 interrupt-parent = <&gpio>;
248 interrupts = < 187 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600249
250 gpio-controller;
251 #gpio-cells = <2>;
252
Stephen Warren797acf72012-01-11 16:09:57 -0700253 micdet-cfg = <0>;
254 micdet-delay = <100>;
255 gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >;
Grant Likely8e267f32011-07-19 17:26:54 -0600256 };
257 };
258
259 i2c@7000c400 {
260 clock-frequency = <400000>;
261 };
262
263 i2c@7000c500 {
264 clock-frequency = <400000>;
265 };
266
267 i2c@7000d000 {
268 clock-frequency = <400000>;
269 };
270
Stephen Warren797acf72012-01-11 16:09:57 -0700271 i2s@70002a00 {
272 status = "disable";
273 };
Grant Likely8e267f32011-07-19 17:26:54 -0600274
Stephen Warren797acf72012-01-11 16:09:57 -0700275 sound {
276 compatible = "nvidia,tegra-audio-wm8903-harmony",
277 "nvidia,tegra-audio-wm8903";
278 nvidia,model = "NVIDIA Tegra Harmony";
279
280 nvidia,audio-routing =
281 "Headphone Jack", "HPOUTR",
282 "Headphone Jack", "HPOUTL",
283 "Int Spk", "ROP",
284 "Int Spk", "RON",
285 "Int Spk", "LOP",
286 "Int Spk", "LON",
287 "Mic Jack", "MICBIAS",
288 "IN1L", "Mic Jack";
289
290 nvidia,i2s-controller = <&tegra_i2s1>;
291 nvidia,audio-codec = <&wm8903>;
292
293 nvidia,spkr-en-gpios = <&wm8903 2 0>;
294 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
295 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
296 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
Grant Likely8e267f32011-07-19 17:26:54 -0600297 };
298
Stephen Warren31c1ec92011-11-21 14:44:10 -0700299 serial@70006000 {
300 status = "disable";
301 };
302
303 serial@70006040 {
304 status = "disable";
305 };
306
307 serial@70006200 {
308 status = "disable";
309 };
310
Grant Likely8e267f32011-07-19 17:26:54 -0600311 serial@70006300 {
312 clock-frequency = < 216000000 >;
313 };
314
Stephen Warren31c1ec92011-11-21 14:44:10 -0700315 serial@70006400 {
316 status = "disable";
317 };
318
Stephen Warren1292c122011-11-21 14:44:11 -0700319 sdhci@c8000000 {
320 status = "disable";
321 };
322
Grant Likely8e267f32011-07-19 17:26:54 -0600323 sdhci@c8000200 {
Stephen Warrena0638eb2011-09-20 10:46:25 -0600324 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
325 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
326 power-gpios = <&gpio 155 0>; /* gpio PT3 */
Grant Likely8e267f32011-07-19 17:26:54 -0600327 };
328
Stephen Warren1292c122011-11-21 14:44:11 -0700329 sdhci@c8000400 {
330 status = "disable";
331 };
332
Grant Likely8e267f32011-07-19 17:26:54 -0600333 sdhci@c8000600 {
Stephen Warrena0638eb2011-09-20 10:46:25 -0600334 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
335 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
336 power-gpios = <&gpio 70 0>; /* gpio PI6 */
Stephen Warren6111d502011-09-20 10:46:26 -0600337 support-8bit;
Grant Likely8e267f32011-07-19 17:26:54 -0600338 };
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600339
340 usb@c5004000 {
341 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
342 };
Grant Likely8e267f32011-07-19 17:26:54 -0600343};