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Simon Horman37a2fce2019-09-30 16:03:52 +02001# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/renesas,ether.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas Electronics SH EtherMAC
8
9allOf:
10 - $ref: ethernet-controller.yaml#
11
12maintainers:
13 - Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
14
15properties:
16 compatible:
17 oneOf:
18 - items:
19 - enum:
20 - renesas,gether-r8a7740 # device is a part of R8A7740 SoC
21 - renesas,gether-r8a77980 # device is a part of R8A77980 SoC
22 - renesas,ether-r7s72100 # device is a part of R7S72100 SoC
23 - renesas,ether-r7s9210 # device is a part of R7S9210 SoC
24 - items:
25 - enum:
26 - renesas,ether-r8a7778 # device is a part of R8A7778 SoC
27 - renesas,ether-r8a7779 # device is a part of R8A7779 SoC
28 - enum:
29 - renesas,rcar-gen1-ether # a generic R-Car Gen1 device
30 - items:
31 - enum:
Lad Prabhakar75d728e2020-05-15 16:08:51 +010032 - renesas,ether-r8a7742 # device is a part of R8A7742 SoC
Simon Horman37a2fce2019-09-30 16:03:52 +020033 - renesas,ether-r8a7743 # device is a part of R8A7743 SoC
Lad Prabhakarf678d212020-04-24 11:38:15 +010034 - renesas,ether-r8a7745 # device is a part of R8A7745 SoC
Simon Horman37a2fce2019-09-30 16:03:52 +020035 - renesas,ether-r8a7790 # device is a part of R8A7790 SoC
36 - renesas,ether-r8a7791 # device is a part of R8A7791 SoC
37 - renesas,ether-r8a7793 # device is a part of R8A7793 SoC
38 - renesas,ether-r8a7794 # device is a part of R8A7794 SoC
39 - enum:
40 - renesas,rcar-gen2-ether # a generic R-Car Gen2 or RZ/G1 device
41
42 reg:
43 items:
Rob Herring9f60a652020-04-15 19:55:48 -050044 - description: E-DMAC/feLic registers
45 - description: TSU registers
Simon Horman37a2fce2019-09-30 16:03:52 +020046 minItems: 1
47
48 interrupts:
49 maxItems: 1
50
51 '#address-cells':
52 description: number of address cells for the MDIO bus
53 const: 1
54
55 '#size-cells':
56 description: number of size cells on the MDIO bus
57 const: 0
58
59 clocks:
60 maxItems: 1
61
Geert Uytterhoeven41506bf2020-08-19 14:45:39 +020062 power-domains:
63 maxItems: 1
Simon Horman37a2fce2019-09-30 16:03:52 +020064
Geert Uytterhoeven41506bf2020-08-19 14:45:39 +020065 resets:
66 maxItems: 1
67
68 phy-mode: true
69
70 phy-handle: true
Simon Horman37a2fce2019-09-30 16:03:52 +020071
72 renesas,no-ether-link:
73 type: boolean
74 description:
75 specify when a board does not provide a proper Ether LINK signal
76
77 renesas,ether-link-active-low:
78 type: boolean
79 description:
80 specify when the Ether LINK signal is active-low instead of normal
81 active-high
82
Geert Uytterhoeven41506bf2020-08-19 14:45:39 +020083patternProperties:
84 "^ethernet-phy@[0-9a-f]$":
85 type: object
86 $ref: ethernet-phy.yaml#
87
Simon Horman37a2fce2019-09-30 16:03:52 +020088required:
89 - compatible
90 - reg
91 - interrupts
92 - phy-mode
93 - phy-handle
94 - '#address-cells'
95 - '#size-cells'
96 - clocks
Geert Uytterhoeven41506bf2020-08-19 14:45:39 +020097
98additionalProperties: false
Simon Horman37a2fce2019-09-30 16:03:52 +020099
100examples:
101 # Lager board
102 - |
103 #include <dt-bindings/clock/r8a7790-clock.h>
104 #include <dt-bindings/interrupt-controller/irq.h>
105
106 ethernet@ee700000 {
107 compatible = "renesas,ether-r8a7790", "renesas,rcar-gen2-ether";
Rob Herringfba56182020-05-12 15:45:43 -0500108 reg = <0xee700000 0x400>;
Simon Horman37a2fce2019-09-30 16:03:52 +0200109 interrupt-parent = <&gic>;
110 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
111 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
112 phy-mode = "rmii";
113 phy-handle = <&phy1>;
Simon Horman37a2fce2019-09-30 16:03:52 +0200114 renesas,ether-link-active-low;
115 #address-cells = <1>;
116 #size-cells = <0>;
117
118 phy1: ethernet-phy@1 {
119 reg = <1>;
120 interrupt-parent = <&irqc0>;
121 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
Simon Horman37a2fce2019-09-30 16:03:52 +0200122 };
123 };