Alan Tull | 6a8c3be | 2015-10-07 16:36:28 +0100 | [diff] [blame] | 1 | # |
| 2 | # FPGA framework configuration |
| 3 | # |
| 4 | |
Vincent Legoll | 50fa028 | 2017-06-14 10:36:26 -0500 | [diff] [blame] | 5 | menuconfig FPGA |
Alan Tull | 6a8c3be | 2015-10-07 16:36:28 +0100 | [diff] [blame] | 6 | tristate "FPGA Configuration Framework" |
| 7 | help |
| 8 | Say Y here if you want support for configuring FPGAs from the |
| 9 | kernel. The FPGA framework adds a FPGA manager class and FPGA |
| 10 | manager drivers. |
| 11 | |
Alan Tull | fab6266 | 2015-10-07 16:36:29 +0100 | [diff] [blame] | 12 | if FPGA |
| 13 | |
| 14 | config FPGA_MGR_SOCFPGA |
| 15 | tristate "Altera SOCFPGA FPGA Manager" |
Jason Gunthorpe | a0e1b61 | 2016-11-21 22:26:42 +0000 | [diff] [blame] | 16 | depends on ARCH_SOCFPGA || COMPILE_TEST |
Alan Tull | fab6266 | 2015-10-07 16:36:29 +0100 | [diff] [blame] | 17 | help |
| 18 | FPGA manager driver support for Altera SOCFPGA. |
| 19 | |
Alan Tull | acbb910a | 2016-11-01 14:14:32 -0500 | [diff] [blame] | 20 | config FPGA_MGR_SOCFPGA_A10 |
| 21 | tristate "Altera SoCFPGA Arria10" |
Jason Gunthorpe | a0e1b61 | 2016-11-21 22:26:42 +0000 | [diff] [blame] | 22 | depends on ARCH_SOCFPGA || COMPILE_TEST |
| 23 | select REGMAP_MMIO |
Alan Tull | acbb910a | 2016-11-01 14:14:32 -0500 | [diff] [blame] | 24 | help |
| 25 | FPGA manager driver support for Altera Arria10 SoCFPGA. |
| 26 | |
Alan Tull | 84e93f1 | 2017-11-15 14:20:27 -0600 | [diff] [blame] | 27 | config ALTERA_PR_IP_CORE |
| 28 | tristate "Altera Partial Reconfiguration IP Core" |
| 29 | help |
| 30 | Core driver support for Altera Partial Reconfiguration IP component |
| 31 | |
| 32 | config ALTERA_PR_IP_CORE_PLAT |
| 33 | tristate "Platform support of Altera Partial Reconfiguration IP Core" |
| 34 | depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM |
Florian Fainelli | 4348f7e | 2017-02-27 16:14:22 -0600 | [diff] [blame] | 35 | help |
Alan Tull | 84e93f1 | 2017-11-15 14:20:27 -0600 | [diff] [blame] | 36 | Platform driver support for Altera Partial Reconfiguration IP |
| 37 | component |
| 38 | |
| 39 | config FPGA_MGR_ALTERA_PS_SPI |
| 40 | tristate "Altera FPGA Passive Serial over SPI" |
| 41 | depends on SPI |
| 42 | help |
| 43 | FPGA manager driver support for Altera Arria/Cyclone/Stratix |
| 44 | using the passive serial interface over SPI. |
| 45 | |
| 46 | config FPGA_MGR_ALTERA_CVP |
| 47 | tristate "Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager" |
| 48 | depends on PCI |
| 49 | help |
| 50 | FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V |
| 51 | and Arria 10 Altera FPGAs using the CvP interface over PCIe. |
| 52 | |
| 53 | config FPGA_MGR_ZYNQ_FPGA |
| 54 | tristate "Xilinx Zynq FPGA" |
| 55 | depends on ARCH_ZYNQ || COMPILE_TEST |
Alan Tull | 84e93f1 | 2017-11-15 14:20:27 -0600 | [diff] [blame] | 56 | help |
| 57 | FPGA manager driver support for Xilinx Zynq FPGAs. |
Florian Fainelli | 4348f7e | 2017-02-27 16:14:22 -0600 | [diff] [blame] | 58 | |
Anatolij Gustschin | 061c97d | 2017-03-23 19:34:26 -0500 | [diff] [blame] | 59 | config FPGA_MGR_XILINX_SPI |
| 60 | tristate "Xilinx Configuration over Slave Serial (SPI)" |
| 61 | depends on SPI |
| 62 | help |
| 63 | FPGA manager driver support for Xilinx FPGA configuration |
| 64 | over slave serial interface. |
| 65 | |
Alan Tull | 84e93f1 | 2017-11-15 14:20:27 -0600 | [diff] [blame] | 66 | config FPGA_MGR_ICE40_SPI |
| 67 | tristate "Lattice iCE40 SPI" |
| 68 | depends on OF && SPI |
Moritz Fischer | 3778470 | 2015-10-16 15:42:30 -0700 | [diff] [blame] | 69 | help |
Alan Tull | 84e93f1 | 2017-11-15 14:20:27 -0600 | [diff] [blame] | 70 | FPGA manager driver support for Lattice iCE40 FPGAs over SPI. |
| 71 | |
Paolo Pisati | 88fb3a0 | 2018-04-16 20:43:36 -0700 | [diff] [blame] | 72 | config FPGA_MGR_MACHXO2_SPI |
| 73 | tristate "Lattice MachXO2 SPI" |
| 74 | depends on SPI |
| 75 | help |
| 76 | FPGA manager driver support for Lattice MachXO2 configuration |
| 77 | over slave SPI interface. |
| 78 | |
Alan Tull | 84e93f1 | 2017-11-15 14:20:27 -0600 | [diff] [blame] | 79 | config FPGA_MGR_TS73XX |
| 80 | tristate "Technologic Systems TS-73xx SBC FPGA Manager" |
| 81 | depends on ARCH_EP93XX && MACH_TS72XX |
| 82 | help |
| 83 | FPGA manager driver support for the Altera Cyclone II FPGA |
| 84 | present on the TS-73xx SBC boards. |
Moritz Fischer | 3778470 | 2015-10-16 15:42:30 -0700 | [diff] [blame] | 85 | |
Alan Tull | 21aeda9 | 2016-11-01 14:14:28 -0500 | [diff] [blame] | 86 | config FPGA_BRIDGE |
| 87 | tristate "FPGA Bridge Framework" |
Alan Tull | 21aeda9 | 2016-11-01 14:14:28 -0500 | [diff] [blame] | 88 | help |
| 89 | Say Y here if you want to support bridges connected between host |
| 90 | processors and FPGAs or between FPGAs. |
| 91 | |
Alan Tull | e5f8efa | 2016-11-01 14:14:30 -0500 | [diff] [blame] | 92 | config SOCFPGA_FPGA_BRIDGE |
| 93 | tristate "Altera SoCFPGA FPGA Bridges" |
| 94 | depends on ARCH_SOCFPGA && FPGA_BRIDGE |
| 95 | help |
| 96 | Say Y to enable drivers for FPGA bridges for Altera SOCFPGA |
| 97 | devices. |
| 98 | |
Alan Tull | ca24a64 | 2016-11-01 14:14:31 -0500 | [diff] [blame] | 99 | config ALTERA_FREEZE_BRIDGE |
| 100 | tristate "Altera FPGA Freeze Bridge" |
| 101 | depends on ARCH_SOCFPGA && FPGA_BRIDGE |
| 102 | help |
| 103 | Say Y to enable drivers for Altera FPGA Freeze bridges. A |
| 104 | freeze bridge is a bridge that exists in the FPGA fabric to |
| 105 | isolate one region of the FPGA from the busses while that |
| 106 | region is being reprogrammed. |
| 107 | |
Moritz Fischer | 7e961c1 | 2017-03-24 10:33:21 -0500 | [diff] [blame] | 108 | config XILINX_PR_DECOUPLER |
| 109 | tristate "Xilinx LogiCORE PR Decoupler" |
| 110 | depends on FPGA_BRIDGE |
| 111 | depends on HAS_IOMEM |
| 112 | help |
| 113 | Say Y to enable drivers for Xilinx LogiCORE PR Decoupler. |
| 114 | The PR Decoupler exists in the FPGA fabric to isolate one |
| 115 | region of the FPGA from the busses while that region is |
| 116 | being reprogrammed during partial reconfig. |
| 117 | |
Alan Tull | 84e93f1 | 2017-11-15 14:20:27 -0600 | [diff] [blame] | 118 | config FPGA_REGION |
| 119 | tristate "FPGA Region" |
| 120 | depends on FPGA_BRIDGE |
| 121 | help |
| 122 | FPGA Region common code. A FPGA Region controls a FPGA Manager |
| 123 | and the FPGA Bridges associated with either a reconfigurable |
| 124 | region of an FPGA or a whole FPGA. |
| 125 | |
| 126 | config OF_FPGA_REGION |
| 127 | tristate "FPGA Region Device Tree Overlay Support" |
| 128 | depends on OF && FPGA_REGION |
| 129 | help |
| 130 | Support for loading FPGA images by applying a Device Tree |
| 131 | overlay. |
| 132 | |
Wu Hao | 543be3d | 2018-06-30 08:53:13 +0800 | [diff] [blame^] | 133 | config FPGA_DFL |
| 134 | tristate "FPGA Device Feature List (DFL) support" |
| 135 | select FPGA_BRIDGE |
| 136 | select FPGA_REGION |
| 137 | help |
| 138 | Device Feature List (DFL) defines a feature list structure that |
| 139 | creates a linked list of feature headers within the MMIO space |
| 140 | to provide an extensible way of adding features for FPGA. |
| 141 | Driver can walk through the feature headers to enumerate feature |
| 142 | devices (e.g. FPGA Management Engine, Port and Accelerator |
| 143 | Function Unit) and their private features for target FPGA devices. |
| 144 | |
| 145 | Select this option to enable common support for Field-Programmable |
| 146 | Gate Array (FPGA) solutions which implement Device Feature List. |
| 147 | It provides enumeration APIs and feature device infrastructure. |
| 148 | |
Alan Tull | fab6266 | 2015-10-07 16:36:29 +0100 | [diff] [blame] | 149 | endif # FPGA |