Vivien Didelot | 18abed2 | 2016-11-04 03:23:26 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Marvell 88E6xxx Switch Port Registers support |
| 3 | * |
| 4 | * Copyright (c) 2008 Marvell Semiconductor |
| 5 | * |
Vivien Didelot | 4333d61 | 2017-03-28 15:10:36 -0400 | [diff] [blame] | 6 | * Copyright (c) 2016-2017 Savoir-faire Linux Inc. |
| 7 | * Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
Vivien Didelot | 18abed2 | 2016-11-04 03:23:26 +0100 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | */ |
| 14 | |
Vivien Didelot | ddcbabf | 2017-06-17 23:07:14 -0400 | [diff] [blame] | 15 | #include <linux/bitfield.h> |
Vivien Didelot | f894c29 | 2017-06-08 18:34:10 -0400 | [diff] [blame] | 16 | #include <linux/if_bridge.h> |
Andrew Lunn | f39908d | 2017-02-04 20:02:50 +0100 | [diff] [blame] | 17 | #include <linux/phy.h> |
Russell King | c9a2356 | 2018-05-10 13:17:35 -0700 | [diff] [blame] | 18 | #include <linux/phylink.h> |
Vivien Didelot | 4d5f2ba7 | 2017-06-02 17:06:15 -0400 | [diff] [blame] | 19 | |
| 20 | #include "chip.h" |
Vivien Didelot | 18abed2 | 2016-11-04 03:23:26 +0100 | [diff] [blame] | 21 | #include "port.h" |
| 22 | |
| 23 | int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, |
| 24 | u16 *val) |
| 25 | { |
| 26 | int addr = chip->info->port_base_addr + port; |
| 27 | |
| 28 | return mv88e6xxx_read(chip, addr, reg, val); |
| 29 | } |
| 30 | |
| 31 | int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, |
| 32 | u16 val) |
| 33 | { |
| 34 | int addr = chip->info->port_base_addr + port; |
| 35 | |
| 36 | return mv88e6xxx_write(chip, addr, reg, val); |
| 37 | } |
Vivien Didelot | e28def33 | 2016-11-04 03:23:27 +0100 | [diff] [blame] | 38 | |
Andrew Lunn | 54186b9 | 2018-08-09 15:38:37 +0200 | [diff] [blame^] | 39 | /* Offset 0x00: MAC (or PCS or Physical) Status Register |
| 40 | * |
| 41 | * For most devices, this is read only. However the 6185 has the MyPause |
| 42 | * bit read/write. |
| 43 | */ |
| 44 | int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, |
| 45 | int pause) |
| 46 | { |
| 47 | u16 reg; |
| 48 | int err; |
| 49 | |
| 50 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); |
| 51 | if (err) |
| 52 | return err; |
| 53 | |
| 54 | if (pause) |
| 55 | reg |= MV88E6XXX_PORT_STS_MY_PAUSE; |
| 56 | else |
| 57 | reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE; |
| 58 | |
| 59 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); |
| 60 | } |
| 61 | |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 62 | /* Offset 0x01: MAC (or PCS or Physical) Control Register |
| 63 | * |
| 64 | * Link, Duplex and Flow Control have one force bit, one value bit. |
Vivien Didelot | 96a2b40 | 2016-11-04 03:23:35 +0100 | [diff] [blame] | 65 | * |
| 66 | * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value. |
| 67 | * Alternative values require the 200BASE (or AltSpeed) bit 12 set. |
| 68 | * Newer chips need a ForcedSpd bit 13 set to consider the value. |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 69 | */ |
| 70 | |
Vivien Didelot | a0a0f62 | 2016-11-04 03:23:34 +0100 | [diff] [blame] | 71 | static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, |
| 72 | phy_interface_t mode) |
| 73 | { |
| 74 | u16 reg; |
| 75 | int err; |
| 76 | |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 77 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); |
Vivien Didelot | a0a0f62 | 2016-11-04 03:23:34 +0100 | [diff] [blame] | 78 | if (err) |
| 79 | return err; |
| 80 | |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 81 | reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | |
| 82 | MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK); |
Vivien Didelot | a0a0f62 | 2016-11-04 03:23:34 +0100 | [diff] [blame] | 83 | |
| 84 | switch (mode) { |
| 85 | case PHY_INTERFACE_MODE_RGMII_RXID: |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 86 | reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK; |
Vivien Didelot | a0a0f62 | 2016-11-04 03:23:34 +0100 | [diff] [blame] | 87 | break; |
| 88 | case PHY_INTERFACE_MODE_RGMII_TXID: |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 89 | reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; |
Vivien Didelot | a0a0f62 | 2016-11-04 03:23:34 +0100 | [diff] [blame] | 90 | break; |
| 91 | case PHY_INTERFACE_MODE_RGMII_ID: |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 92 | reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | |
| 93 | MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; |
Vivien Didelot | a0a0f62 | 2016-11-04 03:23:34 +0100 | [diff] [blame] | 94 | break; |
Andrew Lunn | fedf186 | 2016-11-10 15:44:00 +0100 | [diff] [blame] | 95 | case PHY_INTERFACE_MODE_RGMII: |
Vivien Didelot | a0a0f62 | 2016-11-04 03:23:34 +0100 | [diff] [blame] | 96 | break; |
Andrew Lunn | fedf186 | 2016-11-10 15:44:00 +0100 | [diff] [blame] | 97 | default: |
| 98 | return 0; |
Vivien Didelot | a0a0f62 | 2016-11-04 03:23:34 +0100 | [diff] [blame] | 99 | } |
| 100 | |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 101 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); |
Vivien Didelot | a0a0f62 | 2016-11-04 03:23:34 +0100 | [diff] [blame] | 102 | if (err) |
| 103 | return err; |
| 104 | |
Vivien Didelot | 774439e5 | 2017-06-08 18:34:08 -0400 | [diff] [blame] | 105 | dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port, |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 106 | reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no", |
| 107 | reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no"); |
Vivien Didelot | a0a0f62 | 2016-11-04 03:23:34 +0100 | [diff] [blame] | 108 | |
| 109 | return 0; |
| 110 | } |
| 111 | |
| 112 | int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, |
| 113 | phy_interface_t mode) |
| 114 | { |
| 115 | if (port < 5) |
| 116 | return -EOPNOTSUPP; |
| 117 | |
| 118 | return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); |
| 119 | } |
| 120 | |
| 121 | int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, |
| 122 | phy_interface_t mode) |
| 123 | { |
| 124 | if (port != 0) |
| 125 | return -EOPNOTSUPP; |
| 126 | |
| 127 | return mv88e6xxx_port_set_rgmii_delay(chip, port, mode); |
| 128 | } |
| 129 | |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 130 | int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link) |
| 131 | { |
| 132 | u16 reg; |
| 133 | int err; |
| 134 | |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 135 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 136 | if (err) |
| 137 | return err; |
| 138 | |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 139 | reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | |
| 140 | MV88E6XXX_PORT_MAC_CTL_LINK_UP); |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 141 | |
| 142 | switch (link) { |
| 143 | case LINK_FORCED_DOWN: |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 144 | reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK; |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 145 | break; |
| 146 | case LINK_FORCED_UP: |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 147 | reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | |
| 148 | MV88E6XXX_PORT_MAC_CTL_LINK_UP; |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 149 | break; |
| 150 | case LINK_UNFORCED: |
| 151 | /* normal link detection */ |
| 152 | break; |
| 153 | default: |
| 154 | return -EINVAL; |
| 155 | } |
| 156 | |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 157 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 158 | if (err) |
| 159 | return err; |
| 160 | |
Vivien Didelot | 774439e5 | 2017-06-08 18:34:08 -0400 | [diff] [blame] | 161 | dev_dbg(chip->dev, "p%d: %s link %s\n", port, |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 162 | reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce", |
| 163 | reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down"); |
Vivien Didelot | 08ef7f1 | 2016-11-04 03:23:32 +0100 | [diff] [blame] | 164 | |
| 165 | return 0; |
| 166 | } |
| 167 | |
Vivien Didelot | 7f1ae07 | 2016-11-04 03:23:33 +0100 | [diff] [blame] | 168 | int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup) |
| 169 | { |
| 170 | u16 reg; |
| 171 | int err; |
| 172 | |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 173 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); |
Vivien Didelot | 7f1ae07 | 2016-11-04 03:23:33 +0100 | [diff] [blame] | 174 | if (err) |
| 175 | return err; |
| 176 | |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 177 | reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | |
| 178 | MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL); |
Vivien Didelot | 7f1ae07 | 2016-11-04 03:23:33 +0100 | [diff] [blame] | 179 | |
| 180 | switch (dup) { |
| 181 | case DUPLEX_HALF: |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 182 | reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; |
Vivien Didelot | 7f1ae07 | 2016-11-04 03:23:33 +0100 | [diff] [blame] | 183 | break; |
| 184 | case DUPLEX_FULL: |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 185 | reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | |
| 186 | MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL; |
Vivien Didelot | 7f1ae07 | 2016-11-04 03:23:33 +0100 | [diff] [blame] | 187 | break; |
| 188 | case DUPLEX_UNFORCED: |
| 189 | /* normal duplex detection */ |
| 190 | break; |
| 191 | default: |
| 192 | return -EINVAL; |
| 193 | } |
| 194 | |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 195 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); |
Vivien Didelot | 7f1ae07 | 2016-11-04 03:23:33 +0100 | [diff] [blame] | 196 | if (err) |
| 197 | return err; |
| 198 | |
Vivien Didelot | 774439e5 | 2017-06-08 18:34:08 -0400 | [diff] [blame] | 199 | dev_dbg(chip->dev, "p%d: %s %s duplex\n", port, |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 200 | reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", |
| 201 | reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); |
Vivien Didelot | 7f1ae07 | 2016-11-04 03:23:33 +0100 | [diff] [blame] | 202 | |
| 203 | return 0; |
| 204 | } |
| 205 | |
Vivien Didelot | 96a2b40 | 2016-11-04 03:23:35 +0100 | [diff] [blame] | 206 | static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip *chip, int port, |
| 207 | int speed, bool alt_bit, bool force_bit) |
| 208 | { |
| 209 | u16 reg, ctrl; |
| 210 | int err; |
| 211 | |
| 212 | switch (speed) { |
| 213 | case 10: |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 214 | ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10; |
Vivien Didelot | 96a2b40 | 2016-11-04 03:23:35 +0100 | [diff] [blame] | 215 | break; |
| 216 | case 100: |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 217 | ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100; |
Vivien Didelot | 96a2b40 | 2016-11-04 03:23:35 +0100 | [diff] [blame] | 218 | break; |
| 219 | case 200: |
| 220 | if (alt_bit) |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 221 | ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 | |
| 222 | MV88E6390_PORT_MAC_CTL_ALTSPEED; |
Vivien Didelot | 96a2b40 | 2016-11-04 03:23:35 +0100 | [diff] [blame] | 223 | else |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 224 | ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200; |
Vivien Didelot | 96a2b40 | 2016-11-04 03:23:35 +0100 | [diff] [blame] | 225 | break; |
| 226 | case 1000: |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 227 | ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000; |
Vivien Didelot | 96a2b40 | 2016-11-04 03:23:35 +0100 | [diff] [blame] | 228 | break; |
| 229 | case 2500: |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 230 | ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 | |
| 231 | MV88E6390_PORT_MAC_CTL_ALTSPEED; |
Vivien Didelot | 96a2b40 | 2016-11-04 03:23:35 +0100 | [diff] [blame] | 232 | break; |
| 233 | case 10000: |
| 234 | /* all bits set, fall through... */ |
| 235 | case SPEED_UNFORCED: |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 236 | ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED; |
Vivien Didelot | 96a2b40 | 2016-11-04 03:23:35 +0100 | [diff] [blame] | 237 | break; |
| 238 | default: |
| 239 | return -EOPNOTSUPP; |
| 240 | } |
| 241 | |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 242 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); |
Vivien Didelot | 96a2b40 | 2016-11-04 03:23:35 +0100 | [diff] [blame] | 243 | if (err) |
| 244 | return err; |
| 245 | |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 246 | reg &= ~MV88E6XXX_PORT_MAC_CTL_SPEED_MASK; |
Vivien Didelot | 96a2b40 | 2016-11-04 03:23:35 +0100 | [diff] [blame] | 247 | if (alt_bit) |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 248 | reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED; |
Vivien Didelot | 96a2b40 | 2016-11-04 03:23:35 +0100 | [diff] [blame] | 249 | if (force_bit) { |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 250 | reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED; |
Andrew Lunn | 0b6e3d0 | 2016-11-16 04:26:48 +0100 | [diff] [blame] | 251 | if (speed != SPEED_UNFORCED) |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 252 | ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED; |
Vivien Didelot | 96a2b40 | 2016-11-04 03:23:35 +0100 | [diff] [blame] | 253 | } |
| 254 | reg |= ctrl; |
| 255 | |
Vivien Didelot | 5ee5557 | 2017-06-12 12:37:34 -0400 | [diff] [blame] | 256 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); |
Vivien Didelot | 96a2b40 | 2016-11-04 03:23:35 +0100 | [diff] [blame] | 257 | if (err) |
| 258 | return err; |
| 259 | |
| 260 | if (speed) |
Vivien Didelot | 774439e5 | 2017-06-08 18:34:08 -0400 | [diff] [blame] | 261 | dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed); |
Vivien Didelot | 96a2b40 | 2016-11-04 03:23:35 +0100 | [diff] [blame] | 262 | else |
Vivien Didelot | 774439e5 | 2017-06-08 18:34:08 -0400 | [diff] [blame] | 263 | dev_dbg(chip->dev, "p%d: Speed unforced\n", port); |
Vivien Didelot | 96a2b40 | 2016-11-04 03:23:35 +0100 | [diff] [blame] | 264 | |
| 265 | return 0; |
| 266 | } |
| 267 | |
| 268 | /* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */ |
| 269 | int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) |
| 270 | { |
| 271 | if (speed == SPEED_MAX) |
| 272 | speed = 200; |
| 273 | |
| 274 | if (speed > 200) |
| 275 | return -EOPNOTSUPP; |
| 276 | |
| 277 | /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */ |
| 278 | return mv88e6xxx_port_set_speed(chip, port, speed, false, false); |
| 279 | } |
| 280 | |
| 281 | /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */ |
| 282 | int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) |
| 283 | { |
| 284 | if (speed == SPEED_MAX) |
| 285 | speed = 1000; |
| 286 | |
| 287 | if (speed == 200 || speed > 1000) |
| 288 | return -EOPNOTSUPP; |
| 289 | |
| 290 | return mv88e6xxx_port_set_speed(chip, port, speed, false, false); |
| 291 | } |
| 292 | |
| 293 | /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */ |
| 294 | int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) |
| 295 | { |
| 296 | if (speed == SPEED_MAX) |
| 297 | speed = 1000; |
| 298 | |
| 299 | if (speed > 1000) |
| 300 | return -EOPNOTSUPP; |
| 301 | |
| 302 | if (speed == 200 && port < 5) |
| 303 | return -EOPNOTSUPP; |
| 304 | |
| 305 | return mv88e6xxx_port_set_speed(chip, port, speed, true, false); |
| 306 | } |
| 307 | |
| 308 | /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */ |
| 309 | int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) |
| 310 | { |
| 311 | if (speed == SPEED_MAX) |
| 312 | speed = port < 9 ? 1000 : 2500; |
| 313 | |
| 314 | if (speed > 2500) |
| 315 | return -EOPNOTSUPP; |
| 316 | |
| 317 | if (speed == 200 && port != 0) |
| 318 | return -EOPNOTSUPP; |
| 319 | |
| 320 | if (speed == 2500 && port < 9) |
| 321 | return -EOPNOTSUPP; |
| 322 | |
| 323 | return mv88e6xxx_port_set_speed(chip, port, speed, true, true); |
| 324 | } |
| 325 | |
| 326 | /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */ |
| 327 | int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed) |
| 328 | { |
| 329 | if (speed == SPEED_MAX) |
| 330 | speed = port < 9 ? 1000 : 10000; |
| 331 | |
| 332 | if (speed == 200 && port != 0) |
| 333 | return -EOPNOTSUPP; |
| 334 | |
| 335 | if (speed >= 2500 && port < 9) |
| 336 | return -EOPNOTSUPP; |
| 337 | |
| 338 | return mv88e6xxx_port_set_speed(chip, port, speed, true, true); |
| 339 | } |
| 340 | |
Andrew Lunn | f39908d | 2017-02-04 20:02:50 +0100 | [diff] [blame] | 341 | int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, |
| 342 | phy_interface_t mode) |
| 343 | { |
| 344 | u16 reg; |
| 345 | u16 cmode; |
| 346 | int err; |
| 347 | |
| 348 | if (mode == PHY_INTERFACE_MODE_NA) |
| 349 | return 0; |
| 350 | |
| 351 | if (port != 9 && port != 10) |
| 352 | return -EOPNOTSUPP; |
| 353 | |
| 354 | switch (mode) { |
| 355 | case PHY_INTERFACE_MODE_1000BASEX: |
Vivien Didelot | 5f83dc9 | 2017-06-12 12:37:33 -0400 | [diff] [blame] | 356 | cmode = MV88E6XXX_PORT_STS_CMODE_1000BASE_X; |
Andrew Lunn | f39908d | 2017-02-04 20:02:50 +0100 | [diff] [blame] | 357 | break; |
| 358 | case PHY_INTERFACE_MODE_SGMII: |
Vivien Didelot | 5f83dc9 | 2017-06-12 12:37:33 -0400 | [diff] [blame] | 359 | cmode = MV88E6XXX_PORT_STS_CMODE_SGMII; |
Andrew Lunn | f39908d | 2017-02-04 20:02:50 +0100 | [diff] [blame] | 360 | break; |
| 361 | case PHY_INTERFACE_MODE_2500BASEX: |
Vivien Didelot | 5f83dc9 | 2017-06-12 12:37:33 -0400 | [diff] [blame] | 362 | cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX; |
Andrew Lunn | f39908d | 2017-02-04 20:02:50 +0100 | [diff] [blame] | 363 | break; |
| 364 | case PHY_INTERFACE_MODE_XGMII: |
Russell King | 2e51a8d | 2017-12-12 09:29:46 +0000 | [diff] [blame] | 365 | case PHY_INTERFACE_MODE_XAUI: |
Vivien Didelot | 5f83dc9 | 2017-06-12 12:37:33 -0400 | [diff] [blame] | 366 | cmode = MV88E6XXX_PORT_STS_CMODE_XAUI; |
Andrew Lunn | f39908d | 2017-02-04 20:02:50 +0100 | [diff] [blame] | 367 | break; |
| 368 | case PHY_INTERFACE_MODE_RXAUI: |
Vivien Didelot | 5f83dc9 | 2017-06-12 12:37:33 -0400 | [diff] [blame] | 369 | cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI; |
Andrew Lunn | f39908d | 2017-02-04 20:02:50 +0100 | [diff] [blame] | 370 | break; |
| 371 | default: |
| 372 | cmode = 0; |
| 373 | } |
| 374 | |
| 375 | if (cmode) { |
Vivien Didelot | 5f83dc9 | 2017-06-12 12:37:33 -0400 | [diff] [blame] | 376 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); |
Andrew Lunn | f39908d | 2017-02-04 20:02:50 +0100 | [diff] [blame] | 377 | if (err) |
| 378 | return err; |
| 379 | |
Vivien Didelot | 5f83dc9 | 2017-06-12 12:37:33 -0400 | [diff] [blame] | 380 | reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK; |
Andrew Lunn | f39908d | 2017-02-04 20:02:50 +0100 | [diff] [blame] | 381 | reg |= cmode; |
| 382 | |
Vivien Didelot | 5f83dc9 | 2017-06-12 12:37:33 -0400 | [diff] [blame] | 383 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); |
Andrew Lunn | f39908d | 2017-02-04 20:02:50 +0100 | [diff] [blame] | 384 | if (err) |
| 385 | return err; |
| 386 | } |
| 387 | |
| 388 | return 0; |
| 389 | } |
| 390 | |
| 391 | int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) |
| 392 | { |
| 393 | int err; |
| 394 | u16 reg; |
| 395 | |
Vivien Didelot | 5f83dc9 | 2017-06-12 12:37:33 -0400 | [diff] [blame] | 396 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); |
Andrew Lunn | f39908d | 2017-02-04 20:02:50 +0100 | [diff] [blame] | 397 | if (err) |
| 398 | return err; |
| 399 | |
Vivien Didelot | 5f83dc9 | 2017-06-12 12:37:33 -0400 | [diff] [blame] | 400 | *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK; |
Andrew Lunn | f39908d | 2017-02-04 20:02:50 +0100 | [diff] [blame] | 401 | |
| 402 | return 0; |
| 403 | } |
| 404 | |
Russell King | c9a2356 | 2018-05-10 13:17:35 -0700 | [diff] [blame] | 405 | int mv88e6xxx_port_link_state(struct mv88e6xxx_chip *chip, int port, |
| 406 | struct phylink_link_state *state) |
| 407 | { |
| 408 | int err; |
| 409 | u16 reg; |
| 410 | |
| 411 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); |
| 412 | if (err) |
| 413 | return err; |
| 414 | |
| 415 | switch (reg & MV88E6XXX_PORT_STS_SPEED_MASK) { |
| 416 | case MV88E6XXX_PORT_STS_SPEED_10: |
| 417 | state->speed = SPEED_10; |
| 418 | break; |
| 419 | case MV88E6XXX_PORT_STS_SPEED_100: |
| 420 | state->speed = SPEED_100; |
| 421 | break; |
| 422 | case MV88E6XXX_PORT_STS_SPEED_1000: |
| 423 | state->speed = SPEED_1000; |
| 424 | break; |
| 425 | case MV88E6XXX_PORT_STS_SPEED_10000: |
| 426 | if ((reg &MV88E6XXX_PORT_STS_CMODE_MASK) == |
| 427 | MV88E6XXX_PORT_STS_CMODE_2500BASEX) |
| 428 | state->speed = SPEED_2500; |
| 429 | else |
| 430 | state->speed = SPEED_10000; |
| 431 | break; |
| 432 | } |
| 433 | |
| 434 | state->duplex = reg & MV88E6XXX_PORT_STS_DUPLEX ? |
| 435 | DUPLEX_FULL : DUPLEX_HALF; |
| 436 | state->link = !!(reg & MV88E6XXX_PORT_STS_LINK); |
| 437 | state->an_enabled = 1; |
| 438 | state->an_complete = state->link; |
| 439 | |
| 440 | return 0; |
| 441 | } |
| 442 | |
Vivien Didelot | 6c96bbf | 2017-06-12 12:37:35 -0400 | [diff] [blame] | 443 | /* Offset 0x02: Jamming Control |
Andrew Lunn | b35d322a | 2016-12-03 04:45:19 +0100 | [diff] [blame] | 444 | * |
| 445 | * Do not limit the period of time that this port can be paused for by |
| 446 | * the remote end or the period of time that this port can pause the |
| 447 | * remote end. |
| 448 | */ |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 449 | int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, |
| 450 | u8 out) |
Andrew Lunn | b35d322a | 2016-12-03 04:45:19 +0100 | [diff] [blame] | 451 | { |
Vivien Didelot | 6c96bbf | 2017-06-12 12:37:35 -0400 | [diff] [blame] | 452 | return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL, |
| 453 | out << 8 | in); |
Andrew Lunn | b35d322a | 2016-12-03 04:45:19 +0100 | [diff] [blame] | 454 | } |
| 455 | |
Vivien Didelot | 0898432 | 2017-06-08 18:34:12 -0400 | [diff] [blame] | 456 | int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, |
| 457 | u8 out) |
Andrew Lunn | 3ce0e65 | 2016-12-03 04:45:20 +0100 | [diff] [blame] | 458 | { |
| 459 | int err; |
| 460 | |
Vivien Didelot | 6c96bbf | 2017-06-12 12:37:35 -0400 | [diff] [blame] | 461 | err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, |
| 462 | MV88E6390_PORT_FLOW_CTL_UPDATE | |
| 463 | MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in); |
Andrew Lunn | 3ce0e65 | 2016-12-03 04:45:20 +0100 | [diff] [blame] | 464 | if (err) |
| 465 | return err; |
| 466 | |
Vivien Didelot | 6c96bbf | 2017-06-12 12:37:35 -0400 | [diff] [blame] | 467 | return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL, |
| 468 | MV88E6390_PORT_FLOW_CTL_UPDATE | |
| 469 | MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out); |
Andrew Lunn | 3ce0e65 | 2016-12-03 04:45:20 +0100 | [diff] [blame] | 470 | } |
| 471 | |
Vivien Didelot | e28def33 | 2016-11-04 03:23:27 +0100 | [diff] [blame] | 472 | /* Offset 0x04: Port Control Register */ |
| 473 | |
| 474 | static const char * const mv88e6xxx_port_state_names[] = { |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 475 | [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled", |
| 476 | [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening", |
| 477 | [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning", |
| 478 | [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding", |
Vivien Didelot | e28def33 | 2016-11-04 03:23:27 +0100 | [diff] [blame] | 479 | }; |
| 480 | |
| 481 | int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state) |
| 482 | { |
| 483 | u16 reg; |
| 484 | int err; |
| 485 | |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 486 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); |
Vivien Didelot | e28def33 | 2016-11-04 03:23:27 +0100 | [diff] [blame] | 487 | if (err) |
| 488 | return err; |
| 489 | |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 490 | reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK; |
Vivien Didelot | f894c29 | 2017-06-08 18:34:10 -0400 | [diff] [blame] | 491 | |
| 492 | switch (state) { |
| 493 | case BR_STATE_DISABLED: |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 494 | state = MV88E6XXX_PORT_CTL0_STATE_DISABLED; |
Vivien Didelot | f894c29 | 2017-06-08 18:34:10 -0400 | [diff] [blame] | 495 | break; |
| 496 | case BR_STATE_BLOCKING: |
| 497 | case BR_STATE_LISTENING: |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 498 | state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; |
Vivien Didelot | f894c29 | 2017-06-08 18:34:10 -0400 | [diff] [blame] | 499 | break; |
| 500 | case BR_STATE_LEARNING: |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 501 | state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; |
Vivien Didelot | f894c29 | 2017-06-08 18:34:10 -0400 | [diff] [blame] | 502 | break; |
| 503 | case BR_STATE_FORWARDING: |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 504 | state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; |
Vivien Didelot | f894c29 | 2017-06-08 18:34:10 -0400 | [diff] [blame] | 505 | break; |
| 506 | default: |
| 507 | return -EINVAL; |
| 508 | } |
| 509 | |
Vivien Didelot | e28def33 | 2016-11-04 03:23:27 +0100 | [diff] [blame] | 510 | reg |= state; |
| 511 | |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 512 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); |
Vivien Didelot | e28def33 | 2016-11-04 03:23:27 +0100 | [diff] [blame] | 513 | if (err) |
| 514 | return err; |
| 515 | |
Vivien Didelot | 774439e5 | 2017-06-08 18:34:08 -0400 | [diff] [blame] | 516 | dev_dbg(chip->dev, "p%d: PortState set to %s\n", port, |
| 517 | mv88e6xxx_port_state_names[state]); |
Vivien Didelot | e28def33 | 2016-11-04 03:23:27 +0100 | [diff] [blame] | 518 | |
| 519 | return 0; |
| 520 | } |
Vivien Didelot | 5a7921f | 2016-11-04 03:23:28 +0100 | [diff] [blame] | 521 | |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 522 | int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, |
Vivien Didelot | 31bef4e | 2017-06-08 18:34:09 -0400 | [diff] [blame] | 523 | enum mv88e6xxx_egress_mode mode) |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 524 | { |
| 525 | int err; |
| 526 | u16 reg; |
| 527 | |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 528 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 529 | if (err) |
| 530 | return err; |
| 531 | |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 532 | reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK; |
Vivien Didelot | 31bef4e | 2017-06-08 18:34:09 -0400 | [diff] [blame] | 533 | |
| 534 | switch (mode) { |
| 535 | case MV88E6XXX_EGRESS_MODE_UNMODIFIED: |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 536 | reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED; |
Vivien Didelot | 31bef4e | 2017-06-08 18:34:09 -0400 | [diff] [blame] | 537 | break; |
| 538 | case MV88E6XXX_EGRESS_MODE_UNTAGGED: |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 539 | reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED; |
Vivien Didelot | 31bef4e | 2017-06-08 18:34:09 -0400 | [diff] [blame] | 540 | break; |
| 541 | case MV88E6XXX_EGRESS_MODE_TAGGED: |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 542 | reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED; |
Vivien Didelot | 31bef4e | 2017-06-08 18:34:09 -0400 | [diff] [blame] | 543 | break; |
| 544 | case MV88E6XXX_EGRESS_MODE_ETHERTYPE: |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 545 | reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA; |
Vivien Didelot | 31bef4e | 2017-06-08 18:34:09 -0400 | [diff] [blame] | 546 | break; |
| 547 | default: |
| 548 | return -EINVAL; |
| 549 | } |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 550 | |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 551 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 552 | } |
| 553 | |
| 554 | int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, |
| 555 | enum mv88e6xxx_frame_mode mode) |
| 556 | { |
| 557 | int err; |
| 558 | u16 reg; |
| 559 | |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 560 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 561 | if (err) |
| 562 | return err; |
| 563 | |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 564 | reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 565 | |
| 566 | switch (mode) { |
| 567 | case MV88E6XXX_FRAME_MODE_NORMAL: |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 568 | reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 569 | break; |
| 570 | case MV88E6XXX_FRAME_MODE_DSA: |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 571 | reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 572 | break; |
| 573 | default: |
| 574 | return -EINVAL; |
| 575 | } |
| 576 | |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 577 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 578 | } |
| 579 | |
| 580 | int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, |
| 581 | enum mv88e6xxx_frame_mode mode) |
| 582 | { |
| 583 | int err; |
| 584 | u16 reg; |
| 585 | |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 586 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 587 | if (err) |
| 588 | return err; |
| 589 | |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 590 | reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 591 | |
| 592 | switch (mode) { |
| 593 | case MV88E6XXX_FRAME_MODE_NORMAL: |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 594 | reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 595 | break; |
| 596 | case MV88E6XXX_FRAME_MODE_DSA: |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 597 | reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 598 | break; |
| 599 | case MV88E6XXX_FRAME_MODE_PROVIDER: |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 600 | reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER; |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 601 | break; |
| 602 | case MV88E6XXX_FRAME_MODE_ETHERTYPE: |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 603 | reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA; |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 604 | break; |
| 605 | default: |
| 606 | return -EINVAL; |
| 607 | } |
| 608 | |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 609 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 610 | } |
| 611 | |
Vivien Didelot | 601aeed | 2017-03-11 16:13:00 -0500 | [diff] [blame] | 612 | static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, |
| 613 | int port, bool unicast) |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 614 | { |
| 615 | int err; |
| 616 | u16 reg; |
| 617 | |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 618 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 619 | if (err) |
| 620 | return err; |
| 621 | |
Vivien Didelot | 601aeed | 2017-03-11 16:13:00 -0500 | [diff] [blame] | 622 | if (unicast) |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 623 | reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 624 | else |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 625 | reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 626 | |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 627 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 628 | } |
| 629 | |
Vivien Didelot | 601aeed | 2017-03-11 16:13:00 -0500 | [diff] [blame] | 630 | int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, |
| 631 | bool unicast, bool multicast) |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 632 | { |
| 633 | int err; |
| 634 | u16 reg; |
| 635 | |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 636 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 637 | if (err) |
| 638 | return err; |
| 639 | |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 640 | reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK; |
Vivien Didelot | 601aeed | 2017-03-11 16:13:00 -0500 | [diff] [blame] | 641 | |
| 642 | if (unicast && multicast) |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 643 | reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA; |
Vivien Didelot | 601aeed | 2017-03-11 16:13:00 -0500 | [diff] [blame] | 644 | else if (unicast) |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 645 | reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA; |
Vivien Didelot | 601aeed | 2017-03-11 16:13:00 -0500 | [diff] [blame] | 646 | else if (multicast) |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 647 | reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA; |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 648 | else |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 649 | reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA; |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 650 | |
Vivien Didelot | a89b433be | 2017-06-12 12:37:37 -0400 | [diff] [blame] | 651 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 652 | } |
| 653 | |
Vivien Didelot | b4e48c5 | 2016-11-04 03:23:29 +0100 | [diff] [blame] | 654 | /* Offset 0x05: Port Control 1 */ |
| 655 | |
Vivien Didelot | ea698f4 | 2017-03-11 16:12:50 -0500 | [diff] [blame] | 656 | int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, |
| 657 | bool message_port) |
| 658 | { |
| 659 | u16 val; |
| 660 | int err; |
| 661 | |
Vivien Didelot | cd985bb | 2017-06-12 12:37:38 -0400 | [diff] [blame] | 662 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val); |
Vivien Didelot | ea698f4 | 2017-03-11 16:12:50 -0500 | [diff] [blame] | 663 | if (err) |
| 664 | return err; |
| 665 | |
| 666 | if (message_port) |
Vivien Didelot | cd985bb | 2017-06-12 12:37:38 -0400 | [diff] [blame] | 667 | val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT; |
Vivien Didelot | ea698f4 | 2017-03-11 16:12:50 -0500 | [diff] [blame] | 668 | else |
Vivien Didelot | cd985bb | 2017-06-12 12:37:38 -0400 | [diff] [blame] | 669 | val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT; |
Vivien Didelot | ea698f4 | 2017-03-11 16:12:50 -0500 | [diff] [blame] | 670 | |
Vivien Didelot | cd985bb | 2017-06-12 12:37:38 -0400 | [diff] [blame] | 671 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val); |
Vivien Didelot | ea698f4 | 2017-03-11 16:12:50 -0500 | [diff] [blame] | 672 | } |
| 673 | |
Vivien Didelot | 5a7921f | 2016-11-04 03:23:28 +0100 | [diff] [blame] | 674 | /* Offset 0x06: Port Based VLAN Map */ |
| 675 | |
| 676 | int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map) |
| 677 | { |
Vivien Didelot | 4d294af | 2017-03-11 16:12:47 -0500 | [diff] [blame] | 678 | const u16 mask = mv88e6xxx_port_mask(chip); |
Vivien Didelot | 5a7921f | 2016-11-04 03:23:28 +0100 | [diff] [blame] | 679 | u16 reg; |
| 680 | int err; |
| 681 | |
Vivien Didelot | 7e5cc5f | 2017-06-12 12:37:39 -0400 | [diff] [blame] | 682 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); |
Vivien Didelot | 5a7921f | 2016-11-04 03:23:28 +0100 | [diff] [blame] | 683 | if (err) |
| 684 | return err; |
| 685 | |
| 686 | reg &= ~mask; |
| 687 | reg |= map & mask; |
| 688 | |
Vivien Didelot | 7e5cc5f | 2017-06-12 12:37:39 -0400 | [diff] [blame] | 689 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); |
Vivien Didelot | 5a7921f | 2016-11-04 03:23:28 +0100 | [diff] [blame] | 690 | if (err) |
| 691 | return err; |
| 692 | |
Vivien Didelot | 774439e5 | 2017-06-08 18:34:08 -0400 | [diff] [blame] | 693 | dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map); |
Vivien Didelot | 5a7921f | 2016-11-04 03:23:28 +0100 | [diff] [blame] | 694 | |
| 695 | return 0; |
| 696 | } |
Vivien Didelot | b4e48c5 | 2016-11-04 03:23:29 +0100 | [diff] [blame] | 697 | |
| 698 | int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid) |
| 699 | { |
| 700 | const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; |
| 701 | u16 reg; |
| 702 | int err; |
| 703 | |
| 704 | /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ |
Vivien Didelot | 7e5cc5f | 2017-06-12 12:37:39 -0400 | [diff] [blame] | 705 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); |
Vivien Didelot | b4e48c5 | 2016-11-04 03:23:29 +0100 | [diff] [blame] | 706 | if (err) |
| 707 | return err; |
| 708 | |
| 709 | *fid = (reg & 0xf000) >> 12; |
| 710 | |
| 711 | /* Port's default FID upper bits are located in reg 0x05, offset 0 */ |
| 712 | if (upper_mask) { |
Vivien Didelot | cd985bb | 2017-06-12 12:37:38 -0400 | [diff] [blame] | 713 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, |
| 714 | ®); |
Vivien Didelot | b4e48c5 | 2016-11-04 03:23:29 +0100 | [diff] [blame] | 715 | if (err) |
| 716 | return err; |
| 717 | |
| 718 | *fid |= (reg & upper_mask) << 4; |
| 719 | } |
| 720 | |
| 721 | return 0; |
| 722 | } |
| 723 | |
| 724 | int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid) |
| 725 | { |
| 726 | const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4; |
| 727 | u16 reg; |
| 728 | int err; |
| 729 | |
| 730 | if (fid >= mv88e6xxx_num_databases(chip)) |
| 731 | return -EINVAL; |
| 732 | |
| 733 | /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */ |
Vivien Didelot | 7e5cc5f | 2017-06-12 12:37:39 -0400 | [diff] [blame] | 734 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); |
Vivien Didelot | b4e48c5 | 2016-11-04 03:23:29 +0100 | [diff] [blame] | 735 | if (err) |
| 736 | return err; |
| 737 | |
| 738 | reg &= 0x0fff; |
| 739 | reg |= (fid & 0x000f) << 12; |
| 740 | |
Vivien Didelot | 7e5cc5f | 2017-06-12 12:37:39 -0400 | [diff] [blame] | 741 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); |
Vivien Didelot | b4e48c5 | 2016-11-04 03:23:29 +0100 | [diff] [blame] | 742 | if (err) |
| 743 | return err; |
| 744 | |
| 745 | /* Port's default FID upper bits are located in reg 0x05, offset 0 */ |
| 746 | if (upper_mask) { |
Vivien Didelot | cd985bb | 2017-06-12 12:37:38 -0400 | [diff] [blame] | 747 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, |
| 748 | ®); |
Vivien Didelot | b4e48c5 | 2016-11-04 03:23:29 +0100 | [diff] [blame] | 749 | if (err) |
| 750 | return err; |
| 751 | |
| 752 | reg &= ~upper_mask; |
| 753 | reg |= (fid >> 4) & upper_mask; |
| 754 | |
Vivien Didelot | cd985bb | 2017-06-12 12:37:38 -0400 | [diff] [blame] | 755 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, |
| 756 | reg); |
Vivien Didelot | b4e48c5 | 2016-11-04 03:23:29 +0100 | [diff] [blame] | 757 | if (err) |
| 758 | return err; |
| 759 | } |
| 760 | |
Vivien Didelot | 774439e5 | 2017-06-08 18:34:08 -0400 | [diff] [blame] | 761 | dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid); |
Vivien Didelot | b4e48c5 | 2016-11-04 03:23:29 +0100 | [diff] [blame] | 762 | |
| 763 | return 0; |
| 764 | } |
Vivien Didelot | 77064f3 | 2016-11-04 03:23:30 +0100 | [diff] [blame] | 765 | |
| 766 | /* Offset 0x07: Default Port VLAN ID & Priority */ |
| 767 | |
| 768 | int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid) |
| 769 | { |
| 770 | u16 reg; |
| 771 | int err; |
| 772 | |
Vivien Didelot | b7929fb | 2017-06-12 12:37:40 -0400 | [diff] [blame] | 773 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, |
| 774 | ®); |
Vivien Didelot | 77064f3 | 2016-11-04 03:23:30 +0100 | [diff] [blame] | 775 | if (err) |
| 776 | return err; |
| 777 | |
Vivien Didelot | b7929fb | 2017-06-12 12:37:40 -0400 | [diff] [blame] | 778 | *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; |
Vivien Didelot | 77064f3 | 2016-11-04 03:23:30 +0100 | [diff] [blame] | 779 | |
| 780 | return 0; |
| 781 | } |
| 782 | |
| 783 | int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid) |
| 784 | { |
| 785 | u16 reg; |
| 786 | int err; |
| 787 | |
Vivien Didelot | b7929fb | 2017-06-12 12:37:40 -0400 | [diff] [blame] | 788 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, |
| 789 | ®); |
Vivien Didelot | 77064f3 | 2016-11-04 03:23:30 +0100 | [diff] [blame] | 790 | if (err) |
| 791 | return err; |
| 792 | |
Vivien Didelot | b7929fb | 2017-06-12 12:37:40 -0400 | [diff] [blame] | 793 | reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK; |
| 794 | reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; |
Vivien Didelot | 77064f3 | 2016-11-04 03:23:30 +0100 | [diff] [blame] | 795 | |
Vivien Didelot | b7929fb | 2017-06-12 12:37:40 -0400 | [diff] [blame] | 796 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, |
| 797 | reg); |
Vivien Didelot | 77064f3 | 2016-11-04 03:23:30 +0100 | [diff] [blame] | 798 | if (err) |
| 799 | return err; |
| 800 | |
Vivien Didelot | 774439e5 | 2017-06-08 18:34:08 -0400 | [diff] [blame] | 801 | dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid); |
Vivien Didelot | 77064f3 | 2016-11-04 03:23:30 +0100 | [diff] [blame] | 802 | |
| 803 | return 0; |
| 804 | } |
Vivien Didelot | 385a099 | 2016-11-04 03:23:31 +0100 | [diff] [blame] | 805 | |
| 806 | /* Offset 0x08: Port Control 2 Register */ |
| 807 | |
| 808 | static const char * const mv88e6xxx_port_8021q_mode_names[] = { |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 809 | [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled", |
| 810 | [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback", |
| 811 | [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check", |
| 812 | [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure", |
Vivien Didelot | 385a099 | 2016-11-04 03:23:31 +0100 | [diff] [blame] | 813 | }; |
| 814 | |
Vivien Didelot | 601aeed | 2017-03-11 16:13:00 -0500 | [diff] [blame] | 815 | static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, |
| 816 | int port, bool multicast) |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 817 | { |
| 818 | int err; |
| 819 | u16 reg; |
| 820 | |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 821 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 822 | if (err) |
| 823 | return err; |
| 824 | |
Vivien Didelot | 601aeed | 2017-03-11 16:13:00 -0500 | [diff] [blame] | 825 | if (multicast) |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 826 | reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 827 | else |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 828 | reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 829 | |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 830 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 831 | } |
| 832 | |
Vivien Didelot | 601aeed | 2017-03-11 16:13:00 -0500 | [diff] [blame] | 833 | int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port, |
| 834 | bool unicast, bool multicast) |
| 835 | { |
| 836 | int err; |
| 837 | |
| 838 | err = mv88e6185_port_set_forward_unknown(chip, port, unicast); |
| 839 | if (err) |
| 840 | return err; |
| 841 | |
| 842 | return mv88e6185_port_set_default_forward(chip, port, multicast); |
| 843 | } |
| 844 | |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 845 | int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, |
| 846 | int upstream_port) |
| 847 | { |
| 848 | int err; |
| 849 | u16 reg; |
| 850 | |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 851 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 852 | if (err) |
| 853 | return err; |
| 854 | |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 855 | reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK; |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 856 | reg |= upstream_port; |
| 857 | |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 858 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 859 | } |
| 860 | |
Vivien Didelot | 385a099 | 2016-11-04 03:23:31 +0100 | [diff] [blame] | 861 | int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, |
| 862 | u16 mode) |
| 863 | { |
| 864 | u16 reg; |
| 865 | int err; |
| 866 | |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 867 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); |
Vivien Didelot | 385a099 | 2016-11-04 03:23:31 +0100 | [diff] [blame] | 868 | if (err) |
| 869 | return err; |
| 870 | |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 871 | reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; |
| 872 | reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; |
Vivien Didelot | 385a099 | 2016-11-04 03:23:31 +0100 | [diff] [blame] | 873 | |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 874 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); |
Vivien Didelot | 385a099 | 2016-11-04 03:23:31 +0100 | [diff] [blame] | 875 | if (err) |
| 876 | return err; |
| 877 | |
Vivien Didelot | 774439e5 | 2017-06-08 18:34:08 -0400 | [diff] [blame] | 878 | dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port, |
| 879 | mv88e6xxx_port_8021q_mode_names[mode]); |
Vivien Didelot | 385a099 | 2016-11-04 03:23:31 +0100 | [diff] [blame] | 880 | |
| 881 | return 0; |
| 882 | } |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 883 | |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 884 | int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port) |
| 885 | { |
| 886 | u16 reg; |
| 887 | int err; |
| 888 | |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 889 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 890 | if (err) |
| 891 | return err; |
| 892 | |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 893 | reg |= MV88E6XXX_PORT_CTL2_MAP_DA; |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 894 | |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 895 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); |
Andrew Lunn | a23b296 | 2017-02-04 20:15:28 +0100 | [diff] [blame] | 896 | } |
| 897 | |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 898 | int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, |
| 899 | size_t size) |
Andrew Lunn | 5f43666 | 2016-12-03 04:45:17 +0100 | [diff] [blame] | 900 | { |
| 901 | u16 reg; |
| 902 | int err; |
| 903 | |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 904 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); |
Andrew Lunn | 5f43666 | 2016-12-03 04:45:17 +0100 | [diff] [blame] | 905 | if (err) |
| 906 | return err; |
| 907 | |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 908 | reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK; |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 909 | |
| 910 | if (size <= 1522) |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 911 | reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522; |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 912 | else if (size <= 2048) |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 913 | reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048; |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 914 | else if (size <= 10240) |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 915 | reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240; |
Vivien Didelot | cd78265 | 2017-06-08 18:34:13 -0400 | [diff] [blame] | 916 | else |
| 917 | return -ERANGE; |
Andrew Lunn | 5f43666 | 2016-12-03 04:45:17 +0100 | [diff] [blame] | 918 | |
Vivien Didelot | 81c6edb | 2017-06-12 12:37:41 -0400 | [diff] [blame] | 919 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); |
Andrew Lunn | 5f43666 | 2016-12-03 04:45:17 +0100 | [diff] [blame] | 920 | } |
| 921 | |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 922 | /* Offset 0x09: Port Rate Control */ |
| 923 | |
| 924 | int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) |
| 925 | { |
Vivien Didelot | 2cb8cb1 | 2017-06-12 12:37:42 -0400 | [diff] [blame] | 926 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, |
| 927 | 0x0000); |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 928 | } |
| 929 | |
| 930 | int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) |
| 931 | { |
Vivien Didelot | 2cb8cb1 | 2017-06-12 12:37:42 -0400 | [diff] [blame] | 932 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, |
| 933 | 0x0001); |
Andrew Lunn | ef70b11 | 2016-12-03 04:45:18 +0100 | [diff] [blame] | 934 | } |
| 935 | |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 936 | /* Offset 0x0C: Port ATU Control */ |
| 937 | |
| 938 | int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port) |
| 939 | { |
Vivien Didelot | b810959 | 2017-06-12 12:37:45 -0400 | [diff] [blame] | 940 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0); |
Vivien Didelot | c8c9489 | 2017-03-11 16:13:01 -0500 | [diff] [blame] | 941 | } |
| 942 | |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 943 | /* Offset 0x0D: (Priority) Override Register */ |
| 944 | |
| 945 | int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port) |
| 946 | { |
Vivien Didelot | b810959 | 2017-06-12 12:37:45 -0400 | [diff] [blame] | 947 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0); |
Vivien Didelot | 9dbfb4e | 2017-03-11 16:13:02 -0500 | [diff] [blame] | 948 | } |
| 949 | |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 950 | /* Offset 0x0f: Port Ether type */ |
| 951 | |
| 952 | int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, |
| 953 | u16 etype) |
| 954 | { |
Vivien Didelot | b810959 | 2017-06-12 12:37:45 -0400 | [diff] [blame] | 955 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype); |
Andrew Lunn | 56995cb | 2016-12-03 04:35:19 +0100 | [diff] [blame] | 956 | } |
| 957 | |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 958 | /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3] |
| 959 | * Offset 0x19: Port IEEE Priority Remapping Registers [4-7] |
| 960 | */ |
| 961 | |
| 962 | int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port) |
| 963 | { |
| 964 | int err; |
| 965 | |
| 966 | /* Use a direct priority mapping for all IEEE tagged frames */ |
Vivien Didelot | 8009df9 | 2017-06-12 12:37:44 -0400 | [diff] [blame] | 967 | err = mv88e6xxx_port_write(chip, port, |
| 968 | MV88E6095_PORT_IEEE_PRIO_REMAP_0123, |
| 969 | 0x3210); |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 970 | if (err) |
| 971 | return err; |
| 972 | |
Vivien Didelot | 8009df9 | 2017-06-12 12:37:44 -0400 | [diff] [blame] | 973 | return mv88e6xxx_port_write(chip, port, |
| 974 | MV88E6095_PORT_IEEE_PRIO_REMAP_4567, |
| 975 | 0x7654); |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 976 | } |
| 977 | |
| 978 | static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip, |
Vivien Didelot | ddcbabf | 2017-06-17 23:07:14 -0400 | [diff] [blame] | 979 | int port, u16 table, u8 ptr, u16 data) |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 980 | { |
| 981 | u16 reg; |
| 982 | |
Vivien Didelot | ddcbabf | 2017-06-17 23:07:14 -0400 | [diff] [blame] | 983 | reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table | |
| 984 | (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) | |
| 985 | (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK); |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 986 | |
Vivien Didelot | 8009df9 | 2017-06-12 12:37:44 -0400 | [diff] [blame] | 987 | return mv88e6xxx_port_write(chip, port, |
| 988 | MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg); |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 989 | } |
| 990 | |
| 991 | int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port) |
| 992 | { |
| 993 | int err, i; |
Vivien Didelot | 8009df9 | 2017-06-12 12:37:44 -0400 | [diff] [blame] | 994 | u16 table; |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 995 | |
| 996 | for (i = 0; i <= 7; i++) { |
Vivien Didelot | 8009df9 | 2017-06-12 12:37:44 -0400 | [diff] [blame] | 997 | table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP; |
| 998 | err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, |
| 999 | (i | i << 4)); |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 1000 | if (err) |
| 1001 | return err; |
| 1002 | |
Vivien Didelot | 8009df9 | 2017-06-12 12:37:44 -0400 | [diff] [blame] | 1003 | table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP; |
| 1004 | err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 1005 | if (err) |
| 1006 | return err; |
| 1007 | |
Vivien Didelot | 8009df9 | 2017-06-12 12:37:44 -0400 | [diff] [blame] | 1008 | table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP; |
| 1009 | err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 1010 | if (err) |
| 1011 | return err; |
| 1012 | |
Vivien Didelot | 8009df9 | 2017-06-12 12:37:44 -0400 | [diff] [blame] | 1013 | table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP; |
| 1014 | err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i); |
Andrew Lunn | ef0a731 | 2016-12-03 04:35:16 +0100 | [diff] [blame] | 1015 | if (err) |
| 1016 | return err; |
| 1017 | } |
| 1018 | |
| 1019 | return 0; |
| 1020 | } |