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Manivannan Sadhasivam9d038b22020-11-26 14:01:38 +05301// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * SDX55 SoC device tree source
4 *
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2020, Linaro Ltd.
7 */
8
Manivannan Sadhasivamf0365492021-01-06 18:23:08 +05309#include <dt-bindings/clock/qcom,gcc-sdx55.h>
Manivannan Sadhasivam9d038b22020-11-26 14:01:38 +053010#include <dt-bindings/clock/qcom,rpmh.h>
Manivannan Sadhasivamce5a28d12021-04-08 22:34:50 +053011#include <dt-bindings/interconnect/qcom,sdx55.h>
Manivannan Sadhasivam9d038b22020-11-26 14:01:38 +053012#include <dt-bindings/interrupt-controller/arm-gic.h>
Vinod Koul3cef2d52021-01-06 18:23:20 +053013#include <dt-bindings/power/qcom-rpmpd.h>
Manivannan Sadhasivam9d038b22020-11-26 14:01:38 +053014#include <dt-bindings/soc/qcom,rpmh-rsc.h>
15
16/ {
17 #address-cells = <1>;
18 #size-cells = <1>;
19 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
20 interrupt-parent = <&intc>;
21
22 memory {
23 device_type = "memory";
24 reg = <0 0>;
25 };
26
27 clocks {
28 xo_board: xo-board {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <38400000>;
32 clock-output-names = "xo_board";
33 };
34
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <32000>;
39 };
Manivannan Sadhasivam4bd7bfb2021-01-06 18:23:14 +053040
41 nand_clk_dummy: nand-clk-dummy {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <32000>;
45 };
Manivannan Sadhasivam9d038b22020-11-26 14:01:38 +053046 };
47
48 cpus {
49 #address-cells = <1>;
50 #size-cells = <0>;
51
52 cpu0: cpu@0 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a7";
55 reg = <0x0>;
56 enable-method = "psci";
Manivannan Sadhasivam0ec7bde2021-04-08 22:34:45 +053057 clocks = <&apcs>;
58 power-domains = <&rpmhpd SDX55_CX>;
59 power-domain-names = "rpmhpd";
60 operating-points-v2 = <&cpu_opp_table>;
61 };
62 };
63
64 cpu_opp_table: cpu-opp-table {
65 compatible = "operating-points-v2";
66 opp-shared;
67
68 opp-345600000 {
69 opp-hz = /bits/ 64 <345600000>;
70 required-opps = <&rpmhpd_opp_low_svs>;
71 };
72
73 opp-576000000 {
74 opp-hz = /bits/ 64 <576000000>;
75 required-opps = <&rpmhpd_opp_svs>;
76 };
77
78 opp-1094400000 {
79 opp-hz = /bits/ 64 <1094400000>;
80 required-opps = <&rpmhpd_opp_nom>;
81 };
82
83 opp-1555200000 {
84 opp-hz = /bits/ 64 <1555200000>;
85 required-opps = <&rpmhpd_opp_turbo>;
Manivannan Sadhasivam9d038b22020-11-26 14:01:38 +053086 };
87 };
88
Manivannan Sadhasivam6bf66552021-04-08 22:34:49 +053089 firmware {
90 scm {
91 compatible = "qcom,scm-sdx55", "qcom,scm";
92 };
93 };
94
Manivannan Sadhasivam9d038b22020-11-26 14:01:38 +053095 psci {
96 compatible = "arm,psci-1.0";
97 method = "smc";
98 };
99
Vinod Koulec997702021-01-06 18:23:06 +0530100 reserved-memory {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 ranges;
104
105 hyp_mem: memory@8fc00000 {
106 no-map;
107 reg = <0x8fc00000 0x80000>;
108 };
109
110 ac_db_mem: memory@8fc80000 {
111 no-map;
112 reg = <0x8fc80000 0x40000>;
113 };
114
115 secdata_mem: memory@8fcfd000 {
116 no-map;
117 reg = <0x8fcfd000 0x1000>;
118 };
119
120 sbl_mem: memory@8fd00000 {
121 no-map;
122 reg = <0x8fd00000 0x100000>;
123 };
124
125 aop_image: memory@8fe00000 {
126 no-map;
127 reg = <0x8fe00000 0x20000>;
128 };
129
130 aop_cmd_db: memory@8fe20000 {
131 compatible = "qcom,cmd-db";
132 reg = <0x8fe20000 0x20000>;
133 no-map;
134 };
135
136 smem_mem: memory@8fe40000 {
137 no-map;
138 reg = <0x8fe40000 0xc0000>;
139 };
140
141 tz_mem: memory@8ff00000 {
142 no-map;
143 reg = <0x8ff00000 0x100000>;
144 };
145
Rob Herring9e62ec02021-08-23 11:51:26 -0500146 tz_apps_mem: memory@90000000 {
Vinod Koulec997702021-01-06 18:23:06 +0530147 no-map;
148 reg = <0x90000000 0x500000>;
149 };
150 };
151
Manivannan Sadhasivam8cf74d02021-01-06 18:23:12 +0530152 smem {
153 compatible = "qcom,smem";
154 memory-region = <&smem_mem>;
155 hwlocks = <&tcsr_mutex 3>;
156 };
157
Manivannan Sadhasivam21e6e1d2021-04-08 22:34:46 +0530158 smp2p-mpss {
159 compatible = "qcom,smp2p";
160 qcom,smem = <435>, <428>;
161 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
162 mboxes = <&apcs 14>;
163 qcom,local-pid = <0>;
164 qcom,remote-pid = <1>;
165
166 modem_smp2p_out: master-kernel {
167 qcom,entry-name = "master-kernel";
168 #qcom,smem-state-cells = <1>;
169 };
170
171 modem_smp2p_in: slave-kernel {
172 qcom,entry-name = "slave-kernel";
173 interrupt-controller;
174 #interrupt-cells = <2>;
175 };
176
177 ipa_smp2p_out: ipa-ap-to-modem {
178 qcom,entry-name = "ipa";
179 #qcom,smem-state-cells = <1>;
180 };
181
182 ipa_smp2p_in: ipa-modem-to-ap {
183 qcom,entry-name = "ipa";
184 interrupt-controller;
185 #interrupt-cells = <2>;
186 };
187 };
188
Manivannan Sadhasivam9d038b22020-11-26 14:01:38 +0530189 soc: soc {
190 #address-cells = <1>;
191 #size-cells = <1>;
192 ranges;
193 compatible = "simple-bus";
194
195 gcc: clock-controller@100000 {
196 compatible = "qcom,gcc-sdx55";
197 reg = <0x100000 0x1f0000>;
198 #clock-cells = <1>;
199 #reset-cells = <1>;
Manivannan Sadhasivamfea4b412021-01-18 10:40:00 +0530200 #power-domain-cells = <1>;
Manivannan Sadhasivam9d038b22020-11-26 14:01:38 +0530201 clock-names = "bi_tcxo", "sleep_clk";
202 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
203 };
204
205 blsp1_uart3: serial@831000 {
206 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
207 reg = <0x00831000 0x200>;
208 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_LOW>;
209 clocks = <&gcc 30>,
210 <&gcc 9>;
211 clock-names = "core", "iface";
212 status = "disabled";
213 };
214
Manivannan Sadhasivamfea4b412021-01-18 10:40:00 +0530215 usb_hsphy: phy@ff4000 {
216 compatible = "qcom,usb-snps-hs-7nm-phy";
217 reg = <0x00ff4000 0x114>;
218 status = "disabled";
219 #phy-cells = <0>;
220
221 clocks = <&rpmhcc RPMH_CXO_CLK>;
222 clock-names = "ref";
223
224 resets = <&gcc GCC_QUSB2PHY_BCR>;
225 };
226
227 usb_qmpphy: phy@ff6000 {
228 compatible = "qcom,sdx55-qmp-usb3-uni-phy";
229 reg = <0x00ff6000 0x1c0>;
230 status = "disabled";
Manivannan Sadhasivamfea4b412021-01-18 10:40:00 +0530231 #address-cells = <1>;
232 #size-cells = <1>;
233 ranges;
234
235 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
236 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
237 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
238 clock-names = "aux", "cfg_ahb", "ref";
239
240 resets = <&gcc GCC_USB3PHY_PHY_BCR>,
241 <&gcc GCC_USB3_PHY_BCR>;
242 reset-names = "phy", "common";
243
244 usb_ssphy: phy@ff6200 {
245 reg = <0x00ff6200 0x170>,
246 <0x00ff6400 0x200>,
247 <0x00ff6800 0x800>;
248 #phy-cells = <0>;
249 #clock-cells = <0>;
250 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
251 clock-names = "pipe0";
252 clock-output-names = "usb3_uni_phy_pipe_clk_src";
253 };
254 };
255
Manivannan Sadhasivamce5a28d12021-04-08 22:34:50 +0530256 mc_virt: interconnect@1100000 {
257 compatible = "qcom,sdx55-mc-virt";
258 reg = <0x01100000 0x400000>;
259 #interconnect-cells = <1>;
260 qcom,bcm-voters = <&apps_bcm_voter>;
261 };
262
263 mem_noc: interconnect@9680000 {
264 compatible = "qcom,sdx55-mem-noc";
265 reg = <0x09680000 0x40000>;
266 #interconnect-cells = <1>;
267 qcom,bcm-voters = <&apps_bcm_voter>;
268 };
269
270 system_noc: interconnect@162c000 {
271 compatible = "qcom,sdx55-system-noc";
272 reg = <0x0162c000 0x31200>;
273 #interconnect-cells = <1>;
274 qcom,bcm-voters = <&apps_bcm_voter>;
275 };
276
277 ipa_virt: interconnect@1e00000 {
278 compatible = "qcom,sdx55-ipa-virt";
279 reg = <0x01e00000 0x100000>;
280 #interconnect-cells = <1>;
281 qcom,bcm-voters = <&apps_bcm_voter>;
282 };
283
Manivannan Sadhasivam24709412021-01-06 18:23:13 +0530284 qpic_bam: dma-controller@1b04000 {
285 compatible = "qcom,bam-v1.7.0";
286 reg = <0x01b04000 0x1c000>;
287 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&rpmhcc RPMH_QPIC_CLK>;
289 clock-names = "bam_clk";
290 #dma-cells = <1>;
291 qcom,ee = <0>;
292 qcom,controlled-remotely;
293 status = "disabled";
294 };
295
Manivannan Sadhasivam9e1e00f2021-04-08 22:34:51 +0530296 qpic_nand: nand-controller@1b30000 {
Manivannan Sadhasivam4bd7bfb2021-01-06 18:23:14 +0530297 compatible = "qcom,sdx55-nand";
298 reg = <0x01b30000 0x10000>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 clocks = <&rpmhcc RPMH_QPIC_CLK>,
302 <&nand_clk_dummy>;
303 clock-names = "core", "aon";
304
305 dmas = <&qpic_bam 0>,
306 <&qpic_bam 1>,
307 <&qpic_bam 2>;
308 dma-names = "tx", "rx", "cmd";
309 status = "disabled";
310 };
311
Alex Elder06ad53e2021-04-09 10:52:51 -0500312 ipa: ipa@1e40000 {
313 compatible = "qcom,sdx55-ipa";
314
315 iommus = <&apps_smmu 0x5e0 0x0>,
316 <&apps_smmu 0x5e2 0x0>;
317 reg = <0x1e40000 0x7000>,
318 <0x1e50000 0x4b20>,
319 <0x1e04000 0x2c000>;
320 reg-names = "ipa-reg",
321 "ipa-shared",
322 "gsi";
323
324 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
325 <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
326 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
327 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
328 interrupt-names = "ipa",
329 "gsi",
330 "ipa-clock-query",
331 "ipa-setup-ready";
332
333 clocks = <&rpmhcc RPMH_IPA_CLK>;
334 clock-names = "core";
335
336 interconnects = <&system_noc MASTER_IPA &system_noc SLAVE_SNOC_MEM_NOC_GC>,
337 <&mem_noc MASTER_SNOC_GC_MEM_NOC &mc_virt SLAVE_EBI_CH0>,
338 <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>,
339 <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_IPA_CFG>;
340 interconnect-names = "memory-a",
341 "memory-b",
342 "imem",
343 "config";
344
345 qcom,smem-states = <&ipa_smp2p_out 0>,
346 <&ipa_smp2p_out 1>;
347 qcom,smem-state-names = "ipa-clock-enabled-valid",
348 "ipa-clock-enabled";
349
350 status = "disabled";
351 };
352
Manivannan Sadhasivam985eef12021-01-06 18:23:11 +0530353 tcsr_mutex: hwlock@1f40000 {
354 compatible = "qcom,tcsr-mutex";
355 reg = <0x01f40000 0x40000>;
356 #hwlock-cells = <1>;
357 };
358
Manivannan Sadhasivamf0365492021-01-06 18:23:08 +0530359 sdhc_1: sdhci@8804000 {
360 compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
361 reg = <0x08804000 0x1000>;
362 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
364 interrupt-names = "hc_irq", "pwr_irq";
365 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
366 <&gcc GCC_SDCC1_APPS_CLK>;
367 clock-names = "iface", "core";
368 status = "disabled";
369 };
370
Manivannan Sadhasivam67b47442021-04-08 22:34:57 +0530371 remoteproc_mpss: remoteproc@4080000 {
372 compatible = "qcom,sdx55-mpss-pas";
373 reg = <0x04080000 0x4040>;
374
375 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
376 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
377 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
378 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
379 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
380 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
381 interrupt-names = "wdog", "fatal", "ready", "handover",
382 "stop-ack", "shutdown-ack";
383
384 clocks = <&rpmhcc RPMH_CXO_CLK>;
385 clock-names = "xo";
386
387 power-domains = <&rpmhpd SDX55_CX>,
388 <&rpmhpd SDX55_MSS>;
389 power-domain-names = "cx", "mss";
390
391 qcom,smem-states = <&modem_smp2p_out 0>;
392 qcom,smem-state-names = "stop";
393
394 status = "disabled";
395
396 glink-edge {
397 interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
398 label = "mpss";
399 qcom,remote-pid = <1>;
400 mboxes = <&apcs 15>;
401 };
402 };
403
Manivannan Sadhasivamfea4b412021-01-18 10:40:00 +0530404 usb: usb@a6f8800 {
405 compatible = "qcom,sdx55-dwc3", "qcom,dwc3";
406 reg = <0x0a6f8800 0x400>;
407 status = "disabled";
408 #address-cells = <1>;
409 #size-cells = <1>;
410 ranges;
411
412 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
413 <&gcc GCC_USB30_MASTER_CLK>,
414 <&gcc GCC_USB30_MSTR_AXI_CLK>,
415 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
416 <&gcc GCC_USB30_SLEEP_CLK>;
417 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
418 "sleep";
419
420 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
421 <&gcc GCC_USB30_MASTER_CLK>;
422 assigned-clock-rates = <19200000>, <200000000>;
423
424 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
428 interrupt-names = "hs_phy_irq", "ss_phy_irq",
429 "dm_hs_phy_irq", "dp_hs_phy_irq";
430
431 power-domains = <&gcc USB30_GDSC>;
432
433 resets = <&gcc GCC_USB30_BCR>;
434
435 usb_dwc3: dwc3@a600000 {
436 compatible = "snps,dwc3";
437 reg = <0x0a600000 0xcd00>;
438 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
439 iommus = <&apps_smmu 0x1a0 0x0>;
440 snps,dis_u2_susphy_quirk;
441 snps,dis_enblslpm_quirk;
442 phys = <&usb_hsphy>, <&usb_ssphy>;
443 phy-names = "usb2-phy", "usb3-phy";
444 };
445 };
446
Manivannan Sadhasivam9d038b22020-11-26 14:01:38 +0530447 pdc: interrupt-controller@b210000 {
448 compatible = "qcom,sdx55-pdc", "qcom,pdc";
449 reg = <0x0b210000 0x30000>;
450 qcom,pdc-ranges = <0 179 52>;
451 #interrupt-cells = <3>;
452 interrupt-parent = <&intc>;
453 interrupt-controller;
454 };
455
Manivannan Sadhasivamc4aa86f2021-01-18 10:40:04 +0530456 restart@c264000 {
457 compatible = "qcom,pshold";
458 reg = <0x0c264000 0x1000>;
459 };
460
Vinod Koul3b6785e2021-01-06 18:23:17 +0530461 spmi_bus: qcom,spmi@c440000 {
462 compatible = "qcom,spmi-pmic-arb";
463 reg = <0x0c440000 0x0000d00>,
464 <0x0c600000 0x2000000>,
465 <0x0e600000 0x0100000>,
466 <0x0e700000 0x00a0000>,
467 <0x0c40a000 0x0000700>;
468 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
469 interrupt-names = "periph_irq";
470 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
471 qcom,ee = <0>;
472 qcom,channel = <0>;
473 #address-cells = <2>;
474 #size-cells = <0>;
475 interrupt-controller;
476 #interrupt-cells = <4>;
477 cell-index = <0>;
478 };
479
Vinod Kouldea0e9b2021-01-06 18:23:05 +0530480 tlmm: pinctrl@f100000 {
481 compatible = "qcom,sdx55-pinctrl";
482 reg = <0xf100000 0x300000>;
483 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
484 gpio-controller;
485 #gpio-cells = <2>;
486 interrupt-controller;
487 #interrupt-cells = <2>;
488 };
489
Manivannan Sadhasivam9b7069e2021-04-08 22:34:47 +0530490 imem@1468f000 {
491 compatible = "simple-mfd";
492 reg = <0x1468f000 0x1000>;
493
494 #address-cells = <1>;
495 #size-cells = <1>;
496
497 ranges = <0x0 0x1468f000 0x1000>;
498
499 pil-reloc@94c {
500 compatible = "qcom,pil-reloc-info";
501 reg = <0x94c 0x200>;
502 };
503 };
504
Bjorn Anderssona2bdfdf2021-01-06 18:23:10 +0530505 apps_smmu: iommu@15000000 {
506 compatible = "qcom,sdx55-smmu-500", "arm,mmu-500";
507 reg = <0x15000000 0x20000>;
508 #iommu-cells = <2>;
509 #global-interrupts = <1>;
510 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
527 };
528
Manivannan Sadhasivam9d038b22020-11-26 14:01:38 +0530529 intc: interrupt-controller@17800000 {
530 compatible = "qcom,msm-qgic2";
531 interrupt-controller;
532 interrupt-parent = <&intc>;
533 #interrupt-cells = <3>;
534 reg = <0x17800000 0x1000>,
535 <0x17802000 0x1000>;
536 };
537
Manivannan Sadhasivam37f0f242021-04-08 22:34:43 +0530538 a7pll: clock@17808000 {
539 compatible = "qcom,sdx55-a7pll";
540 reg = <0x17808000 0x1000>;
541 clocks = <&rpmhcc RPMH_CXO_CLK>;
542 clock-names = "bi_tcxo";
543 #clock-cells = <0>;
544 };
545
Manivannan Sadhasivam8e3d9a72021-04-08 22:34:44 +0530546 apcs: mailbox@17810000 {
547 compatible = "qcom,sdx55-apcs-gcc", "syscon";
548 reg = <0x17810000 0x2000>;
549 #mbox-cells = <1>;
550 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;
551 clock-names = "ref", "pll", "aux";
552 #clock-cells = <0>;
553 };
554
Manivannan Sadhasivamb1d20462021-01-18 10:40:03 +0530555 watchdog@17817000 {
556 compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt";
557 reg = <0x17817000 0x1000>;
558 clocks = <&sleep_clk>;
559 };
560
Manivannan Sadhasivam9d038b22020-11-26 14:01:38 +0530561 timer@17820000 {
562 #address-cells = <1>;
563 #size-cells = <1>;
564 ranges;
565 compatible = "arm,armv7-timer-mem";
566 reg = <0x17820000 0x1000>;
567 clock-frequency = <19200000>;
568
569 frame@17821000 {
570 frame-number = <0>;
571 interrupts = <GIC_SPI 7 0x4>,
572 <GIC_SPI 6 0x4>;
573 reg = <0x17821000 0x1000>,
574 <0x17822000 0x1000>;
575 };
576
577 frame@17823000 {
578 frame-number = <1>;
579 interrupts = <GIC_SPI 8 0x4>;
580 reg = <0x17823000 0x1000>;
581 status = "disabled";
582 };
583
584 frame@17824000 {
585 frame-number = <2>;
586 interrupts = <GIC_SPI 9 0x4>;
587 reg = <0x17824000 0x1000>;
588 status = "disabled";
589 };
590
591 frame@17825000 {
592 frame-number = <3>;
593 interrupts = <GIC_SPI 10 0x4>;
594 reg = <0x17825000 0x1000>;
595 status = "disabled";
596 };
597
598 frame@17826000 {
599 frame-number = <4>;
600 interrupts = <GIC_SPI 11 0x4>;
601 reg = <0x17826000 0x1000>;
602 status = "disabled";
603 };
604
605 frame@17827000 {
606 frame-number = <5>;
607 interrupts = <GIC_SPI 12 0x4>;
608 reg = <0x17827000 0x1000>;
609 status = "disabled";
610 };
611
612 frame@17828000 {
613 frame-number = <6>;
614 interrupts = <GIC_SPI 13 0x4>;
615 reg = <0x17828000 0x1000>;
616 status = "disabled";
617 };
618
619 frame@17829000 {
620 frame-number = <7>;
621 interrupts = <GIC_SPI 14 0x4>;
622 reg = <0x17829000 0x1000>;
623 status = "disabled";
624 };
625 };
626
627 apps_rsc: rsc@17840000 {
628 compatible = "qcom,rpmh-rsc";
629 reg = <0x17830000 0x10000>, <0x17840000 0x10000>;
630 reg-names = "drv-0", "drv-1";
631 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
633 qcom,tcs-offset = <0xd00>;
634 qcom,drv-id = <1>;
635 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 2>,
636 <WAKE_TCS 2>, <CONTROL_TCS 1>;
637
638 rpmhcc: clock-controller {
639 compatible = "qcom,sdx55-rpmh-clk";
640 #clock-cells = <1>;
641 clock-names = "xo";
642 clocks = <&xo_board>;
643 };
Vinod Koul3cef2d52021-01-06 18:23:20 +0530644
645 rpmhpd: power-controller {
646 compatible = "qcom,sdx55-rpmhpd";
647 #power-domain-cells = <1>;
648 operating-points-v2 = <&rpmhpd_opp_table>;
649
650 rpmhpd_opp_table: opp-table {
651 compatible = "operating-points-v2";
652
653 rpmhpd_opp_ret: opp1 {
654 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
655 };
656
657 rpmhpd_opp_min_svs: opp2 {
658 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
659 };
660
661 rpmhpd_opp_low_svs: opp3 {
662 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
663 };
664
665 rpmhpd_opp_svs: opp4 {
666 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
667 };
668
669 rpmhpd_opp_svs_l1: opp5 {
670 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
671 };
672
673 rpmhpd_opp_nom: opp6 {
674 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
675 };
676
677 rpmhpd_opp_nom_l1: opp7 {
678 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
679 };
680
681 rpmhpd_opp_nom_l2: opp8 {
682 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
683 };
684
685 rpmhpd_opp_turbo: opp9 {
686 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
687 };
688
689 rpmhpd_opp_turbo_l1: opp10 {
690 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
691 };
692 };
693 };
Manivannan Sadhasivamce5a28d12021-04-08 22:34:50 +0530694
695 apps_bcm_voter: bcm_voter {
696 compatible = "qcom,bcm-voter";
697 };
Manivannan Sadhasivam9d038b22020-11-26 14:01:38 +0530698 };
699 };
700
701 timer {
702 compatible = "arm,armv7-timer";
703 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
704 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
705 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
706 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
707 clock-frequency = <19200000>;
708 };
709};