| Mark Kettenis | a3b539f | 2021-09-21 20:34:14 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/pci/apple,pcie.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Apple PCIe host controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Mark Kettenis <kettenis@openbsd.org> |
| 11 | |
| 12 | description: | |
| 13 | The Apple PCIe host controller is a PCIe host controller with |
| 14 | multiple root ports present in Apple ARM SoC platforms, including |
| 15 | various iPhone and iPad devices and the "Apple Silicon" Macs. |
| 16 | The controller incorporates Synopsys DesigWare PCIe logic to |
| 17 | implements its root ports. But the ATU found on most DesignWare |
| 18 | PCIe host bridges is absent. |
| 19 | |
| 20 | All root ports share a single ECAM space, but separate GPIOs are |
| 21 | used to take the PCI devices on those ports out of reset. Therefore |
| 22 | the standard "reset-gpios" and "max-link-speed" properties appear on |
| 23 | the child nodes that represent the PCI bridges that correspond to |
| 24 | the individual root ports. |
| 25 | |
| 26 | MSIs are handled by the PCIe controller and translated into regular |
| 27 | interrupts. A range of 32 MSIs is provided. These 32 MSIs can be |
| 28 | distributed over the root ports as the OS sees fit by programming |
| 29 | the PCIe controller's port registers. |
| 30 | |
| 31 | allOf: |
| 32 | - $ref: /schemas/pci/pci-bus.yaml# |
| 33 | - $ref: /schemas/interrupt-controller/msi-controller.yaml# |
| 34 | |
| 35 | properties: |
| 36 | compatible: |
| 37 | items: |
| 38 | - const: apple,t8103-pcie |
| 39 | - const: apple,pcie |
| 40 | |
| 41 | reg: |
| 42 | minItems: 3 |
| 43 | maxItems: 5 |
| 44 | |
| 45 | reg-names: |
| 46 | minItems: 3 |
| 47 | items: |
| 48 | - const: config |
| 49 | - const: rc |
| 50 | - const: port0 |
| 51 | - const: port1 |
| 52 | - const: port2 |
| 53 | |
| 54 | ranges: |
| 55 | minItems: 2 |
| 56 | maxItems: 2 |
| 57 | |
| 58 | interrupts: |
| 59 | description: |
| 60 | Interrupt specifiers, one for each root port. |
| 61 | minItems: 1 |
| 62 | maxItems: 3 |
| 63 | |
| 64 | msi-parent: true |
| 65 | |
| 66 | msi-ranges: |
| 67 | maxItems: 1 |
| 68 | |
| 69 | iommu-map: true |
| 70 | iommu-map-mask: true |
| 71 | |
| 72 | required: |
| 73 | - compatible |
| 74 | - reg |
| 75 | - reg-names |
| 76 | - bus-range |
| 77 | - interrupts |
| 78 | - msi-controller |
| 79 | - msi-parent |
| 80 | - msi-ranges |
| 81 | |
| 82 | unevaluatedProperties: false |
| 83 | |
| 84 | examples: |
| 85 | - | |
| 86 | #include <dt-bindings/interrupt-controller/apple-aic.h> |
| 87 | |
| 88 | soc { |
| 89 | #address-cells = <2>; |
| 90 | #size-cells = <2>; |
| 91 | |
| 92 | pcie0: pcie@690000000 { |
| 93 | compatible = "apple,t8103-pcie", "apple,pcie"; |
| 94 | device_type = "pci"; |
| 95 | |
| 96 | reg = <0x6 0x90000000 0x0 0x1000000>, |
| 97 | <0x6 0x80000000 0x0 0x100000>, |
| 98 | <0x6 0x81000000 0x0 0x4000>, |
| 99 | <0x6 0x82000000 0x0 0x4000>, |
| 100 | <0x6 0x83000000 0x0 0x4000>; |
| 101 | reg-names = "config", "rc", "port0", "port1", "port2"; |
| 102 | |
| 103 | interrupt-parent = <&aic>; |
| 104 | interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, |
| 105 | <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, |
| 106 | <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; |
| 107 | |
| 108 | msi-controller; |
| 109 | msi-parent = <&pcie0>; |
| 110 | msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; |
| 111 | |
| 112 | iommu-map = <0x100 &dart0 1 1>, |
| 113 | <0x200 &dart1 1 1>, |
| 114 | <0x300 &dart2 1 1>; |
| 115 | iommu-map-mask = <0xff00>; |
| 116 | |
| 117 | bus-range = <0 3>; |
| 118 | #address-cells = <3>; |
| 119 | #size-cells = <2>; |
| 120 | ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, |
| 121 | <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; |
| 122 | |
| 123 | power-domains = <&ps_apcie>, <&ps_apcie_gp>, <&ps_pcie_ref>; |
| 124 | pinctrl-0 = <&pcie_pins>; |
| 125 | pinctrl-names = "default"; |
| 126 | |
| 127 | pci@0,0 { |
| 128 | device_type = "pci"; |
| 129 | reg = <0x0 0x0 0x0 0x0 0x0>; |
| 130 | reset-gpios = <&pinctrl_ap 152 0>; |
| 131 | max-link-speed = <2>; |
| 132 | |
| 133 | #address-cells = <3>; |
| 134 | #size-cells = <2>; |
| 135 | ranges; |
| 136 | }; |
| 137 | |
| 138 | pci@1,0 { |
| 139 | device_type = "pci"; |
| 140 | reg = <0x800 0x0 0x0 0x0 0x0>; |
| 141 | reset-gpios = <&pinctrl_ap 153 0>; |
| 142 | max-link-speed = <2>; |
| 143 | |
| 144 | #address-cells = <3>; |
| 145 | #size-cells = <2>; |
| 146 | ranges; |
| 147 | }; |
| 148 | |
| 149 | pci@2,0 { |
| 150 | device_type = "pci"; |
| 151 | reg = <0x1000 0x0 0x0 0x0 0x0>; |
| 152 | reset-gpios = <&pinctrl_ap 33 0>; |
| 153 | max-link-speed = <1>; |
| 154 | |
| 155 | #address-cells = <3>; |
| 156 | #size-cells = <2>; |
| 157 | ranges; |
| 158 | }; |
| 159 | }; |
| 160 | }; |