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Jiaxin Yu18b13ff2020-11-03 15:59:37 +08001// SPDX-License-Identifier: GPL-2.0
2//
3// mt8192-mt6359-rt1015-rt5682.c --
4// MT8192-MT6359-RT1015-RT6358 ALSA SoC machine driver
5//
6// Copyright (c) 2020 MediaTek Inc.
7// Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
8//
9
10#include <linux/input.h>
11#include <linux/module.h>
Tzung-Bi Shih2b53d2e2020-12-01 21:26:10 +080012#include <linux/of_device.h>
Jiaxin Yu18b13ff2020-11-03 15:59:37 +080013#include <linux/pm_runtime.h>
14#include <sound/jack.h>
15#include <sound/pcm_params.h>
16#include <sound/rt5682.h>
17#include <sound/soc.h>
18
19#include "../../codecs/mt6359.h"
20#include "../../codecs/rt1015.h"
21#include "../../codecs/rt5682.h"
22#include "../common/mtk-afe-platform-driver.h"
23#include "mt8192-afe-common.h"
24#include "mt8192-afe-clk.h"
25#include "mt8192-afe-gpio.h"
26
27#define RT1015_CODEC_DAI "rt1015-aif"
28#define RT1015_DEV0_NAME "rt1015.1-0028"
29#define RT1015_DEV1_NAME "rt1015.1-0029"
30
31#define RT5682_CODEC_DAI "rt5682-aif1"
32#define RT5682_DEV0_NAME "rt5682.1-001a"
33
Tzung-Bi Shih4e375282021-01-20 16:08:46 +080034struct mt8192_mt6359_priv {
35 struct snd_soc_jack headset_jack;
Tzung-Bi Shih0d80c482021-01-20 16:08:50 +080036 struct snd_soc_jack hdmi_jack;
Tzung-Bi Shih4e375282021-01-20 16:08:46 +080037};
Jiaxin Yu18b13ff2020-11-03 15:59:37 +080038
Jiaxin Yu18b13ff2020-11-03 15:59:37 +080039static int mt8192_rt1015_i2s_hw_params(struct snd_pcm_substream *substream,
40 struct snd_pcm_hw_params *params)
41{
Tzung-Bi Shih8e59cf92021-02-03 11:21:59 +080042 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
Jiaxin Yu18b13ff2020-11-03 15:59:37 +080043 struct snd_soc_card *card = rtd->card;
44 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
45 struct snd_soc_dai *codec_dai;
46 unsigned int rate = params_rate(params);
47 unsigned int mclk_fs_ratio = 128;
48 unsigned int mclk_fs = rate * mclk_fs_ratio;
49 int ret, i;
50
51 for_each_rtd_codec_dais(rtd, i, codec_dai) {
Jiaxin Yu18b13ff2020-11-03 15:59:37 +080052 ret = snd_soc_dai_set_pll(codec_dai, 0,
53 RT1015_PLL_S_BCLK,
54 params_rate(params) * 64,
55 params_rate(params) * 256);
56 if (ret) {
57 dev_err(card->dev, "failed to set pll\n");
58 return ret;
59 }
60
61 ret = snd_soc_dai_set_sysclk(codec_dai,
62 RT1015_SCLK_S_PLL,
63 params_rate(params) * 256,
64 SND_SOC_CLOCK_IN);
65 if (ret) {
66 dev_err(card->dev, "failed to set sysclk\n");
67 return ret;
68 }
69 }
70
71 return snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_fs, SND_SOC_CLOCK_OUT);
72}
73
74static int mt8192_rt5682_i2s_hw_params(struct snd_pcm_substream *substream,
75 struct snd_pcm_hw_params *params)
76{
Tzung-Bi Shih8e59cf92021-02-03 11:21:59 +080077 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
Jiaxin Yu18b13ff2020-11-03 15:59:37 +080078 struct snd_soc_card *card = rtd->card;
79 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
80 struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
81 unsigned int rate = params_rate(params);
82 unsigned int mclk_fs_ratio = 128;
83 unsigned int mclk_fs = rate * mclk_fs_ratio;
84 int bitwidth;
85 int ret;
86
87 bitwidth = snd_pcm_format_width(params_format(params));
88 if (bitwidth < 0) {
89 dev_err(card->dev, "invalid bit width: %d\n", bitwidth);
90 return bitwidth;
91 }
92
93 ret = snd_soc_dai_set_tdm_slot(codec_dai, 0x00, 0x0, 0x2, bitwidth);
94 if (ret) {
95 dev_err(card->dev, "failed to set tdm slot\n");
96 return ret;
97 }
98
99 ret = snd_soc_dai_set_pll(codec_dai, RT5682_PLL1,
100 RT5682_PLL1_S_BCLK1,
101 params_rate(params) * 64,
102 params_rate(params) * 512);
103 if (ret) {
104 dev_err(card->dev, "failed to set pll\n");
105 return ret;
106 }
107
108 ret = snd_soc_dai_set_sysclk(codec_dai,
109 RT5682_SCLK_S_PLL1,
110 params_rate(params) * 512,
111 SND_SOC_CLOCK_IN);
112 if (ret) {
113 dev_err(card->dev, "failed to set sysclk\n");
114 return ret;
115 }
116
117 return snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_fs, SND_SOC_CLOCK_OUT);
118}
119
120static const struct snd_soc_ops mt8192_rt1015_i2s_ops = {
121 .hw_params = mt8192_rt1015_i2s_hw_params,
122};
123
124static const struct snd_soc_ops mt8192_rt5682_i2s_ops = {
125 .hw_params = mt8192_rt5682_i2s_hw_params,
126};
127
128static int mt8192_mt6359_mtkaif_calibration(struct snd_soc_pcm_runtime *rtd)
129{
130 struct snd_soc_component *cmpnt_afe =
131 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
132 struct snd_soc_component *cmpnt_codec =
133 asoc_rtd_to_codec(rtd, 0)->component;
134 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
135 struct mt8192_afe_private *afe_priv = afe->platform_priv;
136 int phase;
137 unsigned int monitor;
138 int test_done_1, test_done_2, test_done_3;
139 int cycle_1, cycle_2, cycle_3;
140 int prev_cycle_1, prev_cycle_2, prev_cycle_3;
141 int chosen_phase_1, chosen_phase_2, chosen_phase_3;
142 int counter;
143 int mtkaif_calib_ok;
144
145 dev_info(afe->dev, "%s(), start\n", __func__);
146
147 pm_runtime_get_sync(afe->dev);
148 mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA, 1);
149 mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA, 0);
150 mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA_CH34, 1);
151 mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA_CH34, 0);
152
153 mt6359_mtkaif_calibration_enable(cmpnt_codec);
154
155 /* set clock protocol 2 */
156 regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, 0xff, 0x38);
157 regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, 0xff, 0x39);
158
159 /* set test type to synchronizer pulse */
160 regmap_update_bits(afe_priv->topckgen,
161 CKSYS_AUD_TOP_CFG, 0xffff, 0x4);
162
163 mtkaif_calib_ok = true;
164 afe_priv->mtkaif_calibration_num_phase = 42; /* mt6359: 0 ~ 42 */
165 afe_priv->mtkaif_chosen_phase[0] = -1;
166 afe_priv->mtkaif_chosen_phase[1] = -1;
167 afe_priv->mtkaif_chosen_phase[2] = -1;
168
169 for (phase = 0;
170 phase <= afe_priv->mtkaif_calibration_num_phase &&
171 mtkaif_calib_ok;
172 phase++) {
173 mt6359_set_mtkaif_calibration_phase(cmpnt_codec,
174 phase, phase, phase);
175
176 regmap_update_bits(afe_priv->topckgen,
177 CKSYS_AUD_TOP_CFG, 0x1, 0x1);
178
179 test_done_1 = 0;
180 test_done_2 = 0;
181 test_done_3 = 0;
182 cycle_1 = -1;
183 cycle_2 = -1;
184 cycle_3 = -1;
185 counter = 0;
186 while (test_done_1 == 0 ||
187 test_done_2 == 0 ||
188 test_done_3 == 0) {
189 regmap_read(afe_priv->topckgen,
190 CKSYS_AUD_TOP_MON, &monitor);
191
192 test_done_1 = (monitor >> 28) & 0x1;
193 test_done_2 = (monitor >> 29) & 0x1;
194 test_done_3 = (monitor >> 30) & 0x1;
195 if (test_done_1 == 1)
196 cycle_1 = monitor & 0xf;
197
198 if (test_done_2 == 1)
199 cycle_2 = (monitor >> 4) & 0xf;
200
201 if (test_done_3 == 1)
202 cycle_3 = (monitor >> 8) & 0xf;
203
204 /* handle if never test done */
205 if (++counter > 10000) {
206 dev_err(afe->dev, "%s(), test fail, cycle_1 %d, cycle_2 %d, cycle_3 %d, monitor 0x%x\n",
207 __func__,
208 cycle_1, cycle_2, cycle_3, monitor);
209 mtkaif_calib_ok = false;
210 break;
211 }
212 }
213
214 if (phase == 0) {
215 prev_cycle_1 = cycle_1;
216 prev_cycle_2 = cycle_2;
217 prev_cycle_3 = cycle_3;
218 }
219
220 if (cycle_1 != prev_cycle_1 &&
221 afe_priv->mtkaif_chosen_phase[0] < 0) {
222 afe_priv->mtkaif_chosen_phase[0] = phase - 1;
223 afe_priv->mtkaif_phase_cycle[0] = prev_cycle_1;
224 }
225
226 if (cycle_2 != prev_cycle_2 &&
227 afe_priv->mtkaif_chosen_phase[1] < 0) {
228 afe_priv->mtkaif_chosen_phase[1] = phase - 1;
229 afe_priv->mtkaif_phase_cycle[1] = prev_cycle_2;
230 }
231
232 if (cycle_3 != prev_cycle_3 &&
233 afe_priv->mtkaif_chosen_phase[2] < 0) {
234 afe_priv->mtkaif_chosen_phase[2] = phase - 1;
235 afe_priv->mtkaif_phase_cycle[2] = prev_cycle_3;
236 }
237
238 regmap_update_bits(afe_priv->topckgen,
239 CKSYS_AUD_TOP_CFG, 0x1, 0x0);
240
241 if (afe_priv->mtkaif_chosen_phase[0] >= 0 &&
242 afe_priv->mtkaif_chosen_phase[1] >= 0 &&
243 afe_priv->mtkaif_chosen_phase[2] >= 0)
244 break;
245 }
246
247 if (afe_priv->mtkaif_chosen_phase[0] < 0)
248 chosen_phase_1 = 0;
249 else
250 chosen_phase_1 = afe_priv->mtkaif_chosen_phase[0];
251
252 if (afe_priv->mtkaif_chosen_phase[1] < 0)
253 chosen_phase_2 = 0;
254 else
255 chosen_phase_2 = afe_priv->mtkaif_chosen_phase[1];
256
257 if (afe_priv->mtkaif_chosen_phase[2] < 0)
258 chosen_phase_3 = 0;
259 else
260 chosen_phase_3 = afe_priv->mtkaif_chosen_phase[2];
261
262 mt6359_set_mtkaif_calibration_phase(cmpnt_codec,
263 chosen_phase_1,
264 chosen_phase_2,
265 chosen_phase_3);
266
267 /* disable rx fifo */
268 regmap_update_bits(afe->regmap, AFE_AUD_PAD_TOP, 0xff, 0x38);
269
270 mt6359_mtkaif_calibration_disable(cmpnt_codec);
271
272 mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA, 1);
273 mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA, 0);
274 mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA_CH34, 1);
275 mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA_CH34, 0);
276 pm_runtime_put(afe->dev);
277
278 dev_info(afe->dev, "%s(), mtkaif_chosen_phase[0/1/2]:%d/%d/%d\n",
279 __func__,
280 afe_priv->mtkaif_chosen_phase[0],
281 afe_priv->mtkaif_chosen_phase[1],
282 afe_priv->mtkaif_chosen_phase[2]);
283
284 return 0;
285}
286
287static int mt8192_mt6359_init(struct snd_soc_pcm_runtime *rtd)
288{
289 struct snd_soc_component *cmpnt_afe =
290 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
291 struct snd_soc_component *cmpnt_codec =
292 asoc_rtd_to_codec(rtd, 0)->component;
293 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt_afe);
294 struct mt8192_afe_private *afe_priv = afe->platform_priv;
295
296 /* set mtkaif protocol */
297 mt6359_set_mtkaif_protocol(cmpnt_codec,
298 MT6359_MTKAIF_PROTOCOL_2_CLK_P2);
299 afe_priv->mtkaif_protocol = MTKAIF_PROTOCOL_2_CLK_P2;
300
301 /* mtkaif calibration */
302 mt8192_mt6359_mtkaif_calibration(rtd);
303
304 return 0;
305}
306
307static int mt8192_rt5682_init(struct snd_soc_pcm_runtime *rtd)
308{
309 struct snd_soc_component *cmpnt_codec =
310 asoc_rtd_to_codec(rtd, 0)->component;
Tzung-Bi Shih4e375282021-01-20 16:08:46 +0800311 struct mt8192_mt6359_priv *priv = snd_soc_card_get_drvdata(rtd->card);
312 struct snd_soc_jack *jack = &priv->headset_jack;
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800313 int ret;
314
315 ret = snd_soc_card_jack_new(rtd->card, "Headset Jack",
316 SND_JACK_HEADSET | SND_JACK_BTN_0 |
317 SND_JACK_BTN_1 | SND_JACK_BTN_2 |
318 SND_JACK_BTN_3,
319 jack, NULL, 0);
320 if (ret) {
321 dev_err(rtd->dev, "Headset Jack creation failed: %d\n", ret);
322 return ret;
323 }
324
325 snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
326 snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOICECOMMAND);
327 snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEUP);
328 snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOLUMEDOWN);
329
Tzung-Bi Shih12295ef2021-01-20 16:08:47 +0800330 return snd_soc_component_set_jack(cmpnt_codec, jack, NULL);
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800331};
332
Tzung-Bi Shih0d80c482021-01-20 16:08:50 +0800333static int mt8192_mt6359_hdmi_init(struct snd_soc_pcm_runtime *rtd)
334{
335 struct snd_soc_component *cmpnt_codec =
336 asoc_rtd_to_codec(rtd, 0)->component;
337 struct mt8192_mt6359_priv *priv = snd_soc_card_get_drvdata(rtd->card);
338 int ret;
339
340 ret = snd_soc_card_jack_new(rtd->card, "HDMI Jack", SND_JACK_LINEOUT,
341 &priv->hdmi_jack, NULL, 0);
342 if (ret) {
343 dev_err(rtd->dev, "HDMI Jack creation failed: %d\n", ret);
344 return ret;
345 }
346
347 return snd_soc_component_set_jack(cmpnt_codec, &priv->hdmi_jack, NULL);
348}
349
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800350static int mt8192_i2s_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
351 struct snd_pcm_hw_params *params)
352{
353 /* fix BE i2s format to 32bit, clean param mask first */
354 snd_mask_reset_range(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
355 0, SNDRV_PCM_FORMAT_LAST);
356
357 params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
358
359 return 0;
360}
361
362static int
Tzung-Bi Shih4cceb422021-02-03 11:22:01 +0800363mt8192_mt6359_cap1_startup(struct snd_pcm_substream *substream)
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800364{
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800365 static const unsigned int channels[] = {
366 1, 2, 4
367 };
368 static const struct snd_pcm_hw_constraint_list constraints_channels = {
369 .count = ARRAY_SIZE(channels),
370 .list = channels,
371 .mask = 0,
372 };
373 static const unsigned int rates[] = {
374 8000, 16000, 32000, 48000, 96000, 192000
375 };
376 static const struct snd_pcm_hw_constraint_list constraints_rates = {
377 .count = ARRAY_SIZE(rates),
378 .list = rates,
379 .mask = 0,
380 };
381
Tzung-Bi Shih4cceb422021-02-03 11:22:01 +0800382 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800383 struct snd_pcm_runtime *runtime = substream->runtime;
Tzung-Bi Shih4cceb422021-02-03 11:22:01 +0800384 int ret;
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800385
386 ret = snd_pcm_hw_constraint_list(runtime, 0,
387 SNDRV_PCM_HW_PARAM_CHANNELS,
388 &constraints_channels);
389 if (ret < 0) {
Tzung-Bi Shih4cceb422021-02-03 11:22:01 +0800390 dev_err(rtd->dev, "hw_constraint_list channels failed\n");
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800391 return ret;
392 }
393
394 ret = snd_pcm_hw_constraint_list(runtime, 0,
395 SNDRV_PCM_HW_PARAM_RATE,
396 &constraints_rates);
397 if (ret < 0) {
Tzung-Bi Shih4cceb422021-02-03 11:22:01 +0800398 dev_err(rtd->dev, "hw_constraint_list rate failed\n");
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800399 return ret;
400 }
401
402 return 0;
403}
404
Tzung-Bi Shih4cceb422021-02-03 11:22:01 +0800405static const struct snd_soc_ops mt8192_mt6359_capture1_ops = {
406 .startup = mt8192_mt6359_cap1_startup,
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800407};
408
409/* FE */
410SND_SOC_DAILINK_DEFS(playback1,
411 DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
412 DAILINK_COMP_ARRAY(COMP_DUMMY()),
413 DAILINK_COMP_ARRAY(COMP_EMPTY()));
414
415SND_SOC_DAILINK_DEFS(playback12,
416 DAILINK_COMP_ARRAY(COMP_CPU("DL12")),
417 DAILINK_COMP_ARRAY(COMP_DUMMY()),
418 DAILINK_COMP_ARRAY(COMP_EMPTY()));
419
420SND_SOC_DAILINK_DEFS(playback2,
421 DAILINK_COMP_ARRAY(COMP_CPU("DL2")),
422 DAILINK_COMP_ARRAY(COMP_DUMMY()),
423 DAILINK_COMP_ARRAY(COMP_EMPTY()));
424
425SND_SOC_DAILINK_DEFS(playback3,
426 DAILINK_COMP_ARRAY(COMP_CPU("DL3")),
427 DAILINK_COMP_ARRAY(COMP_DUMMY()),
428 DAILINK_COMP_ARRAY(COMP_EMPTY()));
429
430SND_SOC_DAILINK_DEFS(playback4,
431 DAILINK_COMP_ARRAY(COMP_CPU("DL4")),
432 DAILINK_COMP_ARRAY(COMP_DUMMY()),
433 DAILINK_COMP_ARRAY(COMP_EMPTY()));
434
435SND_SOC_DAILINK_DEFS(playback5,
436 DAILINK_COMP_ARRAY(COMP_CPU("DL5")),
437 DAILINK_COMP_ARRAY(COMP_DUMMY()),
438 DAILINK_COMP_ARRAY(COMP_EMPTY()));
439
440SND_SOC_DAILINK_DEFS(playback6,
441 DAILINK_COMP_ARRAY(COMP_CPU("DL6")),
442 DAILINK_COMP_ARRAY(COMP_DUMMY()),
443 DAILINK_COMP_ARRAY(COMP_EMPTY()));
444
445SND_SOC_DAILINK_DEFS(playback7,
446 DAILINK_COMP_ARRAY(COMP_CPU("DL7")),
447 DAILINK_COMP_ARRAY(COMP_DUMMY()),
448 DAILINK_COMP_ARRAY(COMP_EMPTY()));
449
450SND_SOC_DAILINK_DEFS(playback8,
451 DAILINK_COMP_ARRAY(COMP_CPU("DL8")),
452 DAILINK_COMP_ARRAY(COMP_DUMMY()),
453 DAILINK_COMP_ARRAY(COMP_EMPTY()));
454
455SND_SOC_DAILINK_DEFS(playback9,
456 DAILINK_COMP_ARRAY(COMP_CPU("DL9")),
457 DAILINK_COMP_ARRAY(COMP_DUMMY()),
458 DAILINK_COMP_ARRAY(COMP_EMPTY()));
459
460SND_SOC_DAILINK_DEFS(capture1,
461 DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
462 DAILINK_COMP_ARRAY(COMP_DUMMY()),
463 DAILINK_COMP_ARRAY(COMP_EMPTY()));
464
465SND_SOC_DAILINK_DEFS(capture2,
466 DAILINK_COMP_ARRAY(COMP_CPU("UL2")),
467 DAILINK_COMP_ARRAY(COMP_DUMMY()),
468 DAILINK_COMP_ARRAY(COMP_EMPTY()));
469
470SND_SOC_DAILINK_DEFS(capture3,
471 DAILINK_COMP_ARRAY(COMP_CPU("UL3")),
472 DAILINK_COMP_ARRAY(COMP_DUMMY()),
473 DAILINK_COMP_ARRAY(COMP_EMPTY()));
474
475SND_SOC_DAILINK_DEFS(capture4,
476 DAILINK_COMP_ARRAY(COMP_CPU("UL4")),
477 DAILINK_COMP_ARRAY(COMP_DUMMY()),
478 DAILINK_COMP_ARRAY(COMP_EMPTY()));
479
480SND_SOC_DAILINK_DEFS(capture5,
481 DAILINK_COMP_ARRAY(COMP_CPU("UL5")),
482 DAILINK_COMP_ARRAY(COMP_DUMMY()),
483 DAILINK_COMP_ARRAY(COMP_EMPTY()));
484
485SND_SOC_DAILINK_DEFS(capture6,
486 DAILINK_COMP_ARRAY(COMP_CPU("UL6")),
487 DAILINK_COMP_ARRAY(COMP_DUMMY()),
488 DAILINK_COMP_ARRAY(COMP_EMPTY()));
489
490SND_SOC_DAILINK_DEFS(capture7,
491 DAILINK_COMP_ARRAY(COMP_CPU("UL7")),
492 DAILINK_COMP_ARRAY(COMP_DUMMY()),
493 DAILINK_COMP_ARRAY(COMP_EMPTY()));
494
495SND_SOC_DAILINK_DEFS(capture8,
496 DAILINK_COMP_ARRAY(COMP_CPU("UL8")),
497 DAILINK_COMP_ARRAY(COMP_DUMMY()),
498 DAILINK_COMP_ARRAY(COMP_EMPTY()));
499
500SND_SOC_DAILINK_DEFS(capture_mono1,
501 DAILINK_COMP_ARRAY(COMP_CPU("UL_MONO_1")),
502 DAILINK_COMP_ARRAY(COMP_DUMMY()),
503 DAILINK_COMP_ARRAY(COMP_EMPTY()));
504
505SND_SOC_DAILINK_DEFS(capture_mono2,
506 DAILINK_COMP_ARRAY(COMP_CPU("UL_MONO_2")),
507 DAILINK_COMP_ARRAY(COMP_DUMMY()),
508 DAILINK_COMP_ARRAY(COMP_EMPTY()));
509
510SND_SOC_DAILINK_DEFS(capture_mono3,
511 DAILINK_COMP_ARRAY(COMP_CPU("UL_MONO_3")),
512 DAILINK_COMP_ARRAY(COMP_DUMMY()),
513 DAILINK_COMP_ARRAY(COMP_EMPTY()));
514
515SND_SOC_DAILINK_DEFS(playback_hdmi,
516 DAILINK_COMP_ARRAY(COMP_CPU("HDMI")),
517 DAILINK_COMP_ARRAY(COMP_DUMMY()),
518 DAILINK_COMP_ARRAY(COMP_EMPTY()));
519
520/* BE */
521SND_SOC_DAILINK_DEFS(primary_codec,
522 DAILINK_COMP_ARRAY(COMP_CPU("ADDA")),
523 DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound",
Jiaxin Yu2aff94e2020-11-11 10:45:22 +0800524 "mt6359-snd-codec-aif1"),
525 COMP_CODEC("dmic-codec",
526 "dmic-hifi")),
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800527 DAILINK_COMP_ARRAY(COMP_EMPTY()));
528
529SND_SOC_DAILINK_DEFS(primary_codec_ch34,
530 DAILINK_COMP_ARRAY(COMP_CPU("ADDA_CH34")),
531 DAILINK_COMP_ARRAY(COMP_CODEC("mt6359-sound",
532 "mt6359-snd-codec-aif2")),
533 DAILINK_COMP_ARRAY(COMP_EMPTY()));
534
535SND_SOC_DAILINK_DEFS(ap_dmic,
536 DAILINK_COMP_ARRAY(COMP_CPU("AP_DMIC")),
537 DAILINK_COMP_ARRAY(COMP_DUMMY()),
538 DAILINK_COMP_ARRAY(COMP_EMPTY()));
539
540SND_SOC_DAILINK_DEFS(ap_dmic_ch34,
541 DAILINK_COMP_ARRAY(COMP_CPU("AP_DMIC_CH34")),
542 DAILINK_COMP_ARRAY(COMP_DUMMY()),
543 DAILINK_COMP_ARRAY(COMP_EMPTY()));
544
545SND_SOC_DAILINK_DEFS(i2s0,
546 DAILINK_COMP_ARRAY(COMP_CPU("I2S0")),
547 DAILINK_COMP_ARRAY(COMP_DUMMY()),
548 DAILINK_COMP_ARRAY(COMP_EMPTY()));
549
550SND_SOC_DAILINK_DEFS(i2s1,
551 DAILINK_COMP_ARRAY(COMP_CPU("I2S1")),
552 DAILINK_COMP_ARRAY(COMP_DUMMY()),
553 DAILINK_COMP_ARRAY(COMP_EMPTY()));
554
555SND_SOC_DAILINK_DEFS(i2s2,
556 DAILINK_COMP_ARRAY(COMP_CPU("I2S2")),
557 DAILINK_COMP_ARRAY(COMP_DUMMY()),
558 DAILINK_COMP_ARRAY(COMP_EMPTY()));
559
Tzung-Bi Shih2b53d2e2020-12-01 21:26:10 +0800560SND_SOC_DAILINK_DEFS(i2s3_rt1015,
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800561 DAILINK_COMP_ARRAY(COMP_CPU("I2S3")),
562 DAILINK_COMP_ARRAY(COMP_CODEC(RT1015_DEV0_NAME,
563 RT1015_CODEC_DAI),
564 COMP_CODEC(RT1015_DEV1_NAME,
565 RT1015_CODEC_DAI)),
566 DAILINK_COMP_ARRAY(COMP_EMPTY()));
567
Tzung-Bi Shihcfd8bb22020-12-01 21:26:14 +0800568SND_SOC_DAILINK_DEFS(i2s3_rt1015p,
569 DAILINK_COMP_ARRAY(COMP_CPU("I2S3")),
570 DAILINK_COMP_ARRAY(COMP_CODEC("rt1015p", "HiFi")),
571 DAILINK_COMP_ARRAY(COMP_EMPTY()));
572
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800573SND_SOC_DAILINK_DEFS(i2s5,
574 DAILINK_COMP_ARRAY(COMP_CPU("I2S5")),
575 DAILINK_COMP_ARRAY(COMP_DUMMY()),
576 DAILINK_COMP_ARRAY(COMP_EMPTY()));
577
578SND_SOC_DAILINK_DEFS(i2s6,
579 DAILINK_COMP_ARRAY(COMP_CPU("I2S6")),
580 DAILINK_COMP_ARRAY(COMP_DUMMY()),
581 DAILINK_COMP_ARRAY(COMP_EMPTY()));
582
583SND_SOC_DAILINK_DEFS(i2s7,
584 DAILINK_COMP_ARRAY(COMP_CPU("I2S7")),
585 DAILINK_COMP_ARRAY(COMP_DUMMY()),
586 DAILINK_COMP_ARRAY(COMP_EMPTY()));
587
588SND_SOC_DAILINK_DEFS(i2s8,
589 DAILINK_COMP_ARRAY(COMP_CPU("I2S8")),
590 DAILINK_COMP_ARRAY(COMP_CODEC(RT5682_DEV0_NAME,
591 RT5682_CODEC_DAI)),
592 DAILINK_COMP_ARRAY(COMP_EMPTY()));
593
594SND_SOC_DAILINK_DEFS(i2s9,
595 DAILINK_COMP_ARRAY(COMP_CPU("I2S9")),
596 DAILINK_COMP_ARRAY(COMP_CODEC(RT5682_DEV0_NAME,
597 RT5682_CODEC_DAI)),
598 DAILINK_COMP_ARRAY(COMP_EMPTY()));
599
600SND_SOC_DAILINK_DEFS(connsys_i2s,
601 DAILINK_COMP_ARRAY(COMP_CPU("CONNSYS_I2S")),
602 DAILINK_COMP_ARRAY(COMP_DUMMY()),
603 DAILINK_COMP_ARRAY(COMP_EMPTY()));
604
605SND_SOC_DAILINK_DEFS(pcm1,
606 DAILINK_COMP_ARRAY(COMP_CPU("PCM 1")),
607 DAILINK_COMP_ARRAY(COMP_DUMMY()),
608 DAILINK_COMP_ARRAY(COMP_EMPTY()));
609
610SND_SOC_DAILINK_DEFS(pcm2,
611 DAILINK_COMP_ARRAY(COMP_CPU("PCM 2")),
612 DAILINK_COMP_ARRAY(COMP_DUMMY()),
613 DAILINK_COMP_ARRAY(COMP_EMPTY()));
614
615SND_SOC_DAILINK_DEFS(tdm,
616 DAILINK_COMP_ARRAY(COMP_CPU("TDM")),
Tzung-Bi Shih0d80c482021-01-20 16:08:50 +0800617 DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "i2s-hifi")),
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800618 DAILINK_COMP_ARRAY(COMP_EMPTY()));
619
Tzung-Bi Shiha5f80372020-12-01 21:26:09 +0800620static struct snd_soc_dai_link mt8192_mt6359_dai_links[] = {
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800621 /* Front End DAI links */
622 {
623 .name = "Playback_1",
624 .stream_name = "Playback_1",
625 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
626 SND_SOC_DPCM_TRIGGER_PRE},
627 .dynamic = 1,
628 .dpcm_playback = 1,
629 SND_SOC_DAILINK_REG(playback1),
630 },
631 {
632 .name = "Playback_12",
633 .stream_name = "Playback_12",
634 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
635 SND_SOC_DPCM_TRIGGER_PRE},
636 .dynamic = 1,
637 .dpcm_playback = 1,
638 SND_SOC_DAILINK_REG(playback12),
639 },
640 {
641 .name = "Playback_2",
642 .stream_name = "Playback_2",
643 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
644 SND_SOC_DPCM_TRIGGER_PRE},
645 .dynamic = 1,
646 .dpcm_playback = 1,
647 SND_SOC_DAILINK_REG(playback2),
648 },
649 {
650 .name = "Playback_3",
651 .stream_name = "Playback_3",
652 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
653 SND_SOC_DPCM_TRIGGER_PRE},
654 .dynamic = 1,
655 .dpcm_playback = 1,
656 SND_SOC_DAILINK_REG(playback3),
657 },
658 {
659 .name = "Playback_4",
660 .stream_name = "Playback_4",
661 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
662 SND_SOC_DPCM_TRIGGER_PRE},
663 .dynamic = 1,
664 .dpcm_playback = 1,
665 SND_SOC_DAILINK_REG(playback4),
666 },
667 {
668 .name = "Playback_5",
669 .stream_name = "Playback_5",
670 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
671 SND_SOC_DPCM_TRIGGER_PRE},
672 .dynamic = 1,
673 .dpcm_playback = 1,
674 SND_SOC_DAILINK_REG(playback5),
675 },
676 {
677 .name = "Playback_6",
678 .stream_name = "Playback_6",
679 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
680 SND_SOC_DPCM_TRIGGER_PRE},
681 .dynamic = 1,
682 .dpcm_playback = 1,
683 SND_SOC_DAILINK_REG(playback6),
684 },
685 {
686 .name = "Playback_7",
687 .stream_name = "Playback_7",
688 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
689 SND_SOC_DPCM_TRIGGER_PRE},
690 .dynamic = 1,
691 .dpcm_playback = 1,
692 SND_SOC_DAILINK_REG(playback7),
693 },
694 {
695 .name = "Playback_8",
696 .stream_name = "Playback_8",
697 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
698 SND_SOC_DPCM_TRIGGER_PRE},
699 .dynamic = 1,
700 .dpcm_playback = 1,
701 SND_SOC_DAILINK_REG(playback8),
702 },
703 {
704 .name = "Playback_9",
705 .stream_name = "Playback_9",
706 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
707 SND_SOC_DPCM_TRIGGER_PRE},
708 .dynamic = 1,
709 .dpcm_playback = 1,
710 SND_SOC_DAILINK_REG(playback9),
711 },
712 {
713 .name = "Capture_1",
714 .stream_name = "Capture_1",
715 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
716 SND_SOC_DPCM_TRIGGER_PRE},
717 .dynamic = 1,
718 .dpcm_capture = 1,
Tzung-Bi Shih4cceb422021-02-03 11:22:01 +0800719 .ops = &mt8192_mt6359_capture1_ops,
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800720 SND_SOC_DAILINK_REG(capture1),
721 },
722 {
723 .name = "Capture_2",
724 .stream_name = "Capture_2",
725 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
726 SND_SOC_DPCM_TRIGGER_PRE},
727 .dynamic = 1,
728 .dpcm_capture = 1,
729 SND_SOC_DAILINK_REG(capture2),
730 },
731 {
732 .name = "Capture_3",
733 .stream_name = "Capture_3",
734 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
735 SND_SOC_DPCM_TRIGGER_PRE},
736 .dynamic = 1,
737 .dpcm_capture = 1,
738 SND_SOC_DAILINK_REG(capture3),
739 },
740 {
741 .name = "Capture_4",
742 .stream_name = "Capture_4",
743 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
744 SND_SOC_DPCM_TRIGGER_PRE},
745 .dynamic = 1,
746 .dpcm_capture = 1,
747 SND_SOC_DAILINK_REG(capture4),
748 },
749 {
750 .name = "Capture_5",
751 .stream_name = "Capture_5",
752 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
753 SND_SOC_DPCM_TRIGGER_PRE},
754 .dynamic = 1,
755 .dpcm_capture = 1,
756 SND_SOC_DAILINK_REG(capture5),
757 },
758 {
759 .name = "Capture_6",
760 .stream_name = "Capture_6",
761 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
762 SND_SOC_DPCM_TRIGGER_PRE},
763 .dynamic = 1,
764 .dpcm_capture = 1,
765 SND_SOC_DAILINK_REG(capture6),
766 },
767 {
768 .name = "Capture_7",
769 .stream_name = "Capture_7",
770 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
771 SND_SOC_DPCM_TRIGGER_PRE},
772 .dynamic = 1,
773 .dpcm_capture = 1,
774 SND_SOC_DAILINK_REG(capture7),
775 },
776 {
777 .name = "Capture_8",
778 .stream_name = "Capture_8",
779 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
780 SND_SOC_DPCM_TRIGGER_PRE},
781 .dynamic = 1,
782 .dpcm_capture = 1,
783 SND_SOC_DAILINK_REG(capture8),
784 },
785 {
786 .name = "Capture_Mono_1",
787 .stream_name = "Capture_Mono_1",
788 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
789 SND_SOC_DPCM_TRIGGER_PRE},
790 .dynamic = 1,
791 .dpcm_capture = 1,
792 SND_SOC_DAILINK_REG(capture_mono1),
793 },
794 {
795 .name = "Capture_Mono_2",
796 .stream_name = "Capture_Mono_2",
797 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
798 SND_SOC_DPCM_TRIGGER_PRE},
799 .dynamic = 1,
800 .dpcm_capture = 1,
801 SND_SOC_DAILINK_REG(capture_mono2),
802 },
803 {
804 .name = "Capture_Mono_3",
805 .stream_name = "Capture_Mono_3",
806 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
807 SND_SOC_DPCM_TRIGGER_PRE},
808 .dynamic = 1,
809 .dpcm_capture = 1,
810 SND_SOC_DAILINK_REG(capture_mono3),
811 },
812 {
813 .name = "playback_hdmi",
814 .stream_name = "Playback_HDMI",
815 .trigger = {SND_SOC_DPCM_TRIGGER_PRE,
816 SND_SOC_DPCM_TRIGGER_PRE},
817 .dynamic = 1,
818 .dpcm_playback = 1,
819 SND_SOC_DAILINK_REG(playback_hdmi),
820 },
821 /* Back End DAI links */
822 {
823 .name = "Primary Codec",
824 .no_pcm = 1,
825 .dpcm_playback = 1,
826 .dpcm_capture = 1,
827 .ignore_suspend = 1,
828 .init = mt8192_mt6359_init,
829 SND_SOC_DAILINK_REG(primary_codec),
830 },
831 {
832 .name = "Primary Codec CH34",
833 .no_pcm = 1,
834 .dpcm_playback = 1,
835 .dpcm_capture = 1,
836 .ignore_suspend = 1,
837 SND_SOC_DAILINK_REG(primary_codec_ch34),
838 },
839 {
840 .name = "AP_DMIC",
841 .no_pcm = 1,
842 .dpcm_capture = 1,
843 .ignore_suspend = 1,
844 SND_SOC_DAILINK_REG(ap_dmic),
845 },
846 {
847 .name = "AP_DMIC_CH34",
848 .no_pcm = 1,
849 .dpcm_capture = 1,
850 .ignore_suspend = 1,
851 SND_SOC_DAILINK_REG(ap_dmic_ch34),
852 },
853 {
854 .name = "I2S0",
855 .no_pcm = 1,
856 .dpcm_capture = 1,
857 .ignore_suspend = 1,
858 .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
859 SND_SOC_DAILINK_REG(i2s0),
860 },
861 {
862 .name = "I2S1",
863 .no_pcm = 1,
864 .dpcm_playback = 1,
865 .ignore_suspend = 1,
866 .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
867 SND_SOC_DAILINK_REG(i2s1),
868 },
869 {
870 .name = "I2S2",
871 .no_pcm = 1,
872 .dpcm_capture = 1,
873 .ignore_suspend = 1,
874 .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
875 SND_SOC_DAILINK_REG(i2s2),
876 },
877 {
878 .name = "I2S3",
879 .no_pcm = 1,
880 .dpcm_playback = 1,
881 .ignore_suspend = 1,
882 .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800883 },
884 {
885 .name = "I2S5",
886 .no_pcm = 1,
887 .dpcm_playback = 1,
888 .ignore_suspend = 1,
889 .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
890 SND_SOC_DAILINK_REG(i2s5),
891 },
892 {
893 .name = "I2S6",
894 .no_pcm = 1,
895 .dpcm_capture = 1,
896 .ignore_suspend = 1,
897 .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
898 SND_SOC_DAILINK_REG(i2s6),
899 },
900 {
901 .name = "I2S7",
902 .no_pcm = 1,
903 .dpcm_playback = 1,
904 .ignore_suspend = 1,
905 .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
906 SND_SOC_DAILINK_REG(i2s7),
907 },
908 {
909 .name = "I2S8",
910 .no_pcm = 1,
911 .dpcm_capture = 1,
912 .ignore_suspend = 1,
913 .init = mt8192_rt5682_init,
914 .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
915 SND_SOC_DAILINK_REG(i2s8),
916 .ops = &mt8192_rt5682_i2s_ops,
917 },
918 {
919 .name = "I2S9",
920 .no_pcm = 1,
921 .dpcm_playback = 1,
922 .ignore_suspend = 1,
923 .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
924 SND_SOC_DAILINK_REG(i2s9),
925 .ops = &mt8192_rt5682_i2s_ops,
926 },
927 {
928 .name = "CONNSYS_I2S",
929 .no_pcm = 1,
930 .dpcm_capture = 1,
931 .ignore_suspend = 1,
932 SND_SOC_DAILINK_REG(connsys_i2s),
933 },
934 {
935 .name = "PCM 1",
936 .no_pcm = 1,
937 .dpcm_playback = 1,
938 .dpcm_capture = 1,
939 .ignore_suspend = 1,
940 SND_SOC_DAILINK_REG(pcm1),
941 },
942 {
943 .name = "PCM 2",
944 .no_pcm = 1,
945 .dpcm_playback = 1,
946 .dpcm_capture = 1,
947 .ignore_suspend = 1,
948 SND_SOC_DAILINK_REG(pcm2),
949 },
950 {
951 .name = "TDM",
952 .no_pcm = 1,
Tzung-Bi Shih0d80c482021-01-20 16:08:50 +0800953 .dai_fmt = SND_SOC_DAIFMT_DSP_A |
954 SND_SOC_DAIFMT_IB_NF |
955 SND_SOC_DAIFMT_CBM_CFM,
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800956 .dpcm_playback = 1,
957 .ignore_suspend = 1,
Tzung-Bi Shih0d80c482021-01-20 16:08:50 +0800958 .be_hw_params_fixup = mt8192_i2s_hw_params_fixup,
959 .ignore = 1,
960 .init = mt8192_mt6359_hdmi_init,
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800961 SND_SOC_DAILINK_REG(tdm),
962 },
963};
964
Tzung-Bi Shihba499c32020-12-01 21:26:11 +0800965static const struct snd_soc_dapm_widget
966mt8192_mt6359_rt1015_rt5682_widgets[] = {
967 SND_SOC_DAPM_SPK("Left Spk", NULL),
968 SND_SOC_DAPM_SPK("Right Spk", NULL),
969 SND_SOC_DAPM_HP("Headphone Jack", NULL),
970 SND_SOC_DAPM_MIC("Headset Mic", NULL),
Tzung-Bi Shih0d80c482021-01-20 16:08:50 +0800971 SND_SOC_DAPM_OUTPUT("TDM Out"),
Tzung-Bi Shihba499c32020-12-01 21:26:11 +0800972};
973
974static const struct snd_soc_dapm_route mt8192_mt6359_rt1015_rt5682_routes[] = {
975 /* speaker */
976 { "Left Spk", NULL, "Left SPO" },
977 { "Right Spk", NULL, "Right SPO" },
978 /* headset */
979 { "Headphone Jack", NULL, "HPOL" },
980 { "Headphone Jack", NULL, "HPOR" },
981 { "IN1P", NULL, "Headset Mic" },
Tzung-Bi Shih0d80c482021-01-20 16:08:50 +0800982 /* TDM */
983 { "TDM Out", NULL, "TDM" },
Tzung-Bi Shihba499c32020-12-01 21:26:11 +0800984};
985
986static const struct snd_kcontrol_new mt8192_mt6359_rt1015_rt5682_controls[] = {
987 SOC_DAPM_PIN_SWITCH("Left Spk"),
988 SOC_DAPM_PIN_SWITCH("Right Spk"),
989 SOC_DAPM_PIN_SWITCH("Headphone Jack"),
990 SOC_DAPM_PIN_SWITCH("Headset Mic"),
991};
992
Jiaxin Yu18b13ff2020-11-03 15:59:37 +0800993static struct snd_soc_codec_conf rt1015_amp_conf[] = {
994 {
995 .dlc = COMP_CODEC_CONF(RT1015_DEV0_NAME),
996 .name_prefix = "Left",
997 },
998 {
999 .dlc = COMP_CODEC_CONF(RT1015_DEV1_NAME),
1000 .name_prefix = "Right",
1001 },
1002};
1003
Tzung-Bi Shih2b53d2e2020-12-01 21:26:10 +08001004static struct snd_soc_card mt8192_mt6359_rt1015_rt5682_card = {
Jiaxin Yu18b13ff2020-11-03 15:59:37 +08001005 .name = "mt8192_mt6359_rt1015_rt5682",
1006 .owner = THIS_MODULE,
Tzung-Bi Shiha5f80372020-12-01 21:26:09 +08001007 .dai_link = mt8192_mt6359_dai_links,
1008 .num_links = ARRAY_SIZE(mt8192_mt6359_dai_links),
Jiaxin Yu18b13ff2020-11-03 15:59:37 +08001009 .controls = mt8192_mt6359_rt1015_rt5682_controls,
1010 .num_controls = ARRAY_SIZE(mt8192_mt6359_rt1015_rt5682_controls),
1011 .dapm_widgets = mt8192_mt6359_rt1015_rt5682_widgets,
1012 .num_dapm_widgets = ARRAY_SIZE(mt8192_mt6359_rt1015_rt5682_widgets),
1013 .dapm_routes = mt8192_mt6359_rt1015_rt5682_routes,
1014 .num_dapm_routes = ARRAY_SIZE(mt8192_mt6359_rt1015_rt5682_routes),
1015 .codec_conf = rt1015_amp_conf,
1016 .num_configs = ARRAY_SIZE(rt1015_amp_conf),
1017};
1018
Tzung-Bi Shihcfd8bb22020-12-01 21:26:14 +08001019static const struct snd_soc_dapm_widget
1020mt8192_mt6359_rt1015p_rt5682_widgets[] = {
1021 SND_SOC_DAPM_SPK("Speakers", NULL),
1022 SND_SOC_DAPM_HP("Headphone Jack", NULL),
1023 SND_SOC_DAPM_MIC("Headset Mic", NULL),
1024};
1025
1026static const struct snd_soc_dapm_route mt8192_mt6359_rt1015p_rt5682_routes[] = {
1027 /* speaker */
1028 { "Speakers", NULL, "Speaker" },
1029 /* headset */
1030 { "Headphone Jack", NULL, "HPOL" },
1031 { "Headphone Jack", NULL, "HPOR" },
1032 { "IN1P", NULL, "Headset Mic" },
1033};
1034
1035static const struct snd_kcontrol_new mt8192_mt6359_rt1015p_rt5682_controls[] = {
1036 SOC_DAPM_PIN_SWITCH("Speakers"),
1037 SOC_DAPM_PIN_SWITCH("Headphone Jack"),
1038 SOC_DAPM_PIN_SWITCH("Headset Mic"),
1039};
1040
1041static struct snd_soc_card mt8192_mt6359_rt1015p_rt5682_card = {
1042 .name = "mt8192_mt6359_rt1015p_rt5682",
1043 .owner = THIS_MODULE,
1044 .dai_link = mt8192_mt6359_dai_links,
1045 .num_links = ARRAY_SIZE(mt8192_mt6359_dai_links),
1046 .controls = mt8192_mt6359_rt1015p_rt5682_controls,
1047 .num_controls = ARRAY_SIZE(mt8192_mt6359_rt1015p_rt5682_controls),
1048 .dapm_widgets = mt8192_mt6359_rt1015p_rt5682_widgets,
1049 .num_dapm_widgets = ARRAY_SIZE(mt8192_mt6359_rt1015p_rt5682_widgets),
1050 .dapm_routes = mt8192_mt6359_rt1015p_rt5682_routes,
1051 .num_dapm_routes = ARRAY_SIZE(mt8192_mt6359_rt1015p_rt5682_routes),
1052};
1053
Tzung-Bi Shiha5f80372020-12-01 21:26:09 +08001054static int mt8192_mt6359_dev_probe(struct platform_device *pdev)
Jiaxin Yu18b13ff2020-11-03 15:59:37 +08001055{
Tzung-Bi Shih2b53d2e2020-12-01 21:26:10 +08001056 struct snd_soc_card *card;
Tzung-Bi Shih0d80c482021-01-20 16:08:50 +08001057 struct device_node *platform_node, *hdmi_codec;
Jiaxin Yu18b13ff2020-11-03 15:59:37 +08001058 int ret, i;
1059 struct snd_soc_dai_link *dai_link;
Tzung-Bi Shih2b53d2e2020-12-01 21:26:10 +08001060 const struct of_device_id *match;
Tzung-Bi Shih4e375282021-01-20 16:08:46 +08001061 struct mt8192_mt6359_priv *priv;
Jiaxin Yu18b13ff2020-11-03 15:59:37 +08001062
1063 platform_node = of_parse_phandle(pdev->dev.of_node,
1064 "mediatek,platform", 0);
1065 if (!platform_node) {
1066 dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
1067 return -EINVAL;
1068 }
1069
Tzung-Bi Shih2b53d2e2020-12-01 21:26:10 +08001070 match = of_match_device(pdev->dev.driver->of_match_table, &pdev->dev);
1071 if (!match || !match->data)
1072 return -EINVAL;
1073
1074 card = (struct snd_soc_card *)match->data;
1075 card->dev = &pdev->dev;
1076
Tzung-Bi Shih0d80c482021-01-20 16:08:50 +08001077 hdmi_codec = of_parse_phandle(pdev->dev.of_node,
1078 "mediatek,hdmi-codec", 0);
1079
Jiaxin Yu18b13ff2020-11-03 15:59:37 +08001080 for_each_card_prelinks(card, i, dai_link) {
Tzung-Bi Shih2b53d2e2020-12-01 21:26:10 +08001081 if (strcmp(dai_link->name, "I2S3") == 0) {
1082 if (card == &mt8192_mt6359_rt1015_rt5682_card) {
1083 dai_link->ops = &mt8192_rt1015_i2s_ops;
1084 dai_link->cpus = i2s3_rt1015_cpus;
1085 dai_link->num_cpus =
1086 ARRAY_SIZE(i2s3_rt1015_cpus);
1087 dai_link->codecs = i2s3_rt1015_codecs;
1088 dai_link->num_codecs =
1089 ARRAY_SIZE(i2s3_rt1015_codecs);
1090 dai_link->platforms = i2s3_rt1015_platforms;
1091 dai_link->num_platforms =
1092 ARRAY_SIZE(i2s3_rt1015_platforms);
Tzung-Bi Shihcfd8bb22020-12-01 21:26:14 +08001093 } else if (card == &mt8192_mt6359_rt1015p_rt5682_card) {
1094 dai_link->cpus = i2s3_rt1015p_cpus;
1095 dai_link->num_cpus =
1096 ARRAY_SIZE(i2s3_rt1015p_cpus);
1097 dai_link->codecs = i2s3_rt1015p_codecs;
1098 dai_link->num_codecs =
1099 ARRAY_SIZE(i2s3_rt1015p_codecs);
1100 dai_link->platforms = i2s3_rt1015p_platforms;
1101 dai_link->num_platforms =
1102 ARRAY_SIZE(i2s3_rt1015p_platforms);
Tzung-Bi Shih2b53d2e2020-12-01 21:26:10 +08001103 }
1104 }
1105
Tzung-Bi Shih0d80c482021-01-20 16:08:50 +08001106 if (hdmi_codec && strcmp(dai_link->name, "TDM") == 0) {
1107 dai_link->codecs->of_node = hdmi_codec;
1108 dai_link->ignore = 0;
1109 }
1110
Jiaxin Yu18b13ff2020-11-03 15:59:37 +08001111 if (!dai_link->platforms->name)
1112 dai_link->platforms->of_node = platform_node;
1113 }
1114
Tzung-Bi Shih4e375282021-01-20 16:08:46 +08001115 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1116 if (!priv)
1117 return -ENOMEM;
1118 snd_soc_card_set_drvdata(card, priv);
1119
Jiaxin Yu18b13ff2020-11-03 15:59:37 +08001120 ret = mt8192_afe_gpio_init(&pdev->dev);
1121 if (ret) {
1122 dev_err(&pdev->dev, "init gpio error %d\n", ret);
1123 return ret;
1124 }
1125
1126 return devm_snd_soc_register_card(&pdev->dev, card);
1127}
1128
1129#ifdef CONFIG_OF
Tzung-Bi Shiha5f80372020-12-01 21:26:09 +08001130static const struct of_device_id mt8192_mt6359_dt_match[] = {
Tzung-Bi Shih2b53d2e2020-12-01 21:26:10 +08001131 {
1132 .compatible = "mediatek,mt8192_mt6359_rt1015_rt5682",
1133 .data = &mt8192_mt6359_rt1015_rt5682_card,
1134 },
Tzung-Bi Shihcfd8bb22020-12-01 21:26:14 +08001135 {
1136 .compatible = "mediatek,mt8192_mt6359_rt1015p_rt5682",
1137 .data = &mt8192_mt6359_rt1015p_rt5682_card,
1138 },
Jiaxin Yu18b13ff2020-11-03 15:59:37 +08001139 {}
1140};
1141#endif
1142
Tzung-Bi Shiha5f80372020-12-01 21:26:09 +08001143static const struct dev_pm_ops mt8192_mt6359_pm_ops = {
Jiaxin Yu18b13ff2020-11-03 15:59:37 +08001144 .poweroff = snd_soc_poweroff,
1145 .restore = snd_soc_resume,
1146};
1147
Tzung-Bi Shiha5f80372020-12-01 21:26:09 +08001148static struct platform_driver mt8192_mt6359_driver = {
Jiaxin Yu18b13ff2020-11-03 15:59:37 +08001149 .driver = {
Tzung-Bi Shiha5f80372020-12-01 21:26:09 +08001150 .name = "mt8192_mt6359",
Jiaxin Yu18b13ff2020-11-03 15:59:37 +08001151#ifdef CONFIG_OF
Tzung-Bi Shiha5f80372020-12-01 21:26:09 +08001152 .of_match_table = mt8192_mt6359_dt_match,
Jiaxin Yu18b13ff2020-11-03 15:59:37 +08001153#endif
Tzung-Bi Shiha5f80372020-12-01 21:26:09 +08001154 .pm = &mt8192_mt6359_pm_ops,
Jiaxin Yu18b13ff2020-11-03 15:59:37 +08001155 },
Tzung-Bi Shiha5f80372020-12-01 21:26:09 +08001156 .probe = mt8192_mt6359_dev_probe,
Jiaxin Yu18b13ff2020-11-03 15:59:37 +08001157};
1158
Tzung-Bi Shiha5f80372020-12-01 21:26:09 +08001159module_platform_driver(mt8192_mt6359_driver);
Jiaxin Yu18b13ff2020-11-03 15:59:37 +08001160
1161/* Module information */
Tzung-Bi Shiha5f80372020-12-01 21:26:09 +08001162MODULE_DESCRIPTION("MT8192-MT6359 ALSA SoC machine driver");
Jiaxin Yu18b13ff2020-11-03 15:59:37 +08001163MODULE_AUTHOR("Jiaxin Yu <jiaxin.yu@mediatek.com>");
1164MODULE_LICENSE("GPL v2");
Tzung-Bi Shiha5f80372020-12-01 21:26:09 +08001165MODULE_ALIAS("mt8192_mt6359 soc card");