| Fabien Parent | a682248 | 2020-09-18 15:23:03 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) 2020 MediaTek Inc. |
| 4 | * Copyright (c) 2020 BayLibre, SAS |
| 5 | * Author: James Liao <jamesjj.liao@mediatek.com> |
| 6 | * Fabien Parent <fparent@baylibre.com> |
| 7 | */ |
| 8 | |
| 9 | #include <linux/clk-provider.h> |
| 10 | #include <linux/of.h> |
| 11 | #include <linux/of_address.h> |
| 12 | #include <linux/of_device.h> |
| 13 | #include <linux/platform_device.h> |
| 14 | |
| 15 | #include "clk-mtk.h" |
| 16 | #include "clk-gate.h" |
| 17 | |
| 18 | #include <dt-bindings/clock/mt8167-clk.h> |
| 19 | |
| 20 | static const struct mtk_gate_regs aud_cg_regs = { |
| 21 | .set_ofs = 0x0, |
| 22 | .clr_ofs = 0x0, |
| 23 | .sta_ofs = 0x0, |
| 24 | }; |
| 25 | |
| 26 | #define GATE_AUD(_id, _name, _parent, _shift) { \ |
| 27 | .id = _id, \ |
| 28 | .name = _name, \ |
| 29 | .parent_name = _parent, \ |
| 30 | .regs = &aud_cg_regs, \ |
| 31 | .shift = _shift, \ |
| 32 | .ops = &mtk_clk_gate_ops_no_setclr, \ |
| 33 | } |
| 34 | |
| 35 | static const struct mtk_gate aud_clks[] __initconst = { |
| 36 | GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2), |
| 37 | GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6), |
| 38 | GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8), |
| 39 | GATE_AUD(CLK_AUD_24M, "aud_24m", "rg_aud_engen2", 9), |
| 40 | GATE_AUD(CLK_AUD_INTDIR, "aud_intdir", "rg_aud_spdif_in", 15), |
| 41 | GATE_AUD(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "rg_aud_engen2", 18), |
| 42 | GATE_AUD(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "rg_aud_engen1", 19), |
| 43 | GATE_AUD(CLK_AUD_HDMI, "aud_hdmi", "apll12_div4", 20), |
| 44 | GATE_AUD(CLK_AUD_SPDF, "aud_spdf", "apll12_div6", 21), |
| 45 | GATE_AUD(CLK_AUD_ADC, "aud_adc", "aud_afe", 24), |
| 46 | GATE_AUD(CLK_AUD_DAC, "aud_dac", "aud_afe", 25), |
| 47 | GATE_AUD(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "aud_afe", 26), |
| 48 | GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27), |
| 49 | }; |
| 50 | |
| 51 | static void __init mtk_audsys_init(struct device_node *node) |
| 52 | { |
| 53 | struct clk_onecell_data *clk_data; |
| 54 | int r; |
| 55 | |
| 56 | clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK); |
| 57 | |
| 58 | mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data); |
| 59 | |
| 60 | r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| 61 | if (r) |
| 62 | pr_err("%s(): could not register clock provider: %d\n", |
| 63 | __func__, r); |
| 64 | |
| 65 | } |
| 66 | CLK_OF_DECLARE(mtk_audsys, "mediatek,mt8167-audsys", mtk_audsys_init); |