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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 496456058b506233a88ca60dbedbcb0e681d2423 / . / arch / arm / boot / dts / imx7ulp.dtsi
blob: d6b711011cba831348c6f4c2cb68f94ef788c1c9 [file] [log] [blame]
A.s. Dong20434dc2018-11-10 15:13:08 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP
5 * Dong Aisheng <aisheng.dong@nxp.com>
6 */
7
8#include <dt-bindings/clock/imx7ulp-clock.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12#include "imx7ulp-pinfunc.h"
13
14/ {
15 interrupt-parent = <&intc>;
16
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 gpio0 = &gpio_ptc;
22 gpio1 = &gpio_ptd;
23 gpio2 = &gpio_pte;
24 gpio3 = &gpio_ptf;
25 i2c0 = &lpi2c6;
26 i2c1 = &lpi2c7;
27 mmc0 = &usdhc0;
28 mmc1 = &usdhc1;
29 serial0 = &lpuart4;
30 serial1 = &lpuart5;
31 serial2 = &lpuart6;
32 serial3 = &lpuart7;
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 cpu0: cpu@0 {
40 compatible = "arm,cortex-a7";
41 device_type = "cpu";
42 reg = <0>;
43 };
44 };
45
46 intc: interrupt-controller@40021000 {
47 compatible = "arm,cortex-a7-gic";
48 #interrupt-cells = <3>;
49 interrupt-controller;
50 reg = <0x40021000 0x1000>,
51 <0x40022000 0x1000>;
52 };
53
54 rosc: clock-rosc {
55 compatible = "fixed-clock";
56 clock-frequency = <32768>;
57 clock-output-names = "rosc";
58 #clock-cells = <0>;
59 };
60
61 sosc: clock-sosc {
62 compatible = "fixed-clock";
63 clock-frequency = <24000000>;
64 clock-output-names = "sosc";
65 #clock-cells = <0>;
66 };
67
68 sirc: clock-sirc {
69 compatible = "fixed-clock";
70 clock-frequency = <16000000>;
71 clock-output-names = "sirc";
72 #clock-cells = <0>;
73 };
74
75 firc: clock-firc {
76 compatible = "fixed-clock";
77 clock-frequency = <48000000>;
78 clock-output-names = "firc";
79 #clock-cells = <0>;
80 };
81
82 upll: clock-upll {
83 compatible = "fixed-clock";
84 clock-frequency = <480000000>;
85 clock-output-names = "upll";
86 #clock-cells = <0>;
87 };
88
89 mpll: clock-mpll {
90 compatible = "fixed-clock";
91 clock-frequency = <480000000>;
92 clock-output-names = "mpll";
93 #clock-cells = <0>;
94 };
95
96 ahbbridge0: bus@40000000 {
97 compatible = "simple-bus";
98 #address-cells = <1>;
99 #size-cells = <1>;
100 reg = <0x40000000 0x800000>;
101 ranges;
102
103 lpuart4: serial@402d0000 {
104 compatible = "fsl,imx7ulp-lpuart";
105 reg = <0x402d0000 0x1000>;
106 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
108 clock-names = "ipg";
109 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
110 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
111 assigned-clock-rates = <24000000>;
112 status = "disabled";
113 };
114
115 lpuart5: serial@402e0000 {
116 compatible = "fsl,imx7ulp-lpuart";
117 reg = <0x402e0000 0x1000>;
118 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
120 clock-names = "ipg";
121 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
122 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
123 assigned-clock-rates = <48000000>;
124 status = "disabled";
125 };
126
127 tpm5: tpm@40260000 {
128 compatible = "fsl,imx7ulp-tpm";
129 reg = <0x40260000 0x1000>;
130 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
132 <&pcc2 IMX7ULP_CLK_LPTPM5>;
133 clock-names = "ipg", "per";
134 };
135
136 usdhc0: mmc@40370000 {
137 compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
138 reg = <0x40370000 0x10000>;
139 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
141 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
142 <&pcc2 IMX7ULP_CLK_USDHC0>;
143 clock-names ="ipg", "ahb", "per";
144 assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
145 assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
146 bus-width = <4>;
147 fsl,tuning-start-tap = <20>;
148 fsl,tuning-step= <2>;
149 status = "disabled";
150 };
151
152 usdhc1: mmc@40380000 {
153 compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
154 reg = <0x40380000 0x10000>;
155 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
157 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
158 <&pcc2 IMX7ULP_CLK_USDHC1>;
159 clock-names ="ipg", "ahb", "per";
160 assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
161 assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
162 bus-width = <4>;
163 fsl,tuning-start-tap = <20>;
164 fsl,tuning-step= <2>;
165 status = "disabled";
166 };
167
168 scg1: clock-controller@403e0000 {
169 compatible = "fsl,imx7ulp-scg1";
170 reg = <0x403e0000 0x10000>;
171 clocks = <&rosc>, <&sosc>, <&sirc>,
172 <&firc>, <&upll>, <&mpll>;
173 clock-names = "rosc", "sosc", "sirc",
174 "firc", "upll", "mpll";
175 #clock-cells = <1>;
176 };
177
178 pcc2: clock-controller@403f0000 {
179 compatible = "fsl,imx7ulp-pcc2";
180 reg = <0x403f0000 0x10000>;
181 #clock-cells = <1>;
182 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
183 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
184 <&scg1 IMX7ULP_CLK_DDR_DIV>,
185 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
186 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
187 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
188 <&scg1 IMX7ULP_CLK_UPLL>,
189 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
190 <&scg1 IMX7ULP_CLK_MIPI_PLL>,
191 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
192 <&scg1 IMX7ULP_CLK_ROSC>,
193 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
194 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
195 "apll_pfd2", "apll_pfd1", "apll_pfd0",
196 "upll", "sosc_bus_clk", "mpll",
197 "firc_bus_clk", "rosc", "spll_bus_clk";
198 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
199 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
200 };
201
Anson Huang13c033b2018-12-07 10:03:39 +0000[diff] [blame]202 smc1: clock-controller@40410000 {
A.s. Dong20434dc2018-11-10 15:13:08 +0000[diff] [blame]203 compatible = "fsl,imx7ulp-smc1";
204 reg = <0x40410000 0x1000>;
Anson Huang13c033b2018-12-07 10:03:39 +0000[diff] [blame]205 #clock-cells = <1>;
206 clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
207 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
208 clock-names = "divcore", "hsrun_divcore";
A.s. Dong20434dc2018-11-10 15:13:08 +0000[diff] [blame]209 };
210
211 pcc3: clock-controller@40b30000 {
212 compatible = "fsl,imx7ulp-pcc3";
213 reg = <0x40b30000 0x10000>;
214 #clock-cells = <1>;
215 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
216 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
217 <&scg1 IMX7ULP_CLK_DDR_DIV>,
218 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
219 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
220 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
221 <&scg1 IMX7ULP_CLK_UPLL>,
222 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
223 <&scg1 IMX7ULP_CLK_MIPI_PLL>,
224 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
225 <&scg1 IMX7ULP_CLK_ROSC>,
226 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
227 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
228 "apll_pfd2", "apll_pfd1", "apll_pfd0",
229 "upll", "sosc_bus_clk", "mpll",
230 "firc_bus_clk", "rosc", "spll_bus_clk";
231 };
232 };
233
234 ahbbridge1: bus@40800000 {
235 compatible = "simple-bus";
236 #address-cells = <1>;
237 #size-cells = <1>;
238 reg = <0x40800000 0x800000>;
239 ranges;
240
241 lpi2c6: i2c@40a40000 {
242 compatible = "fsl,imx7ulp-lpi2c";
243 reg = <0x40a40000 0x10000>;
244 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
246 clock-names = "ipg";
247 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
248 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
249 assigned-clock-rates = <48000000>;
250 status = "disabled";
251 };
252
253 lpi2c7: i2c@40a50000 {
254 compatible = "fsl,imx7ulp-lpi2c";
255 reg = <0x40a50000 0x10000>;
256 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
258 clock-names = "ipg";
259 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
260 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
261 assigned-clock-rates = <48000000>;
262 status = "disabled";
263 };
264
265 lpuart6: serial@40a60000 {
266 compatible = "fsl,imx7ulp-lpuart";
267 reg = <0x40a60000 0x1000>;
268 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
270 clock-names = "ipg";
271 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
272 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
273 assigned-clock-rates = <48000000>;
274 status = "disabled";
275 };
276
277 lpuart7: serial@40a70000 {
278 compatible = "fsl,imx7ulp-lpuart";
279 reg = <0x40a70000 0x1000>;
280 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
282 clock-names = "ipg";
283 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
284 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
285 assigned-clock-rates = <48000000>;
286 status = "disabled";
287 };
288
Anson Huang10ee87d2019-03-12 02:24:12 +0000[diff] [blame]289 memory-controller@40ab0000 {
290 compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
291 reg = <0x40ab0000 0x1000>;
292 clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
293 };
294
A.s. Dong20434dc2018-11-10 15:13:08 +0000[diff] [blame]295 iomuxc1: pinctrl@40ac0000 {
296 compatible = "fsl,imx7ulp-iomuxc1";
297 reg = <0x40ac0000 0x1000>;
298 };
299
300 gpio_ptc: gpio@40ae0000 {
301 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
302 reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
303 gpio-controller;
304 #gpio-cells = <2>;
305 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
306 interrupt-controller;
307 #interrupt-cells = <2>;
308 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
309 <&pcc3 IMX7ULP_CLK_PCTLC>;
310 clock-names = "gpio", "port";
311 gpio-ranges = <&iomuxc1 0 0 32>;
312 };
313
314 gpio_ptd: gpio@40af0000 {
315 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
316 reg = <0x40af0000 0x1000 0x400f0040 0x40>;
317 gpio-controller;
318 #gpio-cells = <2>;
319 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
320 interrupt-controller;
321 #interrupt-cells = <2>;
322 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
323 <&pcc3 IMX7ULP_CLK_PCTLD>;
324 clock-names = "gpio", "port";
325 gpio-ranges = <&iomuxc1 0 32 32>;
326 };
327
328 gpio_pte: gpio@40b00000 {
329 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
330 reg = <0x40b00000 0x1000 0x400f0080 0x40>;
331 gpio-controller;
332 #gpio-cells = <2>;
333 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
334 interrupt-controller;
335 #interrupt-cells = <2>;
336 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
337 <&pcc3 IMX7ULP_CLK_PCTLE>;
338 clock-names = "gpio", "port";
339 gpio-ranges = <&iomuxc1 0 64 32>;
340 };
341
342 gpio_ptf: gpio@40b10000 {
343 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
344 reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
345 gpio-controller;
346 #gpio-cells = <2>;
347 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
350 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
351 <&pcc3 IMX7ULP_CLK_PCTLF>;
352 clock-names = "gpio", "port";
353 gpio-ranges = <&iomuxc1 0 96 32>;
354 };
355 };
Anson Huangcc077d02019-01-11 06:22:55 +0000[diff] [blame]356
357 m4aips1: bus@41080000 {
358 compatible = "simple-bus";
359 #address-cells = <1>;
360 #size-cells = <1>;
361 reg = <0x41080000 0x80000>;
362 ranges;
363
364 sim: sim@410a3000 {
365 compatible = "fsl,imx7ulp-sim", "syscon";
366 reg = <0x410a3000 0x1000>;
367 };
Anson Huang496456052019-03-22 06:31:56 +0000[diff] [blame^]368
369 ocotp: ocotp-ctrl@410a6000 {
370 compatible = "fsl,imx7ulp-ocotp", "syscon";
371 reg = <0x410a6000 0x4000>;
372 clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
373 };
Anson Huangcc077d02019-01-11 06:22:55 +0000[diff] [blame]374 };
A.s. Dong20434dc2018-11-10 15:13:08 +0000[diff] [blame]375};