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Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Jordan Crouse9fe757b2006-10-04 18:48:57 +10002/* Copyright (C) 2003-2006, Advanced Micro Devices, Inc.
Jordan Crouse9fe757b2006-10-04 18:48:57 +10003 */
4
5#ifndef _GEODE_AES_H_
6#define _GEODE_AES_H_
7
Sebastian Siewiorb7a30da2007-10-21 16:21:25 +08008/* driver logic flags */
Jordan Crouse9fe757b2006-10-04 18:48:57 +10009#define AES_MODE_ECB 0
10#define AES_MODE_CBC 1
11
12#define AES_DIR_DECRYPT 0
13#define AES_DIR_ENCRYPT 1
14
Jordan Crouse761e7842007-05-24 21:23:24 +100015#define AES_FLAGS_HIDDENKEY (1 << 0)
Jordan Crouse9fe757b2006-10-04 18:48:57 +100016
Sebastian Siewiorb7a30da2007-10-21 16:21:25 +080017/* Register definitions */
18
19#define AES_CTRLA_REG 0x0000
20
21#define AES_CTRL_START 0x01
22#define AES_CTRL_DECRYPT 0x00
23#define AES_CTRL_ENCRYPT 0x02
24#define AES_CTRL_WRKEY 0x04
25#define AES_CTRL_DCA 0x08
26#define AES_CTRL_SCA 0x10
27#define AES_CTRL_CBC 0x20
28
29#define AES_INTR_REG 0x0008
30
31#define AES_INTRA_PENDING (1 << 16)
32#define AES_INTRB_PENDING (1 << 17)
33
34#define AES_INTR_PENDING (AES_INTRA_PENDING | AES_INTRB_PENDING)
35#define AES_INTR_MASK 0x07
36
37#define AES_SOURCEA_REG 0x0010
38#define AES_DSTA_REG 0x0014
39#define AES_LENA_REG 0x0018
40#define AES_WRITEKEY0_REG 0x0030
41#define AES_WRITEIV0_REG 0x0040
42
43/* A very large counter that is used to gracefully bail out of an
44 * operation in case of trouble
45 */
46
47#define AES_OP_TIMEOUT 0x50000
48
Eric Biggers4549f7e2019-10-10 21:51:32 -070049struct geode_aes_tfm_ctx {
Marek Vasut2e1fc342014-05-14 11:36:40 +020050 u8 key[AES_KEYSIZE_128];
Sebastian Siewiorcd7c3bf2007-11-10 19:29:33 +080051 union {
Eric Biggers4549f7e2019-10-10 21:51:32 -070052 struct crypto_skcipher *skcipher;
Sebastian Siewiorcd7c3bf2007-11-10 19:29:33 +080053 struct crypto_cipher *cip;
54 } fallback;
55 u32 keylen;
Jordan Crouse9fe757b2006-10-04 18:48:57 +100056};
57
Jordan Crouse9fe757b2006-10-04 18:48:57 +100058#endif