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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 495716b191f607b2cb2175f7499966daef79f663 / . / include / linux / mlx5 / mlx5_ifc.h
blob: ae7c08adba4a0f981dbb9b8389e8f9e8b403e0fd [file] [log] [blame]
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]1/*
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]31*/
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
35enum {
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
69enum {
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]70 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
71 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
72 MLX5_CMD_OP_INIT_HCA = 0x102,
73 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
74 MLX5_CMD_OP_ENABLE_HCA = 0x104,
75 MLX5_CMD_OP_DISABLE_HCA = 0x105,
76 MLX5_CMD_OP_QUERY_PAGES = 0x107,
77 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
78 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]79 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
80 MLX5_CMD_OP_SET_ISSI = 0x10b,
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]81 MLX5_CMD_OP_CREATE_MKEY = 0x200,
82 MLX5_CMD_OP_QUERY_MKEY = 0x201,
83 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
84 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
85 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
86 MLX5_CMD_OP_CREATE_EQ = 0x301,
87 MLX5_CMD_OP_DESTROY_EQ = 0x302,
88 MLX5_CMD_OP_QUERY_EQ = 0x303,
89 MLX5_CMD_OP_GEN_EQE = 0x304,
90 MLX5_CMD_OP_CREATE_CQ = 0x400,
91 MLX5_CMD_OP_DESTROY_CQ = 0x401,
92 MLX5_CMD_OP_QUERY_CQ = 0x402,
93 MLX5_CMD_OP_MODIFY_CQ = 0x403,
94 MLX5_CMD_OP_CREATE_QP = 0x500,
95 MLX5_CMD_OP_DESTROY_QP = 0x501,
96 MLX5_CMD_OP_RST2INIT_QP = 0x502,
97 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
98 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
99 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
100 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
101 MLX5_CMD_OP_2ERR_QP = 0x507,
102 MLX5_CMD_OP_2RST_QP = 0x50a,
103 MLX5_CMD_OP_QUERY_QP = 0x50b,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]104 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]105 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
106 MLX5_CMD_OP_CREATE_PSV = 0x600,
107 MLX5_CMD_OP_DESTROY_PSV = 0x601,
108 MLX5_CMD_OP_CREATE_SRQ = 0x700,
109 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
110 MLX5_CMD_OP_QUERY_SRQ = 0x702,
111 MLX5_CMD_OP_ARM_RQ = 0x703,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]112 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
113 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
114 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
115 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]116 MLX5_CMD_OP_CREATE_DCT = 0x710,
117 MLX5_CMD_OP_DESTROY_DCT = 0x711,
118 MLX5_CMD_OP_DRAIN_DCT = 0x712,
119 MLX5_CMD_OP_QUERY_DCT = 0x713,
120 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
121 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
122 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
123 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
124 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
125 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
126 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]127 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]128 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]129 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
130 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
131 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
132 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]133 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
134 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
135 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
136 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
137 MLX5_CMD_OP_ALLOC_PD = 0x800,
138 MLX5_CMD_OP_DEALLOC_PD = 0x801,
139 MLX5_CMD_OP_ALLOC_UAR = 0x802,
140 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
141 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
142 MLX5_CMD_OP_ACCESS_REG = 0x805,
143 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]144 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]145 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
146 MLX5_CMD_OP_MAD_IFC = 0x50d,
147 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
148 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
149 MLX5_CMD_OP_NOP = 0x80d,
150 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
151 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]152 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
153 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
154 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
155 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
156 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
157 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
158 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
159 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
160 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
161 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
162 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
163 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]164 MLX5_CMD_OP_CREATE_TIR = 0x900,
165 MLX5_CMD_OP_MODIFY_TIR = 0x901,
166 MLX5_CMD_OP_DESTROY_TIR = 0x902,
167 MLX5_CMD_OP_QUERY_TIR = 0x903,
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]168 MLX5_CMD_OP_CREATE_SQ = 0x904,
169 MLX5_CMD_OP_MODIFY_SQ = 0x905,
170 MLX5_CMD_OP_DESTROY_SQ = 0x906,
171 MLX5_CMD_OP_QUERY_SQ = 0x907,
172 MLX5_CMD_OP_CREATE_RQ = 0x908,
173 MLX5_CMD_OP_MODIFY_RQ = 0x909,
174 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
175 MLX5_CMD_OP_QUERY_RQ = 0x90b,
176 MLX5_CMD_OP_CREATE_RMP = 0x90c,
177 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
178 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
179 MLX5_CMD_OP_QUERY_RMP = 0x90f,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]180 MLX5_CMD_OP_CREATE_TIS = 0x912,
181 MLX5_CMD_OP_MODIFY_TIS = 0x913,
182 MLX5_CMD_OP_DESTROY_TIS = 0x914,
183 MLX5_CMD_OP_QUERY_TIS = 0x915,
184 MLX5_CMD_OP_CREATE_RQT = 0x916,
185 MLX5_CMD_OP_MODIFY_RQT = 0x917,
186 MLX5_CMD_OP_DESTROY_RQT = 0x918,
187 MLX5_CMD_OP_QUERY_RQT = 0x919,
188 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
189 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
190 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
191 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
192 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
193 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
194 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
195 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
196 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938
197};
198
199struct mlx5_ifc_flow_table_fields_supported_bits {
200 u8 outer_dmac[0x1];
201 u8 outer_smac[0x1];
202 u8 outer_ether_type[0x1];
203 u8 reserved_0[0x1];
204 u8 outer_first_prio[0x1];
205 u8 outer_first_cfi[0x1];
206 u8 outer_first_vid[0x1];
207 u8 reserved_1[0x1];
208 u8 outer_second_prio[0x1];
209 u8 outer_second_cfi[0x1];
210 u8 outer_second_vid[0x1];
211 u8 reserved_2[0x1];
212 u8 outer_sip[0x1];
213 u8 outer_dip[0x1];
214 u8 outer_frag[0x1];
215 u8 outer_ip_protocol[0x1];
216 u8 outer_ip_ecn[0x1];
217 u8 outer_ip_dscp[0x1];
218 u8 outer_udp_sport[0x1];
219 u8 outer_udp_dport[0x1];
220 u8 outer_tcp_sport[0x1];
221 u8 outer_tcp_dport[0x1];
222 u8 outer_tcp_flags[0x1];
223 u8 outer_gre_protocol[0x1];
224 u8 outer_gre_key[0x1];
225 u8 outer_vxlan_vni[0x1];
226 u8 reserved_3[0x5];
227 u8 source_eswitch_port[0x1];
228
229 u8 inner_dmac[0x1];
230 u8 inner_smac[0x1];
231 u8 inner_ether_type[0x1];
232 u8 reserved_4[0x1];
233 u8 inner_first_prio[0x1];
234 u8 inner_first_cfi[0x1];
235 u8 inner_first_vid[0x1];
236 u8 reserved_5[0x1];
237 u8 inner_second_prio[0x1];
238 u8 inner_second_cfi[0x1];
239 u8 inner_second_vid[0x1];
240 u8 reserved_6[0x1];
241 u8 inner_sip[0x1];
242 u8 inner_dip[0x1];
243 u8 inner_frag[0x1];
244 u8 inner_ip_protocol[0x1];
245 u8 inner_ip_ecn[0x1];
246 u8 inner_ip_dscp[0x1];
247 u8 inner_udp_sport[0x1];
248 u8 inner_udp_dport[0x1];
249 u8 inner_tcp_sport[0x1];
250 u8 inner_tcp_dport[0x1];
251 u8 inner_tcp_flags[0x1];
252 u8 reserved_7[0x9];
253
254 u8 reserved_8[0x40];
255};
256
257struct mlx5_ifc_flow_table_prop_layout_bits {
258 u8 ft_support[0x1];
259 u8 reserved_0[0x1f];
260
261 u8 reserved_1[0x2];
262 u8 log_max_ft_size[0x6];
263 u8 reserved_2[0x10];
264 u8 max_ft_level[0x8];
265
266 u8 reserved_3[0x20];
267
268 u8 reserved_4[0x18];
269 u8 log_max_ft_num[0x8];
270
271 u8 reserved_5[0x18];
272 u8 log_max_destination[0x8];
273
274 u8 reserved_6[0x18];
275 u8 log_max_flow[0x8];
276
277 u8 reserved_7[0x40];
278
279 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
280
281 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
282};
283
284struct mlx5_ifc_odp_per_transport_service_cap_bits {
285 u8 send[0x1];
286 u8 receive[0x1];
287 u8 write[0x1];
288 u8 read[0x1];
289 u8 reserved_0[0x1];
290 u8 srq_receive[0x1];
291 u8 reserved_1[0x1a];
292};
293
294struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
295 u8 smac_47_16[0x20];
296
297 u8 smac_15_0[0x10];
298 u8 ethertype[0x10];
299
300 u8 dmac_47_16[0x20];
301
302 u8 dmac_15_0[0x10];
303 u8 first_prio[0x3];
304 u8 first_cfi[0x1];
305 u8 first_vid[0xc];
306
307 u8 ip_protocol[0x8];
308 u8 ip_dscp[0x6];
309 u8 ip_ecn[0x2];
310 u8 vlan_tag[0x1];
311 u8 reserved_0[0x1];
312 u8 frag[0x1];
313 u8 reserved_1[0x4];
314 u8 tcp_flags[0x9];
315
316 u8 tcp_sport[0x10];
317 u8 tcp_dport[0x10];
318
319 u8 reserved_2[0x20];
320
321 u8 udp_sport[0x10];
322 u8 udp_dport[0x10];
323
324 u8 src_ip[4][0x20];
325
326 u8 dst_ip[4][0x20];
327};
328
329struct mlx5_ifc_fte_match_set_misc_bits {
330 u8 reserved_0[0x20];
331
332 u8 reserved_1[0x10];
333 u8 source_port[0x10];
334
335 u8 outer_second_prio[0x3];
336 u8 outer_second_cfi[0x1];
337 u8 outer_second_vid[0xc];
338 u8 inner_second_prio[0x3];
339 u8 inner_second_cfi[0x1];
340 u8 inner_second_vid[0xc];
341
342 u8 outer_second_vlan_tag[0x1];
343 u8 inner_second_vlan_tag[0x1];
344 u8 reserved_2[0xe];
345 u8 gre_protocol[0x10];
346
347 u8 gre_key_h[0x18];
348 u8 gre_key_l[0x8];
349
350 u8 vxlan_vni[0x18];
351 u8 reserved_3[0x8];
352
353 u8 reserved_4[0x20];
354
355 u8 reserved_5[0xc];
356 u8 outer_ipv6_flow_label[0x14];
357
358 u8 reserved_6[0xc];
359 u8 inner_ipv6_flow_label[0x14];
360
361 u8 reserved_7[0xe0];
362};
363
364struct mlx5_ifc_cmd_pas_bits {
365 u8 pa_h[0x20];
366
367 u8 pa_l[0x14];
368 u8 reserved_0[0xc];
369};
370
371struct mlx5_ifc_uint64_bits {
372 u8 hi[0x20];
373
374 u8 lo[0x20];
375};
376
377enum {
378 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
379 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
380 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
381 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
382 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
383 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
384 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
385 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
386 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
387 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
388};
389
390struct mlx5_ifc_ads_bits {
391 u8 fl[0x1];
392 u8 free_ar[0x1];
393 u8 reserved_0[0xe];
394 u8 pkey_index[0x10];
395
396 u8 reserved_1[0x8];
397 u8 grh[0x1];
398 u8 mlid[0x7];
399 u8 rlid[0x10];
400
401 u8 ack_timeout[0x5];
402 u8 reserved_2[0x3];
403 u8 src_addr_index[0x8];
404 u8 reserved_3[0x4];
405 u8 stat_rate[0x4];
406 u8 hop_limit[0x8];
407
408 u8 reserved_4[0x4];
409 u8 tclass[0x8];
410 u8 flow_label[0x14];
411
412 u8 rgid_rip[16][0x8];
413
414 u8 reserved_5[0x4];
415 u8 f_dscp[0x1];
416 u8 f_ecn[0x1];
417 u8 reserved_6[0x1];
418 u8 f_eth_prio[0x1];
419 u8 ecn[0x2];
420 u8 dscp[0x6];
421 u8 udp_sport[0x10];
422
423 u8 dei_cfi[0x1];
424 u8 eth_prio[0x3];
425 u8 sl[0x4];
426 u8 port[0x8];
427 u8 rmac_47_32[0x10];
428
429 u8 rmac_31_0[0x20];
430};
431
432struct mlx5_ifc_flow_table_nic_cap_bits {
433 u8 reserved_0[0x200];
434
435 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
436
437 u8 reserved_1[0x200];
438
439 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
440
441 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
442
443 u8 reserved_2[0x200];
444
445 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
446
447 u8 reserved_3[0x7200];
448};
449
Saeed Mahameed495716b2015-12-01 18:03:19 +0200[diff] [blame^]450struct mlx5_ifc_flow_table_eswitch_cap_bits {
451 u8 reserved_0[0x200];
452
453 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
454
455 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
456
457 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
458
459 u8 reserved_1[0x7800];
460};
461
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]462struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
463 u8 csum_cap[0x1];
464 u8 vlan_cap[0x1];
465 u8 lro_cap[0x1];
466 u8 lro_psh_flag[0x1];
467 u8 lro_time_stamp[0x1];
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]468 u8 reserved_0[0x3];
469 u8 self_lb_en_modifiable[0x1];
470 u8 reserved_1[0x2];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]471 u8 max_lso_cap[0x5];
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]472 u8 reserved_2[0x4];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]473 u8 rss_ind_tbl_cap[0x4];
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]474 u8 reserved_3[0x3];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]475 u8 tunnel_lso_const_out_ip_id[0x1];
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]476 u8 reserved_4[0x2];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]477 u8 tunnel_statless_gre[0x1];
478 u8 tunnel_stateless_vxlan[0x1];
479
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]480 u8 reserved_5[0x20];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]481
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]482 u8 reserved_6[0x10];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]483 u8 lro_min_mss_size[0x10];
484
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]485 u8 reserved_7[0x120];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]486
487 u8 lro_timer_supported_periods[4][0x20];
488
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]489 u8 reserved_8[0x600];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]490};
491
492struct mlx5_ifc_roce_cap_bits {
493 u8 roce_apm[0x1];
494 u8 reserved_0[0x1f];
495
496 u8 reserved_1[0x60];
497
498 u8 reserved_2[0xc];
499 u8 l3_type[0x4];
500 u8 reserved_3[0x8];
501 u8 roce_version[0x8];
502
503 u8 reserved_4[0x10];
504 u8 r_roce_dest_udp_port[0x10];
505
506 u8 r_roce_max_src_udp_port[0x10];
507 u8 r_roce_min_src_udp_port[0x10];
508
509 u8 reserved_5[0x10];
510 u8 roce_address_table_size[0x10];
511
512 u8 reserved_6[0x700];
513};
514
515enum {
516 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
517 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
518 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
519 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
520 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
521 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
522 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
523 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
524 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
525};
526
527enum {
528 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
529 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
530 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
531 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
532 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
533 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
534 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
535 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
536 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
537};
538
539struct mlx5_ifc_atomic_caps_bits {
540 u8 reserved_0[0x40];
541
542 u8 atomic_req_endianness[0x1];
543 u8 reserved_1[0x1f];
544
545 u8 reserved_2[0x20];
546
547 u8 reserved_3[0x10];
548 u8 atomic_operations[0x10];
549
550 u8 reserved_4[0x10];
551 u8 atomic_size_qp[0x10];
552
553 u8 reserved_5[0x10];
554 u8 atomic_size_dc[0x10];
555
556 u8 reserved_6[0x720];
557};
558
559struct mlx5_ifc_odp_cap_bits {
560 u8 reserved_0[0x40];
561
562 u8 sig[0x1];
563 u8 reserved_1[0x1f];
564
565 u8 reserved_2[0x20];
566
567 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
568
569 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
570
571 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
572
573 u8 reserved_3[0x720];
574};
575
576enum {
577 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
578 MLX5_WQ_TYPE_CYCLIC = 0x1,
579 MLX5_WQ_TYPE_STRQ = 0x2,
580};
581
582enum {
583 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
584 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
585};
586
587enum {
588 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
589 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
590 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
591 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
592 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
593};
594
595enum {
596 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
597 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
598 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
599 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
600 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
601 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
602};
603
604enum {
605 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
606 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
607};
608
609enum {
610 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
611 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
612 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
613};
614
615enum {
616 MLX5_CAP_PORT_TYPE_IB = 0x0,
617 MLX5_CAP_PORT_TYPE_ETH = 0x1,
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]618};
619
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]620struct mlx5_ifc_cmd_hca_cap_bits {
621 u8 reserved_0[0x80];
622
623 u8 log_max_srq_sz[0x8];
624 u8 log_max_qp_sz[0x8];
625 u8 reserved_1[0xb];
626 u8 log_max_qp[0x5];
627
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]628 u8 reserved_2[0xb];
629 u8 log_max_srq[0x5];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]630 u8 reserved_3[0x10];
631
632 u8 reserved_4[0x8];
633 u8 log_max_cq_sz[0x8];
634 u8 reserved_5[0xb];
635 u8 log_max_cq[0x5];
636
637 u8 log_max_eq_sz[0x8];
638 u8 reserved_6[0x2];
639 u8 log_max_mkey[0x6];
640 u8 reserved_7[0xc];
641 u8 log_max_eq[0x4];
642
643 u8 max_indirection[0x8];
644 u8 reserved_8[0x1];
645 u8 log_max_mrw_sz[0x7];
646 u8 reserved_9[0x2];
647 u8 log_max_bsf_list_size[0x6];
648 u8 reserved_10[0x2];
649 u8 log_max_klm_list_size[0x6];
650
651 u8 reserved_11[0xa];
652 u8 log_max_ra_req_dc[0x6];
653 u8 reserved_12[0xa];
654 u8 log_max_ra_res_dc[0x6];
655
656 u8 reserved_13[0xa];
657 u8 log_max_ra_req_qp[0x6];
658 u8 reserved_14[0xa];
659 u8 log_max_ra_res_qp[0x6];
660
661 u8 pad_cap[0x1];
662 u8 cc_query_allowed[0x1];
663 u8 cc_modify_allowed[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]664 u8 reserved_15[0xd];
665 u8 gid_table_size[0x10];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]666
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]667 u8 out_of_seq_cnt[0x1];
668 u8 vport_counters[0x1];
669 u8 reserved_16[0x4];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]670 u8 max_qp_cnt[0xa];
671 u8 pkey_table_size[0x10];
672
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]673 u8 vport_group_manager[0x1];
674 u8 vhca_group_manager[0x1];
675 u8 ib_virt[0x1];
676 u8 eth_virt[0x1];
677 u8 reserved_17[0x1];
678 u8 ets[0x1];
679 u8 nic_flow_table[0x1];
Saeed Mahameed54f0a412015-12-01 18:03:10 +0200[diff] [blame]680 u8 eswitch_flow_table[0x1];
Eli Cohenfc50db92015-12-01 18:03:09 +0200[diff] [blame]681 u8 early_vf_enable;
682 u8 reserved_18[0x2];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]683 u8 local_ca_ack_delay[0x5];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]684 u8 reserved_19[0x6];
685 u8 port_type[0x2];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]686 u8 num_ports[0x8];
687
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]688 u8 reserved_20[0x3];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]689 u8 log_max_msg[0x5];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]690 u8 reserved_21[0x18];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]691
692 u8 stat_rate_support[0x10];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]693 u8 reserved_22[0xc];
694 u8 cqe_version[0x4];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]695
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]696 u8 compact_address_vector[0x1];
697 u8 reserved_23[0xe];
698 u8 drain_sigerr[0x1];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]699 u8 cmdif_checksum[0x2];
700 u8 sigerr_cqe[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]701 u8 reserved_24[0x1];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]702 u8 wq_signature[0x1];
703 u8 sctr_data_cqe[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]704 u8 reserved_25[0x1];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]705 u8 sho[0x1];
706 u8 tph[0x1];
707 u8 rf[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]708 u8 dct[0x1];
709 u8 reserved_26[0x1];
710 u8 eth_net_offloads[0x1];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]711 u8 roce[0x1];
712 u8 atomic[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]713 u8 reserved_27[0x1];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]714
715 u8 cq_oi[0x1];
716 u8 cq_resize[0x1];
717 u8 cq_moderation[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]718 u8 reserved_28[0x3];
719 u8 cq_eq_remap[0x1];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]720 u8 pg[0x1];
721 u8 block_lb_mc[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]722 u8 reserved_29[0x1];
723 u8 scqe_break_moderation[0x1];
724 u8 reserved_30[0x1];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]725 u8 cd[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]726 u8 reserved_31[0x1];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]727 u8 apm[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]728 u8 reserved_32[0x7];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]729 u8 qkv[0x1];
730 u8 pkv[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]731 u8 reserved_33[0x4];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]732 u8 xrc[0x1];
733 u8 ud[0x1];
734 u8 uc[0x1];
735 u8 rc[0x1];
736
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]737 u8 reserved_34[0xa];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]738 u8 uar_sz[0x6];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]739 u8 reserved_35[0x8];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]740 u8 log_pg_sz[0x8];
741
742 u8 bf[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]743 u8 reserved_36[0x1];
744 u8 pad_tx_eth_packet[0x1];
745 u8 reserved_37[0x8];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]746 u8 log_bf_reg_size[0x5];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]747 u8 reserved_38[0x10];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]748
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]749 u8 reserved_39[0x10];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]750 u8 max_wqe_sz_sq[0x10];
751
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]752 u8 reserved_40[0x10];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]753 u8 max_wqe_sz_rq[0x10];
754
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]755 u8 reserved_41[0x10];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]756 u8 max_wqe_sz_sq_dc[0x10];
757
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]758 u8 reserved_42[0x7];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]759 u8 max_qp_mcg[0x19];
760
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]761 u8 reserved_43[0x18];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]762 u8 log_max_mcg[0x8];
763
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]764 u8 reserved_44[0x3];
765 u8 log_max_transport_domain[0x5];
766 u8 reserved_45[0x3];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]767 u8 log_max_pd[0x5];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]768 u8 reserved_46[0xb];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]769 u8 log_max_xrcd[0x5];
770
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]771 u8 reserved_47[0x20];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]772
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]773 u8 reserved_48[0x3];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]774 u8 log_max_rq[0x5];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]775 u8 reserved_49[0x3];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]776 u8 log_max_sq[0x5];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]777 u8 reserved_50[0x3];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]778 u8 log_max_tir[0x5];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]779 u8 reserved_51[0x3];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]780 u8 log_max_tis[0x5];
781
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]782 u8 basic_cyclic_rcv_wqe[0x1];
783 u8 reserved_52[0x2];
784 u8 log_max_rmp[0x5];
785 u8 reserved_53[0x3];
786 u8 log_max_rqt[0x5];
787 u8 reserved_54[0x3];
788 u8 log_max_rqt_size[0x5];
789 u8 reserved_55[0x3];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]790 u8 log_max_tis_per_sq[0x5];
791
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]792 u8 reserved_56[0x3];
793 u8 log_max_stride_sz_rq[0x5];
794 u8 reserved_57[0x3];
795 u8 log_min_stride_sz_rq[0x5];
796 u8 reserved_58[0x3];
797 u8 log_max_stride_sz_sq[0x5];
798 u8 reserved_59[0x3];
799 u8 log_min_stride_sz_sq[0x5];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]800
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]801 u8 reserved_60[0x1b];
802 u8 log_max_wq_sz[0x5];
803
Saeed Mahameed54f0a412015-12-01 18:03:10 +0200[diff] [blame]804 u8 nic_vport_change_event[0x1];
805 u8 reserved_61[0xa];
806 u8 log_max_vlan_list[0x5];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]807 u8 reserved_62[0x3];
Saeed Mahameed54f0a412015-12-01 18:03:10 +0200[diff] [blame]808 u8 log_max_current_mc_list[0x5];
809 u8 reserved_63[0x3];
810 u8 log_max_current_uc_list[0x5];
811
812 u8 reserved_64[0x80];
813
814 u8 reserved_65[0x3];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]815 u8 log_max_l2_table[0x5];
Saeed Mahameed54f0a412015-12-01 18:03:10 +0200[diff] [blame]816 u8 reserved_66[0x8];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]817 u8 log_uar_page_sz[0x10];
818
Saeed Mahameed54f0a412015-12-01 18:03:10 +0200[diff] [blame]819 u8 reserved_67[0xe0];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]820
Saeed Mahameed54f0a412015-12-01 18:03:10 +0200[diff] [blame]821 u8 reserved_68[0x1f];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]822 u8 cqe_zip[0x1];
823
824 u8 cqe_zip_timeout[0x10];
825 u8 cqe_zip_max_num[0x10];
826
Saeed Mahameed54f0a412015-12-01 18:03:10 +0200[diff] [blame]827 u8 reserved_69[0x220];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]828};
829
830enum {
831 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_FLOW_TABLE_ = 0x1,
832 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_TIR = 0x2,
833};
834
835struct mlx5_ifc_dest_format_struct_bits {
836 u8 destination_type[0x8];
837 u8 destination_id[0x18];
838
839 u8 reserved_0[0x20];
840};
841
842struct mlx5_ifc_fte_match_param_bits {
843 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
844
845 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
846
847 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
848
849 u8 reserved_0[0xa00];
850};
851
852enum {
853 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
854 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
855 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
856 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
857 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
858};
859
860struct mlx5_ifc_rx_hash_field_select_bits {
861 u8 l3_prot_type[0x1];
862 u8 l4_prot_type[0x1];
863 u8 selected_fields[0x1e];
864};
865
866enum {
867 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
868 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
869};
870
871enum {
872 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
873 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
874};
875
876struct mlx5_ifc_wq_bits {
877 u8 wq_type[0x4];
878 u8 wq_signature[0x1];
879 u8 end_padding_mode[0x2];
880 u8 cd_slave[0x1];
881 u8 reserved_0[0x18];
882
883 u8 hds_skip_first_sge[0x1];
884 u8 log2_hds_buf_size[0x3];
885 u8 reserved_1[0x7];
886 u8 page_offset[0x5];
887 u8 lwm[0x10];
888
889 u8 reserved_2[0x8];
890 u8 pd[0x18];
891
892 u8 reserved_3[0x8];
893 u8 uar_page[0x18];
894
895 u8 dbr_addr[0x40];
896
897 u8 hw_counter[0x20];
898
899 u8 sw_counter[0x20];
900
901 u8 reserved_4[0xc];
902 u8 log_wq_stride[0x4];
903 u8 reserved_5[0x3];
904 u8 log_wq_pg_sz[0x5];
905 u8 reserved_6[0x3];
906 u8 log_wq_sz[0x5];
907
908 u8 reserved_7[0x4e0];
909
910 struct mlx5_ifc_cmd_pas_bits pas[0];
911};
912
913struct mlx5_ifc_rq_num_bits {
914 u8 reserved_0[0x8];
915 u8 rq_num[0x18];
916};
917
918struct mlx5_ifc_mac_address_layout_bits {
919 u8 reserved_0[0x10];
920 u8 mac_addr_47_32[0x10];
921
922 u8 mac_addr_31_0[0x20];
923};
924
Saeed Mahameedc0046cf2015-12-01 18:03:15 +0200[diff] [blame]925struct mlx5_ifc_vlan_layout_bits {
926 u8 reserved_0[0x14];
927 u8 vlan[0x0c];
928
929 u8 reserved_1[0x20];
930};
931
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]932struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
933 u8 reserved_0[0xa0];
934
935 u8 min_time_between_cnps[0x20];
936
937 u8 reserved_1[0x12];
938 u8 cnp_dscp[0x6];
939 u8 reserved_2[0x5];
940 u8 cnp_802p_prio[0x3];
941
942 u8 reserved_3[0x720];
943};
944
945struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
946 u8 reserved_0[0x60];
947
948 u8 reserved_1[0x4];
949 u8 clamp_tgt_rate[0x1];
950 u8 reserved_2[0x3];
951 u8 clamp_tgt_rate_after_time_inc[0x1];
952 u8 reserved_3[0x17];
953
954 u8 reserved_4[0x20];
955
956 u8 rpg_time_reset[0x20];
957
958 u8 rpg_byte_reset[0x20];
959
960 u8 rpg_threshold[0x20];
961
962 u8 rpg_max_rate[0x20];
963
964 u8 rpg_ai_rate[0x20];
965
966 u8 rpg_hai_rate[0x20];
967
968 u8 rpg_gd[0x20];
969
970 u8 rpg_min_dec_fac[0x20];
971
972 u8 rpg_min_rate[0x20];
973
974 u8 reserved_5[0xe0];
975
976 u8 rate_to_set_on_first_cnp[0x20];
977
978 u8 dce_tcp_g[0x20];
979
980 u8 dce_tcp_rtt[0x20];
981
982 u8 rate_reduce_monitor_period[0x20];
983
984 u8 reserved_6[0x20];
985
986 u8 initial_alpha_value[0x20];
987
988 u8 reserved_7[0x4a0];
989};
990
991struct mlx5_ifc_cong_control_802_1qau_rp_bits {
992 u8 reserved_0[0x80];
993
994 u8 rppp_max_rps[0x20];
995
996 u8 rpg_time_reset[0x20];
997
998 u8 rpg_byte_reset[0x20];
999
1000 u8 rpg_threshold[0x20];
1001
1002 u8 rpg_max_rate[0x20];
1003
1004 u8 rpg_ai_rate[0x20];
1005
1006 u8 rpg_hai_rate[0x20];
1007
1008 u8 rpg_gd[0x20];
1009
1010 u8 rpg_min_dec_fac[0x20];
1011
1012 u8 rpg_min_rate[0x20];
1013
1014 u8 reserved_1[0x640];
1015};
1016
1017enum {
1018 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1019 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1020 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1021};
1022
1023struct mlx5_ifc_resize_field_select_bits {
1024 u8 resize_field_select[0x20];
1025};
1026
1027enum {
1028 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1029 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1030 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1031 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1032};
1033
1034struct mlx5_ifc_modify_field_select_bits {
1035 u8 modify_field_select[0x20];
1036};
1037
1038struct mlx5_ifc_field_select_r_roce_np_bits {
1039 u8 field_select_r_roce_np[0x20];
1040};
1041
1042struct mlx5_ifc_field_select_r_roce_rp_bits {
1043 u8 field_select_r_roce_rp[0x20];
1044};
1045
1046enum {
1047 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1048 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1049 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1050 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1051 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1052 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1053 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1054 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1055 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1056 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1057};
1058
1059struct mlx5_ifc_field_select_802_1qau_rp_bits {
1060 u8 field_select_8021qaurp[0x20];
1061};
1062
1063struct mlx5_ifc_phys_layer_cntrs_bits {
1064 u8 time_since_last_clear_high[0x20];
1065
1066 u8 time_since_last_clear_low[0x20];
1067
1068 u8 symbol_errors_high[0x20];
1069
1070 u8 symbol_errors_low[0x20];
1071
1072 u8 sync_headers_errors_high[0x20];
1073
1074 u8 sync_headers_errors_low[0x20];
1075
1076 u8 edpl_bip_errors_lane0_high[0x20];
1077
1078 u8 edpl_bip_errors_lane0_low[0x20];
1079
1080 u8 edpl_bip_errors_lane1_high[0x20];
1081
1082 u8 edpl_bip_errors_lane1_low[0x20];
1083
1084 u8 edpl_bip_errors_lane2_high[0x20];
1085
1086 u8 edpl_bip_errors_lane2_low[0x20];
1087
1088 u8 edpl_bip_errors_lane3_high[0x20];
1089
1090 u8 edpl_bip_errors_lane3_low[0x20];
1091
1092 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1093
1094 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1095
1096 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1097
1098 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1099
1100 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1101
1102 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1103
1104 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1105
1106 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1107
1108 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1109
1110 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1111
1112 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1113
1114 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1115
1116 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1117
1118 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1119
1120 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1121
1122 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1123
1124 u8 rs_fec_corrected_blocks_high[0x20];
1125
1126 u8 rs_fec_corrected_blocks_low[0x20];
1127
1128 u8 rs_fec_uncorrectable_blocks_high[0x20];
1129
1130 u8 rs_fec_uncorrectable_blocks_low[0x20];
1131
1132 u8 rs_fec_no_errors_blocks_high[0x20];
1133
1134 u8 rs_fec_no_errors_blocks_low[0x20];
1135
1136 u8 rs_fec_single_error_blocks_high[0x20];
1137
1138 u8 rs_fec_single_error_blocks_low[0x20];
1139
1140 u8 rs_fec_corrected_symbols_total_high[0x20];
1141
1142 u8 rs_fec_corrected_symbols_total_low[0x20];
1143
1144 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1145
1146 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1147
1148 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1149
1150 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1151
1152 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1153
1154 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1155
1156 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1157
1158 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1159
1160 u8 link_down_events[0x20];
1161
1162 u8 successful_recovery_events[0x20];
1163
1164 u8 reserved_0[0x180];
1165};
1166
1167struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1168 u8 transmit_queue_high[0x20];
1169
1170 u8 transmit_queue_low[0x20];
1171
1172 u8 reserved_0[0x780];
1173};
1174
1175struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1176 u8 rx_octets_high[0x20];
1177
1178 u8 rx_octets_low[0x20];
1179
1180 u8 reserved_0[0xc0];
1181
1182 u8 rx_frames_high[0x20];
1183
1184 u8 rx_frames_low[0x20];
1185
1186 u8 tx_octets_high[0x20];
1187
1188 u8 tx_octets_low[0x20];
1189
1190 u8 reserved_1[0xc0];
1191
1192 u8 tx_frames_high[0x20];
1193
1194 u8 tx_frames_low[0x20];
1195
1196 u8 rx_pause_high[0x20];
1197
1198 u8 rx_pause_low[0x20];
1199
1200 u8 rx_pause_duration_high[0x20];
1201
1202 u8 rx_pause_duration_low[0x20];
1203
1204 u8 tx_pause_high[0x20];
1205
1206 u8 tx_pause_low[0x20];
1207
1208 u8 tx_pause_duration_high[0x20];
1209
1210 u8 tx_pause_duration_low[0x20];
1211
1212 u8 rx_pause_transition_high[0x20];
1213
1214 u8 rx_pause_transition_low[0x20];
1215
1216 u8 reserved_2[0x400];
1217};
1218
1219struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1220 u8 port_transmit_wait_high[0x20];
1221
1222 u8 port_transmit_wait_low[0x20];
1223
1224 u8 reserved_0[0x780];
1225};
1226
1227struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1228 u8 dot3stats_alignment_errors_high[0x20];
1229
1230 u8 dot3stats_alignment_errors_low[0x20];
1231
1232 u8 dot3stats_fcs_errors_high[0x20];
1233
1234 u8 dot3stats_fcs_errors_low[0x20];
1235
1236 u8 dot3stats_single_collision_frames_high[0x20];
1237
1238 u8 dot3stats_single_collision_frames_low[0x20];
1239
1240 u8 dot3stats_multiple_collision_frames_high[0x20];
1241
1242 u8 dot3stats_multiple_collision_frames_low[0x20];
1243
1244 u8 dot3stats_sqe_test_errors_high[0x20];
1245
1246 u8 dot3stats_sqe_test_errors_low[0x20];
1247
1248 u8 dot3stats_deferred_transmissions_high[0x20];
1249
1250 u8 dot3stats_deferred_transmissions_low[0x20];
1251
1252 u8 dot3stats_late_collisions_high[0x20];
1253
1254 u8 dot3stats_late_collisions_low[0x20];
1255
1256 u8 dot3stats_excessive_collisions_high[0x20];
1257
1258 u8 dot3stats_excessive_collisions_low[0x20];
1259
1260 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1261
1262 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1263
1264 u8 dot3stats_carrier_sense_errors_high[0x20];
1265
1266 u8 dot3stats_carrier_sense_errors_low[0x20];
1267
1268 u8 dot3stats_frame_too_longs_high[0x20];
1269
1270 u8 dot3stats_frame_too_longs_low[0x20];
1271
1272 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1273
1274 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1275
1276 u8 dot3stats_symbol_errors_high[0x20];
1277
1278 u8 dot3stats_symbol_errors_low[0x20];
1279
1280 u8 dot3control_in_unknown_opcodes_high[0x20];
1281
1282 u8 dot3control_in_unknown_opcodes_low[0x20];
1283
1284 u8 dot3in_pause_frames_high[0x20];
1285
1286 u8 dot3in_pause_frames_low[0x20];
1287
1288 u8 dot3out_pause_frames_high[0x20];
1289
1290 u8 dot3out_pause_frames_low[0x20];
1291
1292 u8 reserved_0[0x3c0];
1293};
1294
1295struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1296 u8 ether_stats_drop_events_high[0x20];
1297
1298 u8 ether_stats_drop_events_low[0x20];
1299
1300 u8 ether_stats_octets_high[0x20];
1301
1302 u8 ether_stats_octets_low[0x20];
1303
1304 u8 ether_stats_pkts_high[0x20];
1305
1306 u8 ether_stats_pkts_low[0x20];
1307
1308 u8 ether_stats_broadcast_pkts_high[0x20];
1309
1310 u8 ether_stats_broadcast_pkts_low[0x20];
1311
1312 u8 ether_stats_multicast_pkts_high[0x20];
1313
1314 u8 ether_stats_multicast_pkts_low[0x20];
1315
1316 u8 ether_stats_crc_align_errors_high[0x20];
1317
1318 u8 ether_stats_crc_align_errors_low[0x20];
1319
1320 u8 ether_stats_undersize_pkts_high[0x20];
1321
1322 u8 ether_stats_undersize_pkts_low[0x20];
1323
1324 u8 ether_stats_oversize_pkts_high[0x20];
1325
1326 u8 ether_stats_oversize_pkts_low[0x20];
1327
1328 u8 ether_stats_fragments_high[0x20];
1329
1330 u8 ether_stats_fragments_low[0x20];
1331
1332 u8 ether_stats_jabbers_high[0x20];
1333
1334 u8 ether_stats_jabbers_low[0x20];
1335
1336 u8 ether_stats_collisions_high[0x20];
1337
1338 u8 ether_stats_collisions_low[0x20];
1339
1340 u8 ether_stats_pkts64octets_high[0x20];
1341
1342 u8 ether_stats_pkts64octets_low[0x20];
1343
1344 u8 ether_stats_pkts65to127octets_high[0x20];
1345
1346 u8 ether_stats_pkts65to127octets_low[0x20];
1347
1348 u8 ether_stats_pkts128to255octets_high[0x20];
1349
1350 u8 ether_stats_pkts128to255octets_low[0x20];
1351
1352 u8 ether_stats_pkts256to511octets_high[0x20];
1353
1354 u8 ether_stats_pkts256to511octets_low[0x20];
1355
1356 u8 ether_stats_pkts512to1023octets_high[0x20];
1357
1358 u8 ether_stats_pkts512to1023octets_low[0x20];
1359
1360 u8 ether_stats_pkts1024to1518octets_high[0x20];
1361
1362 u8 ether_stats_pkts1024to1518octets_low[0x20];
1363
1364 u8 ether_stats_pkts1519to2047octets_high[0x20];
1365
1366 u8 ether_stats_pkts1519to2047octets_low[0x20];
1367
1368 u8 ether_stats_pkts2048to4095octets_high[0x20];
1369
1370 u8 ether_stats_pkts2048to4095octets_low[0x20];
1371
1372 u8 ether_stats_pkts4096to8191octets_high[0x20];
1373
1374 u8 ether_stats_pkts4096to8191octets_low[0x20];
1375
1376 u8 ether_stats_pkts8192to10239octets_high[0x20];
1377
1378 u8 ether_stats_pkts8192to10239octets_low[0x20];
1379
1380 u8 reserved_0[0x280];
1381};
1382
1383struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1384 u8 if_in_octets_high[0x20];
1385
1386 u8 if_in_octets_low[0x20];
1387
1388 u8 if_in_ucast_pkts_high[0x20];
1389
1390 u8 if_in_ucast_pkts_low[0x20];
1391
1392 u8 if_in_discards_high[0x20];
1393
1394 u8 if_in_discards_low[0x20];
1395
1396 u8 if_in_errors_high[0x20];
1397
1398 u8 if_in_errors_low[0x20];
1399
1400 u8 if_in_unknown_protos_high[0x20];
1401
1402 u8 if_in_unknown_protos_low[0x20];
1403
1404 u8 if_out_octets_high[0x20];
1405
1406 u8 if_out_octets_low[0x20];
1407
1408 u8 if_out_ucast_pkts_high[0x20];
1409
1410 u8 if_out_ucast_pkts_low[0x20];
1411
1412 u8 if_out_discards_high[0x20];
1413
1414 u8 if_out_discards_low[0x20];
1415
1416 u8 if_out_errors_high[0x20];
1417
1418 u8 if_out_errors_low[0x20];
1419
1420 u8 if_in_multicast_pkts_high[0x20];
1421
1422 u8 if_in_multicast_pkts_low[0x20];
1423
1424 u8 if_in_broadcast_pkts_high[0x20];
1425
1426 u8 if_in_broadcast_pkts_low[0x20];
1427
1428 u8 if_out_multicast_pkts_high[0x20];
1429
1430 u8 if_out_multicast_pkts_low[0x20];
1431
1432 u8 if_out_broadcast_pkts_high[0x20];
1433
1434 u8 if_out_broadcast_pkts_low[0x20];
1435
1436 u8 reserved_0[0x480];
1437};
1438
1439struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1440 u8 a_frames_transmitted_ok_high[0x20];
1441
1442 u8 a_frames_transmitted_ok_low[0x20];
1443
1444 u8 a_frames_received_ok_high[0x20];
1445
1446 u8 a_frames_received_ok_low[0x20];
1447
1448 u8 a_frame_check_sequence_errors_high[0x20];
1449
1450 u8 a_frame_check_sequence_errors_low[0x20];
1451
1452 u8 a_alignment_errors_high[0x20];
1453
1454 u8 a_alignment_errors_low[0x20];
1455
1456 u8 a_octets_transmitted_ok_high[0x20];
1457
1458 u8 a_octets_transmitted_ok_low[0x20];
1459
1460 u8 a_octets_received_ok_high[0x20];
1461
1462 u8 a_octets_received_ok_low[0x20];
1463
1464 u8 a_multicast_frames_xmitted_ok_high[0x20];
1465
1466 u8 a_multicast_frames_xmitted_ok_low[0x20];
1467
1468 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1469
1470 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1471
1472 u8 a_multicast_frames_received_ok_high[0x20];
1473
1474 u8 a_multicast_frames_received_ok_low[0x20];
1475
1476 u8 a_broadcast_frames_received_ok_high[0x20];
1477
1478 u8 a_broadcast_frames_received_ok_low[0x20];
1479
1480 u8 a_in_range_length_errors_high[0x20];
1481
1482 u8 a_in_range_length_errors_low[0x20];
1483
1484 u8 a_out_of_range_length_field_high[0x20];
1485
1486 u8 a_out_of_range_length_field_low[0x20];
1487
1488 u8 a_frame_too_long_errors_high[0x20];
1489
1490 u8 a_frame_too_long_errors_low[0x20];
1491
1492 u8 a_symbol_error_during_carrier_high[0x20];
1493
1494 u8 a_symbol_error_during_carrier_low[0x20];
1495
1496 u8 a_mac_control_frames_transmitted_high[0x20];
1497
1498 u8 a_mac_control_frames_transmitted_low[0x20];
1499
1500 u8 a_mac_control_frames_received_high[0x20];
1501
1502 u8 a_mac_control_frames_received_low[0x20];
1503
1504 u8 a_unsupported_opcodes_received_high[0x20];
1505
1506 u8 a_unsupported_opcodes_received_low[0x20];
1507
1508 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1509
1510 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1511
1512 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1513
1514 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1515
1516 u8 reserved_0[0x300];
1517};
1518
1519struct mlx5_ifc_cmd_inter_comp_event_bits {
1520 u8 command_completion_vector[0x20];
1521
1522 u8 reserved_0[0xc0];
1523};
1524
1525struct mlx5_ifc_stall_vl_event_bits {
1526 u8 reserved_0[0x18];
1527 u8 port_num[0x1];
1528 u8 reserved_1[0x3];
1529 u8 vl[0x4];
1530
1531 u8 reserved_2[0xa0];
1532};
1533
1534struct mlx5_ifc_db_bf_congestion_event_bits {
1535 u8 event_subtype[0x8];
1536 u8 reserved_0[0x8];
1537 u8 congestion_level[0x8];
1538 u8 reserved_1[0x8];
1539
1540 u8 reserved_2[0xa0];
1541};
1542
1543struct mlx5_ifc_gpio_event_bits {
1544 u8 reserved_0[0x60];
1545
1546 u8 gpio_event_hi[0x20];
1547
1548 u8 gpio_event_lo[0x20];
1549
1550 u8 reserved_1[0x40];
1551};
1552
1553struct mlx5_ifc_port_state_change_event_bits {
1554 u8 reserved_0[0x40];
1555
1556 u8 port_num[0x4];
1557 u8 reserved_1[0x1c];
1558
1559 u8 reserved_2[0x80];
1560};
1561
1562struct mlx5_ifc_dropped_packet_logged_bits {
1563 u8 reserved_0[0xe0];
1564};
1565
1566enum {
1567 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1568 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1569};
1570
1571struct mlx5_ifc_cq_error_bits {
1572 u8 reserved_0[0x8];
1573 u8 cqn[0x18];
1574
1575 u8 reserved_1[0x20];
1576
1577 u8 reserved_2[0x18];
1578 u8 syndrome[0x8];
1579
1580 u8 reserved_3[0x80];
1581};
1582
1583struct mlx5_ifc_rdma_page_fault_event_bits {
1584 u8 bytes_committed[0x20];
1585
1586 u8 r_key[0x20];
1587
1588 u8 reserved_0[0x10];
1589 u8 packet_len[0x10];
1590
1591 u8 rdma_op_len[0x20];
1592
1593 u8 rdma_va[0x40];
1594
1595 u8 reserved_1[0x5];
1596 u8 rdma[0x1];
1597 u8 write[0x1];
1598 u8 requestor[0x1];
1599 u8 qp_number[0x18];
1600};
1601
1602struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1603 u8 bytes_committed[0x20];
1604
1605 u8 reserved_0[0x10];
1606 u8 wqe_index[0x10];
1607
1608 u8 reserved_1[0x10];
1609 u8 len[0x10];
1610
1611 u8 reserved_2[0x60];
1612
1613 u8 reserved_3[0x5];
1614 u8 rdma[0x1];
1615 u8 write_read[0x1];
1616 u8 requestor[0x1];
1617 u8 qpn[0x18];
1618};
1619
1620struct mlx5_ifc_qp_events_bits {
1621 u8 reserved_0[0xa0];
1622
1623 u8 type[0x8];
1624 u8 reserved_1[0x18];
1625
1626 u8 reserved_2[0x8];
1627 u8 qpn_rqn_sqn[0x18];
1628};
1629
1630struct mlx5_ifc_dct_events_bits {
1631 u8 reserved_0[0xc0];
1632
1633 u8 reserved_1[0x8];
1634 u8 dct_number[0x18];
1635};
1636
1637struct mlx5_ifc_comp_event_bits {
1638 u8 reserved_0[0xc0];
1639
1640 u8 reserved_1[0x8];
1641 u8 cq_number[0x18];
1642};
1643
1644enum {
1645 MLX5_QPC_STATE_RST = 0x0,
1646 MLX5_QPC_STATE_INIT = 0x1,
1647 MLX5_QPC_STATE_RTR = 0x2,
1648 MLX5_QPC_STATE_RTS = 0x3,
1649 MLX5_QPC_STATE_SQER = 0x4,
1650 MLX5_QPC_STATE_ERR = 0x6,
1651 MLX5_QPC_STATE_SQD = 0x7,
1652 MLX5_QPC_STATE_SUSPENDED = 0x9,
1653};
1654
1655enum {
1656 MLX5_QPC_ST_RC = 0x0,
1657 MLX5_QPC_ST_UC = 0x1,
1658 MLX5_QPC_ST_UD = 0x2,
1659 MLX5_QPC_ST_XRC = 0x3,
1660 MLX5_QPC_ST_DCI = 0x5,
1661 MLX5_QPC_ST_QP0 = 0x7,
1662 MLX5_QPC_ST_QP1 = 0x8,
1663 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1664 MLX5_QPC_ST_REG_UMR = 0xc,
1665};
1666
1667enum {
1668 MLX5_QPC_PM_STATE_ARMED = 0x0,
1669 MLX5_QPC_PM_STATE_REARM = 0x1,
1670 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1671 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1672};
1673
1674enum {
1675 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1676 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1677};
1678
1679enum {
1680 MLX5_QPC_MTU_256_BYTES = 0x1,
1681 MLX5_QPC_MTU_512_BYTES = 0x2,
1682 MLX5_QPC_MTU_1K_BYTES = 0x3,
1683 MLX5_QPC_MTU_2K_BYTES = 0x4,
1684 MLX5_QPC_MTU_4K_BYTES = 0x5,
1685 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1686};
1687
1688enum {
1689 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1690 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1691 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1692 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1693 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1694 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1695 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1696 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1697};
1698
1699enum {
1700 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1701 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1702 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1703};
1704
1705enum {
1706 MLX5_QPC_CS_RES_DISABLE = 0x0,
1707 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1708 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1709};
1710
1711struct mlx5_ifc_qpc_bits {
1712 u8 state[0x4];
1713 u8 reserved_0[0x4];
1714 u8 st[0x8];
1715 u8 reserved_1[0x3];
1716 u8 pm_state[0x2];
1717 u8 reserved_2[0x7];
1718 u8 end_padding_mode[0x2];
1719 u8 reserved_3[0x2];
1720
1721 u8 wq_signature[0x1];
1722 u8 block_lb_mc[0x1];
1723 u8 atomic_like_write_en[0x1];
1724 u8 latency_sensitive[0x1];
1725 u8 reserved_4[0x1];
1726 u8 drain_sigerr[0x1];
1727 u8 reserved_5[0x2];
1728 u8 pd[0x18];
1729
1730 u8 mtu[0x3];
1731 u8 log_msg_max[0x5];
1732 u8 reserved_6[0x1];
1733 u8 log_rq_size[0x4];
1734 u8 log_rq_stride[0x3];
1735 u8 no_sq[0x1];
1736 u8 log_sq_size[0x4];
1737 u8 reserved_7[0x6];
1738 u8 rlky[0x1];
1739 u8 reserved_8[0x4];
1740
1741 u8 counter_set_id[0x8];
1742 u8 uar_page[0x18];
1743
1744 u8 reserved_9[0x8];
1745 u8 user_index[0x18];
1746
1747 u8 reserved_10[0x3];
1748 u8 log_page_size[0x5];
1749 u8 remote_qpn[0x18];
1750
1751 struct mlx5_ifc_ads_bits primary_address_path;
1752
1753 struct mlx5_ifc_ads_bits secondary_address_path;
1754
1755 u8 log_ack_req_freq[0x4];
1756 u8 reserved_11[0x4];
1757 u8 log_sra_max[0x3];
1758 u8 reserved_12[0x2];
1759 u8 retry_count[0x3];
1760 u8 rnr_retry[0x3];
1761 u8 reserved_13[0x1];
1762 u8 fre[0x1];
1763 u8 cur_rnr_retry[0x3];
1764 u8 cur_retry_count[0x3];
1765 u8 reserved_14[0x5];
1766
1767 u8 reserved_15[0x20];
1768
1769 u8 reserved_16[0x8];
1770 u8 next_send_psn[0x18];
1771
1772 u8 reserved_17[0x8];
1773 u8 cqn_snd[0x18];
1774
1775 u8 reserved_18[0x40];
1776
1777 u8 reserved_19[0x8];
1778 u8 last_acked_psn[0x18];
1779
1780 u8 reserved_20[0x8];
1781 u8 ssn[0x18];
1782
1783 u8 reserved_21[0x8];
1784 u8 log_rra_max[0x3];
1785 u8 reserved_22[0x1];
1786 u8 atomic_mode[0x4];
1787 u8 rre[0x1];
1788 u8 rwe[0x1];
1789 u8 rae[0x1];
1790 u8 reserved_23[0x1];
1791 u8 page_offset[0x6];
1792 u8 reserved_24[0x3];
1793 u8 cd_slave_receive[0x1];
1794 u8 cd_slave_send[0x1];
1795 u8 cd_master[0x1];
1796
1797 u8 reserved_25[0x3];
1798 u8 min_rnr_nak[0x5];
1799 u8 next_rcv_psn[0x18];
1800
1801 u8 reserved_26[0x8];
1802 u8 xrcd[0x18];
1803
1804 u8 reserved_27[0x8];
1805 u8 cqn_rcv[0x18];
1806
1807 u8 dbr_addr[0x40];
1808
1809 u8 q_key[0x20];
1810
1811 u8 reserved_28[0x5];
1812 u8 rq_type[0x3];
1813 u8 srqn_rmpn[0x18];
1814
1815 u8 reserved_29[0x8];
1816 u8 rmsn[0x18];
1817
1818 u8 hw_sq_wqebb_counter[0x10];
1819 u8 sw_sq_wqebb_counter[0x10];
1820
1821 u8 hw_rq_counter[0x20];
1822
1823 u8 sw_rq_counter[0x20];
1824
1825 u8 reserved_30[0x20];
1826
1827 u8 reserved_31[0xf];
1828 u8 cgs[0x1];
1829 u8 cs_req[0x8];
1830 u8 cs_res[0x8];
1831
1832 u8 dc_access_key[0x40];
1833
1834 u8 reserved_32[0xc0];
1835};
1836
1837struct mlx5_ifc_roce_addr_layout_bits {
1838 u8 source_l3_address[16][0x8];
1839
1840 u8 reserved_0[0x3];
1841 u8 vlan_valid[0x1];
1842 u8 vlan_id[0xc];
1843 u8 source_mac_47_32[0x10];
1844
1845 u8 source_mac_31_0[0x20];
1846
1847 u8 reserved_1[0x14];
1848 u8 roce_l3_type[0x4];
1849 u8 roce_version[0x8];
1850
1851 u8 reserved_2[0x20];
1852};
1853
1854union mlx5_ifc_hca_cap_union_bits {
1855 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1856 struct mlx5_ifc_odp_cap_bits odp_cap;
1857 struct mlx5_ifc_atomic_caps_bits atomic_caps;
1858 struct mlx5_ifc_roce_cap_bits roce_cap;
1859 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1860 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
Saeed Mahameed495716b2015-12-01 18:03:19 +0200[diff] [blame^]1861 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]1862 u8 reserved_0[0x8000];
1863};
1864
1865enum {
1866 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
1867 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
1868 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
1869};
1870
1871struct mlx5_ifc_flow_context_bits {
1872 u8 reserved_0[0x20];
1873
1874 u8 group_id[0x20];
1875
1876 u8 reserved_1[0x8];
1877 u8 flow_tag[0x18];
1878
1879 u8 reserved_2[0x10];
1880 u8 action[0x10];
1881
1882 u8 reserved_3[0x8];
1883 u8 destination_list_size[0x18];
1884
1885 u8 reserved_4[0x160];
1886
1887 struct mlx5_ifc_fte_match_param_bits match_value;
1888
1889 u8 reserved_5[0x600];
1890
1891 struct mlx5_ifc_dest_format_struct_bits destination[0];
1892};
1893
1894enum {
1895 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
1896 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
1897};
1898
1899struct mlx5_ifc_xrc_srqc_bits {
1900 u8 state[0x4];
1901 u8 log_xrc_srq_size[0x4];
1902 u8 reserved_0[0x18];
1903
1904 u8 wq_signature[0x1];
1905 u8 cont_srq[0x1];
1906 u8 reserved_1[0x1];
1907 u8 rlky[0x1];
1908 u8 basic_cyclic_rcv_wqe[0x1];
1909 u8 log_rq_stride[0x3];
1910 u8 xrcd[0x18];
1911
1912 u8 page_offset[0x6];
1913 u8 reserved_2[0x2];
1914 u8 cqn[0x18];
1915
1916 u8 reserved_3[0x20];
1917
1918 u8 user_index_equal_xrc_srqn[0x1];
1919 u8 reserved_4[0x1];
1920 u8 log_page_size[0x6];
1921 u8 user_index[0x18];
1922
1923 u8 reserved_5[0x20];
1924
1925 u8 reserved_6[0x8];
1926 u8 pd[0x18];
1927
1928 u8 lwm[0x10];
1929 u8 wqe_cnt[0x10];
1930
1931 u8 reserved_7[0x40];
1932
1933 u8 db_record_addr_h[0x20];
1934
1935 u8 db_record_addr_l[0x1e];
1936 u8 reserved_8[0x2];
1937
1938 u8 reserved_9[0x80];
1939};
1940
1941struct mlx5_ifc_traffic_counter_bits {
1942 u8 packets[0x40];
1943
1944 u8 octets[0x40];
1945};
1946
1947struct mlx5_ifc_tisc_bits {
1948 u8 reserved_0[0xc];
1949 u8 prio[0x4];
1950 u8 reserved_1[0x10];
1951
1952 u8 reserved_2[0x100];
1953
1954 u8 reserved_3[0x8];
1955 u8 transport_domain[0x18];
1956
1957 u8 reserved_4[0x3c0];
1958};
1959
1960enum {
1961 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1962 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1963};
1964
1965enum {
1966 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1967 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1968};
1969
1970enum {
Saeed Mahameed2be69672015-07-23 23:35:56 +0300[diff] [blame]1971 MLX5_RX_HASH_FN_NONE = 0x0,
1972 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
1973 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]1974};
1975
1976enum {
1977 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
1978 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
1979};
1980
1981struct mlx5_ifc_tirc_bits {
1982 u8 reserved_0[0x20];
1983
1984 u8 disp_type[0x4];
1985 u8 reserved_1[0x1c];
1986
1987 u8 reserved_2[0x40];
1988
1989 u8 reserved_3[0x4];
1990 u8 lro_timeout_period_usecs[0x10];
1991 u8 lro_enable_mask[0x4];
1992 u8 lro_max_ip_payload_size[0x8];
1993
1994 u8 reserved_4[0x40];
1995
1996 u8 reserved_5[0x8];
1997 u8 inline_rqn[0x18];
1998
1999 u8 rx_hash_symmetric[0x1];
2000 u8 reserved_6[0x1];
2001 u8 tunneled_offload_en[0x1];
2002 u8 reserved_7[0x5];
2003 u8 indirect_table[0x18];
2004
2005 u8 rx_hash_fn[0x4];
2006 u8 reserved_8[0x2];
2007 u8 self_lb_block[0x2];
2008 u8 transport_domain[0x18];
2009
2010 u8 rx_hash_toeplitz_key[10][0x20];
2011
2012 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2013
2014 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2015
2016 u8 reserved_9[0x4c0];
2017};
2018
2019enum {
2020 MLX5_SRQC_STATE_GOOD = 0x0,
2021 MLX5_SRQC_STATE_ERROR = 0x1,
2022};
2023
2024struct mlx5_ifc_srqc_bits {
2025 u8 state[0x4];
2026 u8 log_srq_size[0x4];
2027 u8 reserved_0[0x18];
2028
2029 u8 wq_signature[0x1];
2030 u8 cont_srq[0x1];
2031 u8 reserved_1[0x1];
2032 u8 rlky[0x1];
2033 u8 reserved_2[0x1];
2034 u8 log_rq_stride[0x3];
2035 u8 xrcd[0x18];
2036
2037 u8 page_offset[0x6];
2038 u8 reserved_3[0x2];
2039 u8 cqn[0x18];
2040
2041 u8 reserved_4[0x20];
2042
2043 u8 reserved_5[0x2];
2044 u8 log_page_size[0x6];
2045 u8 reserved_6[0x18];
2046
2047 u8 reserved_7[0x20];
2048
2049 u8 reserved_8[0x8];
2050 u8 pd[0x18];
2051
2052 u8 lwm[0x10];
2053 u8 wqe_cnt[0x10];
2054
2055 u8 reserved_9[0x40];
2056
Haggai Abramonvsky01949d02015-06-04 19:30:38 +0300[diff] [blame]2057 u8 dbr_addr[0x40];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2058
Haggai Abramonvsky01949d02015-06-04 19:30:38 +0300[diff] [blame]2059 u8 reserved_10[0x80];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2060};
2061
2062enum {
2063 MLX5_SQC_STATE_RST = 0x0,
2064 MLX5_SQC_STATE_RDY = 0x1,
2065 MLX5_SQC_STATE_ERR = 0x3,
2066};
2067
2068struct mlx5_ifc_sqc_bits {
2069 u8 rlky[0x1];
2070 u8 cd_master[0x1];
2071 u8 fre[0x1];
2072 u8 flush_in_error_en[0x1];
2073 u8 reserved_0[0x4];
2074 u8 state[0x4];
2075 u8 reserved_1[0x14];
2076
2077 u8 reserved_2[0x8];
2078 u8 user_index[0x18];
2079
2080 u8 reserved_3[0x8];
2081 u8 cqn[0x18];
2082
2083 u8 reserved_4[0xa0];
2084
2085 u8 tis_lst_sz[0x10];
2086 u8 reserved_5[0x10];
2087
2088 u8 reserved_6[0x40];
2089
2090 u8 reserved_7[0x8];
2091 u8 tis_num_0[0x18];
2092
2093 struct mlx5_ifc_wq_bits wq;
2094};
2095
2096struct mlx5_ifc_rqtc_bits {
2097 u8 reserved_0[0xa0];
2098
2099 u8 reserved_1[0x10];
2100 u8 rqt_max_size[0x10];
2101
2102 u8 reserved_2[0x10];
2103 u8 rqt_actual_size[0x10];
2104
2105 u8 reserved_3[0x6a0];
2106
2107 struct mlx5_ifc_rq_num_bits rq_num[0];
2108};
2109
2110enum {
2111 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2112 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2113};
2114
2115enum {
2116 MLX5_RQC_STATE_RST = 0x0,
2117 MLX5_RQC_STATE_RDY = 0x1,
2118 MLX5_RQC_STATE_ERR = 0x3,
2119};
2120
2121struct mlx5_ifc_rqc_bits {
2122 u8 rlky[0x1];
2123 u8 reserved_0[0x2];
2124 u8 vsd[0x1];
2125 u8 mem_rq_type[0x4];
2126 u8 state[0x4];
2127 u8 reserved_1[0x1];
2128 u8 flush_in_error_en[0x1];
2129 u8 reserved_2[0x12];
2130
2131 u8 reserved_3[0x8];
2132 u8 user_index[0x18];
2133
2134 u8 reserved_4[0x8];
2135 u8 cqn[0x18];
2136
2137 u8 counter_set_id[0x8];
2138 u8 reserved_5[0x18];
2139
2140 u8 reserved_6[0x8];
2141 u8 rmpn[0x18];
2142
2143 u8 reserved_7[0xe0];
2144
2145 struct mlx5_ifc_wq_bits wq;
2146};
2147
2148enum {
2149 MLX5_RMPC_STATE_RDY = 0x1,
2150 MLX5_RMPC_STATE_ERR = 0x3,
2151};
2152
2153struct mlx5_ifc_rmpc_bits {
2154 u8 reserved_0[0x8];
2155 u8 state[0x4];
2156 u8 reserved_1[0x14];
2157
2158 u8 basic_cyclic_rcv_wqe[0x1];
2159 u8 reserved_2[0x1f];
2160
2161 u8 reserved_3[0x140];
2162
2163 struct mlx5_ifc_wq_bits wq;
2164};
2165
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2166struct mlx5_ifc_nic_vport_context_bits {
2167 u8 reserved_0[0x1f];
2168 u8 roce_en[0x1];
2169
Saeed Mahameedd82b7312015-12-01 18:03:14 +0200[diff] [blame]2170 u8 arm_change_event[0x1];
2171 u8 reserved_1[0x1a];
2172 u8 event_on_mtu[0x1];
2173 u8 event_on_promisc_change[0x1];
2174 u8 event_on_vlan_change[0x1];
2175 u8 event_on_mc_address_change[0x1];
2176 u8 event_on_uc_address_change[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2177
Saeed Mahameedd82b7312015-12-01 18:03:14 +0200[diff] [blame]2178 u8 reserved_2[0xf0];
2179
2180 u8 mtu[0x10];
2181
2182 u8 reserved_3[0x640];
2183
2184 u8 promisc_uc[0x1];
2185 u8 promisc_mc[0x1];
2186 u8 promisc_all[0x1];
2187 u8 reserved_4[0x2];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2188 u8 allowed_list_type[0x3];
Saeed Mahameedd82b7312015-12-01 18:03:14 +0200[diff] [blame]2189 u8 reserved_5[0xc];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2190 u8 allowed_list_size[0xc];
2191
2192 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2193
Saeed Mahameedd82b7312015-12-01 18:03:14 +0200[diff] [blame]2194 u8 reserved_6[0x20];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2195
2196 u8 current_uc_mac_address[0][0x40];
2197};
2198
2199enum {
2200 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2201 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2202 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2203};
2204
2205struct mlx5_ifc_mkc_bits {
2206 u8 reserved_0[0x1];
2207 u8 free[0x1];
2208 u8 reserved_1[0xd];
2209 u8 small_fence_on_rdma_read_response[0x1];
2210 u8 umr_en[0x1];
2211 u8 a[0x1];
2212 u8 rw[0x1];
2213 u8 rr[0x1];
2214 u8 lw[0x1];
2215 u8 lr[0x1];
2216 u8 access_mode[0x2];
2217 u8 reserved_2[0x8];
2218
2219 u8 qpn[0x18];
2220 u8 mkey_7_0[0x8];
2221
2222 u8 reserved_3[0x20];
2223
2224 u8 length64[0x1];
2225 u8 bsf_en[0x1];
2226 u8 sync_umr[0x1];
2227 u8 reserved_4[0x2];
2228 u8 expected_sigerr_count[0x1];
2229 u8 reserved_5[0x1];
2230 u8 en_rinval[0x1];
2231 u8 pd[0x18];
2232
2233 u8 start_addr[0x40];
2234
2235 u8 len[0x40];
2236
2237 u8 bsf_octword_size[0x20];
2238
2239 u8 reserved_6[0x80];
2240
2241 u8 translations_octword_size[0x20];
2242
2243 u8 reserved_7[0x1b];
2244 u8 log_page_size[0x5];
2245
2246 u8 reserved_8[0x20];
2247};
2248
2249struct mlx5_ifc_pkey_bits {
2250 u8 reserved_0[0x10];
2251 u8 pkey[0x10];
2252};
2253
2254struct mlx5_ifc_array128_auto_bits {
2255 u8 array128_auto[16][0x8];
2256};
2257
2258struct mlx5_ifc_hca_vport_context_bits {
2259 u8 field_select[0x20];
2260
2261 u8 reserved_0[0xe0];
2262
2263 u8 sm_virt_aware[0x1];
2264 u8 has_smi[0x1];
2265 u8 has_raw[0x1];
2266 u8 grh_required[0x1];
Majd Dibbiny707c4602015-06-04 19:30:41 +0300[diff] [blame]2267 u8 reserved_1[0xc];
2268 u8 port_physical_state[0x4];
2269 u8 vport_state_policy[0x4];
2270 u8 port_state[0x4];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2271 u8 vport_state[0x4];
2272
Majd Dibbiny707c4602015-06-04 19:30:41 +0300[diff] [blame]2273 u8 reserved_2[0x20];
2274
2275 u8 system_image_guid[0x40];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2276
2277 u8 port_guid[0x40];
2278
2279 u8 node_guid[0x40];
2280
2281 u8 cap_mask1[0x20];
2282
2283 u8 cap_mask1_field_select[0x20];
2284
2285 u8 cap_mask2[0x20];
2286
2287 u8 cap_mask2_field_select[0x20];
2288
2289 u8 reserved_3[0x80];
2290
2291 u8 lid[0x10];
2292 u8 reserved_4[0x4];
2293 u8 init_type_reply[0x4];
2294 u8 lmc[0x3];
2295 u8 subnet_timeout[0x5];
2296
2297 u8 sm_lid[0x10];
2298 u8 sm_sl[0x4];
2299 u8 reserved_5[0xc];
2300
2301 u8 qkey_violation_counter[0x10];
2302 u8 pkey_violation_counter[0x10];
2303
2304 u8 reserved_6[0xca0];
2305};
2306
2307enum {
2308 MLX5_EQC_STATUS_OK = 0x0,
2309 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2310};
2311
2312enum {
2313 MLX5_EQC_ST_ARMED = 0x9,
2314 MLX5_EQC_ST_FIRED = 0xa,
2315};
2316
2317struct mlx5_ifc_eqc_bits {
2318 u8 status[0x4];
2319 u8 reserved_0[0x9];
2320 u8 ec[0x1];
2321 u8 oi[0x1];
2322 u8 reserved_1[0x5];
2323 u8 st[0x4];
2324 u8 reserved_2[0x8];
2325
2326 u8 reserved_3[0x20];
2327
2328 u8 reserved_4[0x14];
2329 u8 page_offset[0x6];
2330 u8 reserved_5[0x6];
2331
2332 u8 reserved_6[0x3];
2333 u8 log_eq_size[0x5];
2334 u8 uar_page[0x18];
2335
2336 u8 reserved_7[0x20];
2337
2338 u8 reserved_8[0x18];
2339 u8 intr[0x8];
2340
2341 u8 reserved_9[0x3];
2342 u8 log_page_size[0x5];
2343 u8 reserved_10[0x18];
2344
2345 u8 reserved_11[0x60];
2346
2347 u8 reserved_12[0x8];
2348 u8 consumer_counter[0x18];
2349
2350 u8 reserved_13[0x8];
2351 u8 producer_counter[0x18];
2352
2353 u8 reserved_14[0x80];
2354};
2355
2356enum {
2357 MLX5_DCTC_STATE_ACTIVE = 0x0,
2358 MLX5_DCTC_STATE_DRAINING = 0x1,
2359 MLX5_DCTC_STATE_DRAINED = 0x2,
2360};
2361
2362enum {
2363 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2364 MLX5_DCTC_CS_RES_NA = 0x1,
2365 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2366};
2367
2368enum {
2369 MLX5_DCTC_MTU_256_BYTES = 0x1,
2370 MLX5_DCTC_MTU_512_BYTES = 0x2,
2371 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2372 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2373 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2374};
2375
2376struct mlx5_ifc_dctc_bits {
2377 u8 reserved_0[0x4];
2378 u8 state[0x4];
2379 u8 reserved_1[0x18];
2380
2381 u8 reserved_2[0x8];
2382 u8 user_index[0x18];
2383
2384 u8 reserved_3[0x8];
2385 u8 cqn[0x18];
2386
2387 u8 counter_set_id[0x8];
2388 u8 atomic_mode[0x4];
2389 u8 rre[0x1];
2390 u8 rwe[0x1];
2391 u8 rae[0x1];
2392 u8 atomic_like_write_en[0x1];
2393 u8 latency_sensitive[0x1];
2394 u8 rlky[0x1];
2395 u8 free_ar[0x1];
2396 u8 reserved_4[0xd];
2397
2398 u8 reserved_5[0x8];
2399 u8 cs_res[0x8];
2400 u8 reserved_6[0x3];
2401 u8 min_rnr_nak[0x5];
2402 u8 reserved_7[0x8];
2403
2404 u8 reserved_8[0x8];
2405 u8 srqn[0x18];
2406
2407 u8 reserved_9[0x8];
2408 u8 pd[0x18];
2409
2410 u8 tclass[0x8];
2411 u8 reserved_10[0x4];
2412 u8 flow_label[0x14];
2413
2414 u8 dc_access_key[0x40];
2415
2416 u8 reserved_11[0x5];
2417 u8 mtu[0x3];
2418 u8 port[0x8];
2419 u8 pkey_index[0x10];
2420
2421 u8 reserved_12[0x8];
2422 u8 my_addr_index[0x8];
2423 u8 reserved_13[0x8];
2424 u8 hop_limit[0x8];
2425
2426 u8 dc_access_key_violation_count[0x20];
2427
2428 u8 reserved_14[0x14];
2429 u8 dei_cfi[0x1];
2430 u8 eth_prio[0x3];
2431 u8 ecn[0x2];
2432 u8 dscp[0x6];
2433
2434 u8 reserved_15[0x40];
2435};
2436
2437enum {
2438 MLX5_CQC_STATUS_OK = 0x0,
2439 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2440 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2441};
2442
2443enum {
2444 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2445 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2446};
2447
2448enum {
2449 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2450 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2451 MLX5_CQC_ST_FIRED = 0xa,
2452};
2453
2454struct mlx5_ifc_cqc_bits {
2455 u8 status[0x4];
2456 u8 reserved_0[0x4];
2457 u8 cqe_sz[0x3];
2458 u8 cc[0x1];
2459 u8 reserved_1[0x1];
2460 u8 scqe_break_moderation_en[0x1];
2461 u8 oi[0x1];
2462 u8 reserved_2[0x2];
2463 u8 cqe_zip_en[0x1];
2464 u8 mini_cqe_res_format[0x2];
2465 u8 st[0x4];
2466 u8 reserved_3[0x8];
2467
2468 u8 reserved_4[0x20];
2469
2470 u8 reserved_5[0x14];
2471 u8 page_offset[0x6];
2472 u8 reserved_6[0x6];
2473
2474 u8 reserved_7[0x3];
2475 u8 log_cq_size[0x5];
2476 u8 uar_page[0x18];
2477
2478 u8 reserved_8[0x4];
2479 u8 cq_period[0xc];
2480 u8 cq_max_count[0x10];
2481
2482 u8 reserved_9[0x18];
2483 u8 c_eqn[0x8];
2484
2485 u8 reserved_10[0x3];
2486 u8 log_page_size[0x5];
2487 u8 reserved_11[0x18];
2488
2489 u8 reserved_12[0x20];
2490
2491 u8 reserved_13[0x8];
2492 u8 last_notified_index[0x18];
2493
2494 u8 reserved_14[0x8];
2495 u8 last_solicit_index[0x18];
2496
2497 u8 reserved_15[0x8];
2498 u8 consumer_counter[0x18];
2499
2500 u8 reserved_16[0x8];
2501 u8 producer_counter[0x18];
2502
2503 u8 reserved_17[0x40];
2504
2505 u8 dbr_addr[0x40];
2506};
2507
2508union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2509 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2510 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2511 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2512 u8 reserved_0[0x800];
2513};
2514
2515struct mlx5_ifc_query_adapter_param_block_bits {
Majd Dibbiny211e6c82015-06-04 19:30:42 +0300[diff] [blame]2516 u8 reserved_0[0xc0];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2517
Majd Dibbiny211e6c82015-06-04 19:30:42 +0300[diff] [blame]2518 u8 reserved_1[0x8];
2519 u8 ieee_vendor_id[0x18];
2520
2521 u8 reserved_2[0x10];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2522 u8 vsd_vendor_id[0x10];
2523
2524 u8 vsd[208][0x8];
2525
2526 u8 vsd_contd_psid[16][0x8];
2527};
2528
2529union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2530 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2531 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2532 u8 reserved_0[0x20];
2533};
2534
2535union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2536 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2537 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2538 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2539 u8 reserved_0[0x20];
2540};
2541
2542union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2543 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2544 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2545 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2546 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2547 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2548 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2549 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2550 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2551 u8 reserved_0[0x7c0];
2552};
2553
2554union mlx5_ifc_event_auto_bits {
2555 struct mlx5_ifc_comp_event_bits comp_event;
2556 struct mlx5_ifc_dct_events_bits dct_events;
2557 struct mlx5_ifc_qp_events_bits qp_events;
2558 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2559 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2560 struct mlx5_ifc_cq_error_bits cq_error;
2561 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2562 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2563 struct mlx5_ifc_gpio_event_bits gpio_event;
2564 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2565 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2566 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2567 u8 reserved_0[0xe0];
2568};
2569
2570struct mlx5_ifc_health_buffer_bits {
2571 u8 reserved_0[0x100];
2572
2573 u8 assert_existptr[0x20];
2574
2575 u8 assert_callra[0x20];
2576
2577 u8 reserved_1[0x40];
2578
2579 u8 fw_version[0x20];
2580
2581 u8 hw_id[0x20];
2582
2583 u8 reserved_2[0x20];
2584
2585 u8 irisc_index[0x8];
2586 u8 synd[0x8];
2587 u8 ext_synd[0x10];
2588};
2589
2590struct mlx5_ifc_register_loopback_control_bits {
2591 u8 no_lb[0x1];
2592 u8 reserved_0[0x7];
2593 u8 port[0x8];
2594 u8 reserved_1[0x10];
2595
2596 u8 reserved_2[0x60];
2597};
2598
2599struct mlx5_ifc_teardown_hca_out_bits {
2600 u8 status[0x8];
2601 u8 reserved_0[0x18];
2602
2603 u8 syndrome[0x20];
2604
2605 u8 reserved_1[0x40];
2606};
2607
2608enum {
2609 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2610 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2611};
2612
2613struct mlx5_ifc_teardown_hca_in_bits {
2614 u8 opcode[0x10];
2615 u8 reserved_0[0x10];
2616
2617 u8 reserved_1[0x10];
2618 u8 op_mod[0x10];
2619
2620 u8 reserved_2[0x10];
2621 u8 profile[0x10];
2622
2623 u8 reserved_3[0x20];
2624};
2625
2626struct mlx5_ifc_sqerr2rts_qp_out_bits {
2627 u8 status[0x8];
2628 u8 reserved_0[0x18];
2629
2630 u8 syndrome[0x20];
2631
2632 u8 reserved_1[0x40];
2633};
2634
2635struct mlx5_ifc_sqerr2rts_qp_in_bits {
2636 u8 opcode[0x10];
2637 u8 reserved_0[0x10];
2638
2639 u8 reserved_1[0x10];
2640 u8 op_mod[0x10];
2641
2642 u8 reserved_2[0x8];
2643 u8 qpn[0x18];
2644
2645 u8 reserved_3[0x20];
2646
2647 u8 opt_param_mask[0x20];
2648
2649 u8 reserved_4[0x20];
2650
2651 struct mlx5_ifc_qpc_bits qpc;
2652
2653 u8 reserved_5[0x80];
2654};
2655
2656struct mlx5_ifc_sqd2rts_qp_out_bits {
2657 u8 status[0x8];
2658 u8 reserved_0[0x18];
2659
2660 u8 syndrome[0x20];
2661
2662 u8 reserved_1[0x40];
2663};
2664
2665struct mlx5_ifc_sqd2rts_qp_in_bits {
2666 u8 opcode[0x10];
2667 u8 reserved_0[0x10];
2668
2669 u8 reserved_1[0x10];
2670 u8 op_mod[0x10];
2671
2672 u8 reserved_2[0x8];
2673 u8 qpn[0x18];
2674
2675 u8 reserved_3[0x20];
2676
2677 u8 opt_param_mask[0x20];
2678
2679 u8 reserved_4[0x20];
2680
2681 struct mlx5_ifc_qpc_bits qpc;
2682
2683 u8 reserved_5[0x80];
2684};
2685
2686struct mlx5_ifc_set_roce_address_out_bits {
2687 u8 status[0x8];
2688 u8 reserved_0[0x18];
2689
2690 u8 syndrome[0x20];
2691
2692 u8 reserved_1[0x40];
2693};
2694
2695struct mlx5_ifc_set_roce_address_in_bits {
2696 u8 opcode[0x10];
2697 u8 reserved_0[0x10];
2698
2699 u8 reserved_1[0x10];
2700 u8 op_mod[0x10];
2701
2702 u8 roce_address_index[0x10];
2703 u8 reserved_2[0x10];
2704
2705 u8 reserved_3[0x20];
2706
2707 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2708};
2709
2710struct mlx5_ifc_set_mad_demux_out_bits {
2711 u8 status[0x8];
2712 u8 reserved_0[0x18];
2713
2714 u8 syndrome[0x20];
2715
2716 u8 reserved_1[0x40];
2717};
2718
2719enum {
2720 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2721 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2722};
2723
2724struct mlx5_ifc_set_mad_demux_in_bits {
2725 u8 opcode[0x10];
2726 u8 reserved_0[0x10];
2727
2728 u8 reserved_1[0x10];
2729 u8 op_mod[0x10];
2730
2731 u8 reserved_2[0x20];
2732
2733 u8 reserved_3[0x6];
2734 u8 demux_mode[0x2];
2735 u8 reserved_4[0x18];
2736};
2737
2738struct mlx5_ifc_set_l2_table_entry_out_bits {
2739 u8 status[0x8];
2740 u8 reserved_0[0x18];
2741
2742 u8 syndrome[0x20];
2743
2744 u8 reserved_1[0x40];
2745};
2746
2747struct mlx5_ifc_set_l2_table_entry_in_bits {
2748 u8 opcode[0x10];
2749 u8 reserved_0[0x10];
2750
2751 u8 reserved_1[0x10];
2752 u8 op_mod[0x10];
2753
2754 u8 reserved_2[0x60];
2755
2756 u8 reserved_3[0x8];
2757 u8 table_index[0x18];
2758
2759 u8 reserved_4[0x20];
2760
2761 u8 reserved_5[0x13];
2762 u8 vlan_valid[0x1];
2763 u8 vlan[0xc];
2764
2765 struct mlx5_ifc_mac_address_layout_bits mac_address;
2766
2767 u8 reserved_6[0xc0];
2768};
2769
2770struct mlx5_ifc_set_issi_out_bits {
2771 u8 status[0x8];
2772 u8 reserved_0[0x18];
2773
2774 u8 syndrome[0x20];
2775
2776 u8 reserved_1[0x40];
2777};
2778
2779struct mlx5_ifc_set_issi_in_bits {
2780 u8 opcode[0x10];
2781 u8 reserved_0[0x10];
2782
2783 u8 reserved_1[0x10];
2784 u8 op_mod[0x10];
2785
2786 u8 reserved_2[0x10];
2787 u8 current_issi[0x10];
2788
2789 u8 reserved_3[0x20];
2790};
2791
2792struct mlx5_ifc_set_hca_cap_out_bits {
2793 u8 status[0x8];
2794 u8 reserved_0[0x18];
2795
2796 u8 syndrome[0x20];
2797
2798 u8 reserved_1[0x40];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]2799};
2800
2801struct mlx5_ifc_set_hca_cap_in_bits {
2802 u8 opcode[0x10];
2803 u8 reserved_0[0x10];
2804
2805 u8 reserved_1[0x10];
2806 u8 op_mod[0x10];
2807
2808 u8 reserved_2[0x40];
2809
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2810 union mlx5_ifc_hca_cap_union_bits capability;
2811};
2812
2813struct mlx5_ifc_set_fte_out_bits {
2814 u8 status[0x8];
2815 u8 reserved_0[0x18];
2816
2817 u8 syndrome[0x20];
2818
2819 u8 reserved_1[0x40];
2820};
2821
2822struct mlx5_ifc_set_fte_in_bits {
2823 u8 opcode[0x10];
2824 u8 reserved_0[0x10];
2825
2826 u8 reserved_1[0x10];
2827 u8 op_mod[0x10];
2828
2829 u8 reserved_2[0x40];
2830
2831 u8 table_type[0x8];
2832 u8 reserved_3[0x18];
2833
2834 u8 reserved_4[0x8];
2835 u8 table_id[0x18];
2836
2837 u8 reserved_5[0x40];
2838
2839 u8 flow_index[0x20];
2840
2841 u8 reserved_6[0xe0];
2842
2843 struct mlx5_ifc_flow_context_bits flow_context;
2844};
2845
2846struct mlx5_ifc_rts2rts_qp_out_bits {
2847 u8 status[0x8];
2848 u8 reserved_0[0x18];
2849
2850 u8 syndrome[0x20];
2851
2852 u8 reserved_1[0x40];
2853};
2854
2855struct mlx5_ifc_rts2rts_qp_in_bits {
2856 u8 opcode[0x10];
2857 u8 reserved_0[0x10];
2858
2859 u8 reserved_1[0x10];
2860 u8 op_mod[0x10];
2861
2862 u8 reserved_2[0x8];
2863 u8 qpn[0x18];
2864
2865 u8 reserved_3[0x20];
2866
2867 u8 opt_param_mask[0x20];
2868
2869 u8 reserved_4[0x20];
2870
2871 struct mlx5_ifc_qpc_bits qpc;
2872
2873 u8 reserved_5[0x80];
2874};
2875
2876struct mlx5_ifc_rtr2rts_qp_out_bits {
2877 u8 status[0x8];
2878 u8 reserved_0[0x18];
2879
2880 u8 syndrome[0x20];
2881
2882 u8 reserved_1[0x40];
2883};
2884
2885struct mlx5_ifc_rtr2rts_qp_in_bits {
2886 u8 opcode[0x10];
2887 u8 reserved_0[0x10];
2888
2889 u8 reserved_1[0x10];
2890 u8 op_mod[0x10];
2891
2892 u8 reserved_2[0x8];
2893 u8 qpn[0x18];
2894
2895 u8 reserved_3[0x20];
2896
2897 u8 opt_param_mask[0x20];
2898
2899 u8 reserved_4[0x20];
2900
2901 struct mlx5_ifc_qpc_bits qpc;
2902
2903 u8 reserved_5[0x80];
2904};
2905
2906struct mlx5_ifc_rst2init_qp_out_bits {
2907 u8 status[0x8];
2908 u8 reserved_0[0x18];
2909
2910 u8 syndrome[0x20];
2911
2912 u8 reserved_1[0x40];
2913};
2914
2915struct mlx5_ifc_rst2init_qp_in_bits {
2916 u8 opcode[0x10];
2917 u8 reserved_0[0x10];
2918
2919 u8 reserved_1[0x10];
2920 u8 op_mod[0x10];
2921
2922 u8 reserved_2[0x8];
2923 u8 qpn[0x18];
2924
2925 u8 reserved_3[0x20];
2926
2927 u8 opt_param_mask[0x20];
2928
2929 u8 reserved_4[0x20];
2930
2931 struct mlx5_ifc_qpc_bits qpc;
2932
2933 u8 reserved_5[0x80];
2934};
2935
2936struct mlx5_ifc_query_xrc_srq_out_bits {
2937 u8 status[0x8];
2938 u8 reserved_0[0x18];
2939
2940 u8 syndrome[0x20];
2941
2942 u8 reserved_1[0x40];
2943
2944 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
2945
2946 u8 reserved_2[0x600];
2947
2948 u8 pas[0][0x40];
2949};
2950
2951struct mlx5_ifc_query_xrc_srq_in_bits {
2952 u8 opcode[0x10];
2953 u8 reserved_0[0x10];
2954
2955 u8 reserved_1[0x10];
2956 u8 op_mod[0x10];
2957
2958 u8 reserved_2[0x8];
2959 u8 xrc_srqn[0x18];
2960
2961 u8 reserved_3[0x20];
2962};
2963
2964enum {
2965 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
2966 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
2967};
2968
2969struct mlx5_ifc_query_vport_state_out_bits {
2970 u8 status[0x8];
2971 u8 reserved_0[0x18];
2972
2973 u8 syndrome[0x20];
2974
2975 u8 reserved_1[0x20];
2976
2977 u8 reserved_2[0x18];
2978 u8 admin_state[0x4];
2979 u8 state[0x4];
2980};
2981
2982enum {
2983 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
Saeed Mahameede7546512015-12-01 18:03:13 +0200[diff] [blame]2984 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2985};
2986
2987struct mlx5_ifc_query_vport_state_in_bits {
2988 u8 opcode[0x10];
2989 u8 reserved_0[0x10];
2990
2991 u8 reserved_1[0x10];
2992 u8 op_mod[0x10];
2993
2994 u8 other_vport[0x1];
2995 u8 reserved_2[0xf];
2996 u8 vport_number[0x10];
2997
2998 u8 reserved_3[0x20];
2999};
3000
3001struct mlx5_ifc_query_vport_counter_out_bits {
3002 u8 status[0x8];
3003 u8 reserved_0[0x18];
3004
3005 u8 syndrome[0x20];
3006
3007 u8 reserved_1[0x40];
3008
3009 struct mlx5_ifc_traffic_counter_bits received_errors;
3010
3011 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3012
3013 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3014
3015 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3016
3017 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3018
3019 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3020
3021 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3022
3023 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3024
3025 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3026
3027 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3028
3029 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3030
3031 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3032
3033 u8 reserved_2[0xa00];
3034};
3035
3036enum {
3037 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3038};
3039
3040struct mlx5_ifc_query_vport_counter_in_bits {
3041 u8 opcode[0x10];
3042 u8 reserved_0[0x10];
3043
3044 u8 reserved_1[0x10];
3045 u8 op_mod[0x10];
3046
3047 u8 other_vport[0x1];
3048 u8 reserved_2[0xf];
3049 u8 vport_number[0x10];
3050
3051 u8 reserved_3[0x60];
3052
3053 u8 clear[0x1];
3054 u8 reserved_4[0x1f];
3055
3056 u8 reserved_5[0x20];
3057};
3058
3059struct mlx5_ifc_query_tis_out_bits {
3060 u8 status[0x8];
3061 u8 reserved_0[0x18];
3062
3063 u8 syndrome[0x20];
3064
3065 u8 reserved_1[0x40];
3066
3067 struct mlx5_ifc_tisc_bits tis_context;
3068};
3069
3070struct mlx5_ifc_query_tis_in_bits {
3071 u8 opcode[0x10];
3072 u8 reserved_0[0x10];
3073
3074 u8 reserved_1[0x10];
3075 u8 op_mod[0x10];
3076
3077 u8 reserved_2[0x8];
3078 u8 tisn[0x18];
3079
3080 u8 reserved_3[0x20];
3081};
3082
3083struct mlx5_ifc_query_tir_out_bits {
3084 u8 status[0x8];
3085 u8 reserved_0[0x18];
3086
3087 u8 syndrome[0x20];
3088
3089 u8 reserved_1[0xc0];
3090
3091 struct mlx5_ifc_tirc_bits tir_context;
3092};
3093
3094struct mlx5_ifc_query_tir_in_bits {
3095 u8 opcode[0x10];
3096 u8 reserved_0[0x10];
3097
3098 u8 reserved_1[0x10];
3099 u8 op_mod[0x10];
3100
3101 u8 reserved_2[0x8];
3102 u8 tirn[0x18];
3103
3104 u8 reserved_3[0x20];
3105};
3106
3107struct mlx5_ifc_query_srq_out_bits {
3108 u8 status[0x8];
3109 u8 reserved_0[0x18];
3110
3111 u8 syndrome[0x20];
3112
3113 u8 reserved_1[0x40];
3114
3115 struct mlx5_ifc_srqc_bits srq_context_entry;
3116
3117 u8 reserved_2[0x600];
3118
3119 u8 pas[0][0x40];
3120};
3121
3122struct mlx5_ifc_query_srq_in_bits {
3123 u8 opcode[0x10];
3124 u8 reserved_0[0x10];
3125
3126 u8 reserved_1[0x10];
3127 u8 op_mod[0x10];
3128
3129 u8 reserved_2[0x8];
3130 u8 srqn[0x18];
3131
3132 u8 reserved_3[0x20];
3133};
3134
3135struct mlx5_ifc_query_sq_out_bits {
3136 u8 status[0x8];
3137 u8 reserved_0[0x18];
3138
3139 u8 syndrome[0x20];
3140
3141 u8 reserved_1[0xc0];
3142
3143 struct mlx5_ifc_sqc_bits sq_context;
3144};
3145
3146struct mlx5_ifc_query_sq_in_bits {
3147 u8 opcode[0x10];
3148 u8 reserved_0[0x10];
3149
3150 u8 reserved_1[0x10];
3151 u8 op_mod[0x10];
3152
3153 u8 reserved_2[0x8];
3154 u8 sqn[0x18];
3155
3156 u8 reserved_3[0x20];
3157};
3158
3159struct mlx5_ifc_query_special_contexts_out_bits {
3160 u8 status[0x8];
3161 u8 reserved_0[0x18];
3162
3163 u8 syndrome[0x20];
3164
3165 u8 reserved_1[0x20];
3166
3167 u8 resd_lkey[0x20];
3168};
3169
3170struct mlx5_ifc_query_special_contexts_in_bits {
3171 u8 opcode[0x10];
3172 u8 reserved_0[0x10];
3173
3174 u8 reserved_1[0x10];
3175 u8 op_mod[0x10];
3176
3177 u8 reserved_2[0x40];
3178};
3179
3180struct mlx5_ifc_query_rqt_out_bits {
3181 u8 status[0x8];
3182 u8 reserved_0[0x18];
3183
3184 u8 syndrome[0x20];
3185
3186 u8 reserved_1[0xc0];
3187
3188 struct mlx5_ifc_rqtc_bits rqt_context;
3189};
3190
3191struct mlx5_ifc_query_rqt_in_bits {
3192 u8 opcode[0x10];
3193 u8 reserved_0[0x10];
3194
3195 u8 reserved_1[0x10];
3196 u8 op_mod[0x10];
3197
3198 u8 reserved_2[0x8];
3199 u8 rqtn[0x18];
3200
3201 u8 reserved_3[0x20];
3202};
3203
3204struct mlx5_ifc_query_rq_out_bits {
3205 u8 status[0x8];
3206 u8 reserved_0[0x18];
3207
3208 u8 syndrome[0x20];
3209
3210 u8 reserved_1[0xc0];
3211
3212 struct mlx5_ifc_rqc_bits rq_context;
3213};
3214
3215struct mlx5_ifc_query_rq_in_bits {
3216 u8 opcode[0x10];
3217 u8 reserved_0[0x10];
3218
3219 u8 reserved_1[0x10];
3220 u8 op_mod[0x10];
3221
3222 u8 reserved_2[0x8];
3223 u8 rqn[0x18];
3224
3225 u8 reserved_3[0x20];
3226};
3227
3228struct mlx5_ifc_query_roce_address_out_bits {
3229 u8 status[0x8];
3230 u8 reserved_0[0x18];
3231
3232 u8 syndrome[0x20];
3233
3234 u8 reserved_1[0x40];
3235
3236 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3237};
3238
3239struct mlx5_ifc_query_roce_address_in_bits {
3240 u8 opcode[0x10];
3241 u8 reserved_0[0x10];
3242
3243 u8 reserved_1[0x10];
3244 u8 op_mod[0x10];
3245
3246 u8 roce_address_index[0x10];
3247 u8 reserved_2[0x10];
3248
3249 u8 reserved_3[0x20];
3250};
3251
3252struct mlx5_ifc_query_rmp_out_bits {
3253 u8 status[0x8];
3254 u8 reserved_0[0x18];
3255
3256 u8 syndrome[0x20];
3257
3258 u8 reserved_1[0xc0];
3259
3260 struct mlx5_ifc_rmpc_bits rmp_context;
3261};
3262
3263struct mlx5_ifc_query_rmp_in_bits {
3264 u8 opcode[0x10];
3265 u8 reserved_0[0x10];
3266
3267 u8 reserved_1[0x10];
3268 u8 op_mod[0x10];
3269
3270 u8 reserved_2[0x8];
3271 u8 rmpn[0x18];
3272
3273 u8 reserved_3[0x20];
3274};
3275
3276struct mlx5_ifc_query_qp_out_bits {
3277 u8 status[0x8];
3278 u8 reserved_0[0x18];
3279
3280 u8 syndrome[0x20];
3281
3282 u8 reserved_1[0x40];
3283
3284 u8 opt_param_mask[0x20];
3285
3286 u8 reserved_2[0x20];
3287
3288 struct mlx5_ifc_qpc_bits qpc;
3289
3290 u8 reserved_3[0x80];
3291
3292 u8 pas[0][0x40];
3293};
3294
3295struct mlx5_ifc_query_qp_in_bits {
3296 u8 opcode[0x10];
3297 u8 reserved_0[0x10];
3298
3299 u8 reserved_1[0x10];
3300 u8 op_mod[0x10];
3301
3302 u8 reserved_2[0x8];
3303 u8 qpn[0x18];
3304
3305 u8 reserved_3[0x20];
3306};
3307
3308struct mlx5_ifc_query_q_counter_out_bits {
3309 u8 status[0x8];
3310 u8 reserved_0[0x18];
3311
3312 u8 syndrome[0x20];
3313
3314 u8 reserved_1[0x40];
3315
3316 u8 rx_write_requests[0x20];
3317
3318 u8 reserved_2[0x20];
3319
3320 u8 rx_read_requests[0x20];
3321
3322 u8 reserved_3[0x20];
3323
3324 u8 rx_atomic_requests[0x20];
3325
3326 u8 reserved_4[0x20];
3327
3328 u8 rx_dct_connect[0x20];
3329
3330 u8 reserved_5[0x20];
3331
3332 u8 out_of_buffer[0x20];
3333
3334 u8 reserved_6[0x20];
3335
3336 u8 out_of_sequence[0x20];
3337
3338 u8 reserved_7[0x620];
3339};
3340
3341struct mlx5_ifc_query_q_counter_in_bits {
3342 u8 opcode[0x10];
3343 u8 reserved_0[0x10];
3344
3345 u8 reserved_1[0x10];
3346 u8 op_mod[0x10];
3347
3348 u8 reserved_2[0x80];
3349
3350 u8 clear[0x1];
3351 u8 reserved_3[0x1f];
3352
3353 u8 reserved_4[0x18];
3354 u8 counter_set_id[0x8];
3355};
3356
3357struct mlx5_ifc_query_pages_out_bits {
3358 u8 status[0x8];
3359 u8 reserved_0[0x18];
3360
3361 u8 syndrome[0x20];
3362
3363 u8 reserved_1[0x10];
3364 u8 function_id[0x10];
3365
3366 u8 num_pages[0x20];
3367};
3368
3369enum {
3370 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3371 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3372 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3373};
3374
3375struct mlx5_ifc_query_pages_in_bits {
3376 u8 opcode[0x10];
3377 u8 reserved_0[0x10];
3378
3379 u8 reserved_1[0x10];
3380 u8 op_mod[0x10];
3381
3382 u8 reserved_2[0x10];
3383 u8 function_id[0x10];
3384
3385 u8 reserved_3[0x20];
3386};
3387
3388struct mlx5_ifc_query_nic_vport_context_out_bits {
3389 u8 status[0x8];
3390 u8 reserved_0[0x18];
3391
3392 u8 syndrome[0x20];
3393
3394 u8 reserved_1[0x40];
3395
3396 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3397};
3398
3399struct mlx5_ifc_query_nic_vport_context_in_bits {
3400 u8 opcode[0x10];
3401 u8 reserved_0[0x10];
3402
3403 u8 reserved_1[0x10];
3404 u8 op_mod[0x10];
3405
3406 u8 other_vport[0x1];
3407 u8 reserved_2[0xf];
3408 u8 vport_number[0x10];
3409
3410 u8 reserved_3[0x5];
3411 u8 allowed_list_type[0x3];
3412 u8 reserved_4[0x18];
3413};
3414
3415struct mlx5_ifc_query_mkey_out_bits {
3416 u8 status[0x8];
3417 u8 reserved_0[0x18];
3418
3419 u8 syndrome[0x20];
3420
3421 u8 reserved_1[0x40];
3422
3423 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3424
3425 u8 reserved_2[0x600];
3426
3427 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3428
3429 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3430};
3431
3432struct mlx5_ifc_query_mkey_in_bits {
3433 u8 opcode[0x10];
3434 u8 reserved_0[0x10];
3435
3436 u8 reserved_1[0x10];
3437 u8 op_mod[0x10];
3438
3439 u8 reserved_2[0x8];
3440 u8 mkey_index[0x18];
3441
3442 u8 pg_access[0x1];
3443 u8 reserved_3[0x1f];
3444};
3445
3446struct mlx5_ifc_query_mad_demux_out_bits {
3447 u8 status[0x8];
3448 u8 reserved_0[0x18];
3449
3450 u8 syndrome[0x20];
3451
3452 u8 reserved_1[0x40];
3453
3454 u8 mad_dumux_parameters_block[0x20];
3455};
3456
3457struct mlx5_ifc_query_mad_demux_in_bits {
3458 u8 opcode[0x10];
3459 u8 reserved_0[0x10];
3460
3461 u8 reserved_1[0x10];
3462 u8 op_mod[0x10];
3463
3464 u8 reserved_2[0x40];
3465};
3466
3467struct mlx5_ifc_query_l2_table_entry_out_bits {
3468 u8 status[0x8];
3469 u8 reserved_0[0x18];
3470
3471 u8 syndrome[0x20];
3472
3473 u8 reserved_1[0xa0];
3474
3475 u8 reserved_2[0x13];
3476 u8 vlan_valid[0x1];
3477 u8 vlan[0xc];
3478
3479 struct mlx5_ifc_mac_address_layout_bits mac_address;
3480
3481 u8 reserved_3[0xc0];
3482};
3483
3484struct mlx5_ifc_query_l2_table_entry_in_bits {
3485 u8 opcode[0x10];
3486 u8 reserved_0[0x10];
3487
3488 u8 reserved_1[0x10];
3489 u8 op_mod[0x10];
3490
3491 u8 reserved_2[0x60];
3492
3493 u8 reserved_3[0x8];
3494 u8 table_index[0x18];
3495
3496 u8 reserved_4[0x140];
3497};
3498
3499struct mlx5_ifc_query_issi_out_bits {
3500 u8 status[0x8];
3501 u8 reserved_0[0x18];
3502
3503 u8 syndrome[0x20];
3504
3505 u8 reserved_1[0x10];
3506 u8 current_issi[0x10];
3507
3508 u8 reserved_2[0xa0];
3509
3510 u8 supported_issi_reserved[76][0x8];
3511 u8 supported_issi_dw0[0x20];
3512};
3513
3514struct mlx5_ifc_query_issi_in_bits {
3515 u8 opcode[0x10];
3516 u8 reserved_0[0x10];
3517
3518 u8 reserved_1[0x10];
3519 u8 op_mod[0x10];
3520
3521 u8 reserved_2[0x40];
3522};
3523
3524struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3525 u8 status[0x8];
3526 u8 reserved_0[0x18];
3527
3528 u8 syndrome[0x20];
3529
3530 u8 reserved_1[0x40];
3531
3532 struct mlx5_ifc_pkey_bits pkey[0];
3533};
3534
3535struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3536 u8 opcode[0x10];
3537 u8 reserved_0[0x10];
3538
3539 u8 reserved_1[0x10];
3540 u8 op_mod[0x10];
3541
3542 u8 other_vport[0x1];
Majd Dibbiny707c4602015-06-04 19:30:41 +0300[diff] [blame]3543 u8 reserved_2[0xb];
3544 u8 port_num[0x4];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]3545 u8 vport_number[0x10];
3546
3547 u8 reserved_3[0x10];
3548 u8 pkey_index[0x10];
3549};
3550
3551struct mlx5_ifc_query_hca_vport_gid_out_bits {
3552 u8 status[0x8];
3553 u8 reserved_0[0x18];
3554
3555 u8 syndrome[0x20];
3556
3557 u8 reserved_1[0x20];
3558
3559 u8 gids_num[0x10];
3560 u8 reserved_2[0x10];
3561
3562 struct mlx5_ifc_array128_auto_bits gid[0];
3563};
3564
3565struct mlx5_ifc_query_hca_vport_gid_in_bits {
3566 u8 opcode[0x10];
3567 u8 reserved_0[0x10];
3568
3569 u8 reserved_1[0x10];
3570 u8 op_mod[0x10];
3571
3572 u8 other_vport[0x1];
Majd Dibbiny707c4602015-06-04 19:30:41 +0300[diff] [blame]3573 u8 reserved_2[0xb];
3574 u8 port_num[0x4];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]3575 u8 vport_number[0x10];
3576
3577 u8 reserved_3[0x10];
3578 u8 gid_index[0x10];
3579};
3580
3581struct mlx5_ifc_query_hca_vport_context_out_bits {
3582 u8 status[0x8];
3583 u8 reserved_0[0x18];
3584
3585 u8 syndrome[0x20];
3586
3587 u8 reserved_1[0x40];
3588
3589 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3590};
3591
3592struct mlx5_ifc_query_hca_vport_context_in_bits {
3593 u8 opcode[0x10];
3594 u8 reserved_0[0x10];
3595
3596 u8 reserved_1[0x10];
3597 u8 op_mod[0x10];
3598
3599 u8 other_vport[0x1];
Majd Dibbiny707c4602015-06-04 19:30:41 +0300[diff] [blame]3600 u8 reserved_2[0xb];
3601 u8 port_num[0x4];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]3602 u8 vport_number[0x10];
3603
3604 u8 reserved_3[0x20];
3605};
3606
3607struct mlx5_ifc_query_hca_cap_out_bits {
3608 u8 status[0x8];
3609 u8 reserved_0[0x18];
3610
3611 u8 syndrome[0x20];
3612
3613 u8 reserved_1[0x40];
3614
3615 union mlx5_ifc_hca_cap_union_bits capability;
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]3616};
3617
3618struct mlx5_ifc_query_hca_cap_in_bits {
3619 u8 opcode[0x10];
3620 u8 reserved_0[0x10];
3621
3622 u8 reserved_1[0x10];
3623 u8 op_mod[0x10];
3624
3625 u8 reserved_2[0x40];
3626};
3627
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]3628struct mlx5_ifc_query_flow_table_out_bits {
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]3629 u8 status[0x8];
3630 u8 reserved_0[0x18];
3631
3632 u8 syndrome[0x20];
3633
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]3634 u8 reserved_1[0x80];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]3635
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]3636 u8 reserved_2[0x8];
3637 u8 level[0x8];
3638 u8 reserved_3[0x8];
3639 u8 log_size[0x8];
3640
3641 u8 reserved_4[0x120];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]3642};
3643
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]3644struct mlx5_ifc_query_flow_table_in_bits {
3645 u8 opcode[0x10];
3646 u8 reserved_0[0x10];
3647
3648 u8 reserved_1[0x10];
3649 u8 op_mod[0x10];
3650
3651 u8 reserved_2[0x40];
3652
3653 u8 table_type[0x8];
3654 u8 reserved_3[0x18];
3655
3656 u8 reserved_4[0x8];
3657 u8 table_id[0x18];
3658
3659 u8 reserved_5[0x140];
3660};
3661
3662struct mlx5_ifc_query_fte_out_bits {
3663 u8 status[0x8];
3664 u8 reserved_0[0x18];
3665
3666 u8 syndrome[0x20];
3667
3668 u8 reserved_1[0x1c0];
3669
3670 struct mlx5_ifc_flow_context_bits flow_context;
3671};
3672
3673struct mlx5_ifc_query_fte_in_bits {
3674 u8 opcode[0x10];
3675 u8 reserved_0[0x10];
3676
3677 u8 reserved_1[0x10];
3678 u8 op_mod[0x10];
3679
3680 u8 reserved_2[0x40];
3681
3682 u8 table_type[0x8];
3683 u8 reserved_3[0x18];
3684
3685 u8 reserved_4[0x8];
3686 u8 table_id[0x18];
3687
3688 u8 reserved_5[0x40];
3689
3690 u8 flow_index[0x20];
3691
3692 u8 reserved_6[0xe0];
3693};
3694
3695enum {
3696 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3697 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3698 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3699};
3700
3701struct mlx5_ifc_query_flow_group_out_bits {
3702 u8 status[0x8];
3703 u8 reserved_0[0x18];
3704
3705 u8 syndrome[0x20];
3706
3707 u8 reserved_1[0xa0];
3708
3709 u8 start_flow_index[0x20];
3710
3711 u8 reserved_2[0x20];
3712
3713 u8 end_flow_index[0x20];
3714
3715 u8 reserved_3[0xa0];
3716
3717 u8 reserved_4[0x18];
3718 u8 match_criteria_enable[0x8];
3719
3720 struct mlx5_ifc_fte_match_param_bits match_criteria;
3721
3722 u8 reserved_5[0xe00];
3723};
3724
3725struct mlx5_ifc_query_flow_group_in_bits {
3726 u8 opcode[0x10];
3727 u8 reserved_0[0x10];
3728
3729 u8 reserved_1[0x10];
3730 u8 op_mod[0x10];
3731
3732 u8 reserved_2[0x40];
3733
3734 u8 table_type[0x8];
3735 u8 reserved_3[0x18];
3736
3737 u8 reserved_4[0x8];
3738 u8 table_id[0x18];
3739
3740 u8 group_id[0x20];
3741
3742 u8 reserved_5[0x120];
3743};
3744
3745struct mlx5_ifc_query_eq_out_bits {
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]3746 u8 status[0x8];
3747 u8 reserved_0[0x18];
3748
3749 u8 syndrome[0x20];
3750
3751 u8 reserved_1[0x40];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]3752
3753 struct mlx5_ifc_eqc_bits eq_context_entry;
3754
3755 u8 reserved_2[0x40];
3756
3757 u8 event_bitmask[0x40];
3758
3759 u8 reserved_3[0x580];
3760
3761 u8 pas[0][0x40];
3762};
3763
3764struct mlx5_ifc_query_eq_in_bits {
3765 u8 opcode[0x10];
3766 u8 reserved_0[0x10];
3767
3768 u8 reserved_1[0x10];
3769 u8 op_mod[0x10];
3770
3771 u8 reserved_2[0x18];
3772 u8 eq_number[0x8];
3773
3774 u8 reserved_3[0x20];
3775};
3776
3777struct mlx5_ifc_query_dct_out_bits {
3778 u8 status[0x8];
3779 u8 reserved_0[0x18];
3780
3781 u8 syndrome[0x20];
3782
3783 u8 reserved_1[0x40];
3784
3785 struct mlx5_ifc_dctc_bits dct_context_entry;
3786
3787 u8 reserved_2[0x180];
3788};
3789
3790struct mlx5_ifc_query_dct_in_bits {
3791 u8 opcode[0x10];
3792 u8 reserved_0[0x10];
3793
3794 u8 reserved_1[0x10];
3795 u8 op_mod[0x10];
3796
3797 u8 reserved_2[0x8];
3798 u8 dctn[0x18];
3799
3800 u8 reserved_3[0x20];
3801};
3802
3803struct mlx5_ifc_query_cq_out_bits {
3804 u8 status[0x8];
3805 u8 reserved_0[0x18];
3806
3807 u8 syndrome[0x20];
3808
3809 u8 reserved_1[0x40];
3810
3811 struct mlx5_ifc_cqc_bits cq_context;
3812
3813 u8 reserved_2[0x600];
3814
3815 u8 pas[0][0x40];
3816};
3817
3818struct mlx5_ifc_query_cq_in_bits {
3819 u8 opcode[0x10];
3820 u8 reserved_0[0x10];
3821
3822 u8 reserved_1[0x10];
3823 u8 op_mod[0x10];
3824
3825 u8 reserved_2[0x8];
3826 u8 cqn[0x18];
3827
3828 u8 reserved_3[0x20];
3829};
3830
3831struct mlx5_ifc_query_cong_status_out_bits {
3832 u8 status[0x8];
3833 u8 reserved_0[0x18];
3834
3835 u8 syndrome[0x20];
3836
3837 u8 reserved_1[0x20];
3838
3839 u8 enable[0x1];
3840 u8 tag_enable[0x1];
3841 u8 reserved_2[0x1e];
3842};
3843
3844struct mlx5_ifc_query_cong_status_in_bits {
3845 u8 opcode[0x10];
3846 u8 reserved_0[0x10];
3847
3848 u8 reserved_1[0x10];
3849 u8 op_mod[0x10];
3850
3851 u8 reserved_2[0x18];
3852 u8 priority[0x4];
3853 u8 cong_protocol[0x4];
3854
3855 u8 reserved_3[0x20];
3856};
3857
3858struct mlx5_ifc_query_cong_statistics_out_bits {
3859 u8 status[0x8];
3860 u8 reserved_0[0x18];
3861
3862 u8 syndrome[0x20];
3863
3864 u8 reserved_1[0x40];
3865
3866 u8 cur_flows[0x20];
3867
3868 u8 sum_flows[0x20];
3869
3870 u8 cnp_ignored_high[0x20];
3871
3872 u8 cnp_ignored_low[0x20];
3873
3874 u8 cnp_handled_high[0x20];
3875
3876 u8 cnp_handled_low[0x20];
3877
3878 u8 reserved_2[0x100];
3879
3880 u8 time_stamp_high[0x20];
3881
3882 u8 time_stamp_low[0x20];
3883
3884 u8 accumulators_period[0x20];
3885
3886 u8 ecn_marked_roce_packets_high[0x20];
3887
3888 u8 ecn_marked_roce_packets_low[0x20];
3889
3890 u8 cnps_sent_high[0x20];
3891
3892 u8 cnps_sent_low[0x20];
3893
3894 u8 reserved_3[0x560];
3895};
3896
3897struct mlx5_ifc_query_cong_statistics_in_bits {
3898 u8 opcode[0x10];
3899 u8 reserved_0[0x10];
3900
3901 u8 reserved_1[0x10];
3902 u8 op_mod[0x10];
3903
3904 u8 clear[0x1];
3905 u8 reserved_2[0x1f];
3906
3907 u8 reserved_3[0x20];
3908};
3909
3910struct mlx5_ifc_query_cong_params_out_bits {
3911 u8 status[0x8];
3912 u8 reserved_0[0x18];
3913
3914 u8 syndrome[0x20];
3915
3916 u8 reserved_1[0x40];
3917
3918 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
3919};
3920
3921struct mlx5_ifc_query_cong_params_in_bits {
3922 u8 opcode[0x10];
3923 u8 reserved_0[0x10];
3924
3925 u8 reserved_1[0x10];
3926 u8 op_mod[0x10];
3927
3928 u8 reserved_2[0x1c];
3929 u8 cong_protocol[0x4];
3930
3931 u8 reserved_3[0x20];
3932};
3933
3934struct mlx5_ifc_query_adapter_out_bits {
3935 u8 status[0x8];
3936 u8 reserved_0[0x18];
3937
3938 u8 syndrome[0x20];
3939
3940 u8 reserved_1[0x40];
3941
3942 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
3943};
3944
3945struct mlx5_ifc_query_adapter_in_bits {
3946 u8 opcode[0x10];
3947 u8 reserved_0[0x10];
3948
3949 u8 reserved_1[0x10];
3950 u8 op_mod[0x10];
3951
3952 u8 reserved_2[0x40];
3953};
3954
3955struct mlx5_ifc_qp_2rst_out_bits {
3956 u8 status[0x8];
3957 u8 reserved_0[0x18];
3958
3959 u8 syndrome[0x20];
3960
3961 u8 reserved_1[0x40];
3962};
3963
3964struct mlx5_ifc_qp_2rst_in_bits {
3965 u8 opcode[0x10];
3966 u8 reserved_0[0x10];
3967
3968 u8 reserved_1[0x10];
3969 u8 op_mod[0x10];
3970
3971 u8 reserved_2[0x8];
3972 u8 qpn[0x18];
3973
3974 u8 reserved_3[0x20];
3975};
3976
3977struct mlx5_ifc_qp_2err_out_bits {
3978 u8 status[0x8];
3979 u8 reserved_0[0x18];
3980
3981 u8 syndrome[0x20];
3982
3983 u8 reserved_1[0x40];
3984};
3985
3986struct mlx5_ifc_qp_2err_in_bits {
3987 u8 opcode[0x10];
3988 u8 reserved_0[0x10];
3989
3990 u8 reserved_1[0x10];
3991 u8 op_mod[0x10];
3992
3993 u8 reserved_2[0x8];
3994 u8 qpn[0x18];
3995
3996 u8 reserved_3[0x20];
3997};
3998
3999struct mlx5_ifc_page_fault_resume_out_bits {
4000 u8 status[0x8];
4001 u8 reserved_0[0x18];
4002
4003 u8 syndrome[0x20];
4004
4005 u8 reserved_1[0x40];
4006};
4007
4008struct mlx5_ifc_page_fault_resume_in_bits {
4009 u8 opcode[0x10];
4010 u8 reserved_0[0x10];
4011
4012 u8 reserved_1[0x10];
4013 u8 op_mod[0x10];
4014
4015 u8 error[0x1];
4016 u8 reserved_2[0x4];
4017 u8 rdma[0x1];
4018 u8 read_write[0x1];
4019 u8 req_res[0x1];
4020 u8 qpn[0x18];
4021
4022 u8 reserved_3[0x20];
4023};
4024
4025struct mlx5_ifc_nop_out_bits {
4026 u8 status[0x8];
4027 u8 reserved_0[0x18];
4028
4029 u8 syndrome[0x20];
4030
4031 u8 reserved_1[0x40];
4032};
4033
4034struct mlx5_ifc_nop_in_bits {
4035 u8 opcode[0x10];
4036 u8 reserved_0[0x10];
4037
4038 u8 reserved_1[0x10];
4039 u8 op_mod[0x10];
4040
4041 u8 reserved_2[0x40];
4042};
4043
4044struct mlx5_ifc_modify_vport_state_out_bits {
4045 u8 status[0x8];
4046 u8 reserved_0[0x18];
4047
4048 u8 syndrome[0x20];
4049
4050 u8 reserved_1[0x40];
4051};
4052
4053struct mlx5_ifc_modify_vport_state_in_bits {
4054 u8 opcode[0x10];
4055 u8 reserved_0[0x10];
4056
4057 u8 reserved_1[0x10];
4058 u8 op_mod[0x10];
4059
4060 u8 other_vport[0x1];
4061 u8 reserved_2[0xf];
4062 u8 vport_number[0x10];
4063
4064 u8 reserved_3[0x18];
4065 u8 admin_state[0x4];
4066 u8 reserved_4[0x4];
4067};
4068
4069struct mlx5_ifc_modify_tis_out_bits {
4070 u8 status[0x8];
4071 u8 reserved_0[0x18];
4072
4073 u8 syndrome[0x20];
4074
4075 u8 reserved_1[0x40];
4076};
4077
4078struct mlx5_ifc_modify_tis_in_bits {
4079 u8 opcode[0x10];
4080 u8 reserved_0[0x10];
4081
4082 u8 reserved_1[0x10];
4083 u8 op_mod[0x10];
4084
4085 u8 reserved_2[0x8];
4086 u8 tisn[0x18];
4087
4088 u8 reserved_3[0x20];
4089
4090 u8 modify_bitmask[0x40];
4091
4092 u8 reserved_4[0x40];
4093
4094 struct mlx5_ifc_tisc_bits ctx;
4095};
4096
Achiad Shochatd9eea402015-08-04 14:05:42 +0300[diff] [blame]4097struct mlx5_ifc_modify_tir_bitmask_bits {
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]4098 u8 reserved_0[0x20];
Achiad Shochatd9eea402015-08-04 14:05:42 +0300[diff] [blame]4099
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]4100 u8 reserved_1[0x1b];
4101 u8 self_lb_en[0x1];
4102 u8 reserved_2[0x3];
Achiad Shochatd9eea402015-08-04 14:05:42 +0300[diff] [blame]4103 u8 lro[0x1];
4104};
4105
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]4106struct mlx5_ifc_modify_tir_out_bits {
4107 u8 status[0x8];
4108 u8 reserved_0[0x18];
4109
4110 u8 syndrome[0x20];
4111
4112 u8 reserved_1[0x40];
4113};
4114
4115struct mlx5_ifc_modify_tir_in_bits {
4116 u8 opcode[0x10];
4117 u8 reserved_0[0x10];
4118
4119 u8 reserved_1[0x10];
4120 u8 op_mod[0x10];
4121
4122 u8 reserved_2[0x8];
4123 u8 tirn[0x18];
4124
4125 u8 reserved_3[0x20];
4126
Achiad Shochatd9eea402015-08-04 14:05:42 +0300[diff] [blame]4127 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]4128
4129 u8 reserved_4[0x40];
4130
4131 struct mlx5_ifc_tirc_bits ctx;
4132};
4133
4134struct mlx5_ifc_modify_sq_out_bits {
4135 u8 status[0x8];
4136 u8 reserved_0[0x18];
4137
4138 u8 syndrome[0x20];
4139
4140 u8 reserved_1[0x40];
4141};
4142
4143struct mlx5_ifc_modify_sq_in_bits {
4144 u8 opcode[0x10];
4145 u8 reserved_0[0x10];
4146
4147 u8 reserved_1[0x10];
4148 u8 op_mod[0x10];
4149
4150 u8 sq_state[0x4];
4151 u8 reserved_2[0x4];
4152 u8 sqn[0x18];
4153
4154 u8 reserved_3[0x20];
4155
4156 u8 modify_bitmask[0x40];
4157
4158 u8 reserved_4[0x40];
4159
4160 struct mlx5_ifc_sqc_bits ctx;
4161};
4162
4163struct mlx5_ifc_modify_rqt_out_bits {
4164 u8 status[0x8];
4165 u8 reserved_0[0x18];
4166
4167 u8 syndrome[0x20];
4168
4169 u8 reserved_1[0x40];
4170};
4171
Achiad Shochat5c503682015-08-04 14:05:43 +0300[diff] [blame]4172struct mlx5_ifc_rqt_bitmask_bits {
4173 u8 reserved[0x20];
4174
4175 u8 reserved1[0x1f];
4176 u8 rqn_list[0x1];
4177};
4178
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]4179struct mlx5_ifc_modify_rqt_in_bits {
4180 u8 opcode[0x10];
4181 u8 reserved_0[0x10];
4182
4183 u8 reserved_1[0x10];
4184 u8 op_mod[0x10];
4185
4186 u8 reserved_2[0x8];
4187 u8 rqtn[0x18];
4188
4189 u8 reserved_3[0x20];
4190
Achiad Shochat5c503682015-08-04 14:05:43 +0300[diff] [blame]4191 struct mlx5_ifc_rqt_bitmask_bits bitmask;
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]4192
4193 u8 reserved_4[0x40];
4194
4195 struct mlx5_ifc_rqtc_bits ctx;
4196};
4197
4198struct mlx5_ifc_modify_rq_out_bits {
4199 u8 status[0x8];
4200 u8 reserved_0[0x18];
4201
4202 u8 syndrome[0x20];
4203
4204 u8 reserved_1[0x40];
4205};
4206
4207struct mlx5_ifc_modify_rq_in_bits {
4208 u8 opcode[0x10];
4209 u8 reserved_0[0x10];
4210
4211 u8 reserved_1[0x10];
4212 u8 op_mod[0x10];
4213
4214 u8 rq_state[0x4];
4215 u8 reserved_2[0x4];
4216 u8 rqn[0x18];
4217
4218 u8 reserved_3[0x20];
4219
4220 u8 modify_bitmask[0x40];
4221
4222 u8 reserved_4[0x40];
4223
4224 struct mlx5_ifc_rqc_bits ctx;
4225};
4226
4227struct mlx5_ifc_modify_rmp_out_bits {
4228 u8 status[0x8];
4229 u8 reserved_0[0x18];
4230
4231 u8 syndrome[0x20];
4232
4233 u8 reserved_1[0x40];
4234};
4235
Haggai Abramonvsky01949d02015-06-04 19:30:38 +0300[diff] [blame]4236struct mlx5_ifc_rmp_bitmask_bits {
4237 u8 reserved[0x20];
4238
4239 u8 reserved1[0x1f];
4240 u8 lwm[0x1];
4241};
4242
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]4243struct mlx5_ifc_modify_rmp_in_bits {
4244 u8 opcode[0x10];
4245 u8 reserved_0[0x10];
4246
4247 u8 reserved_1[0x10];
4248 u8 op_mod[0x10];
4249
4250 u8 rmp_state[0x4];
4251 u8 reserved_2[0x4];
4252 u8 rmpn[0x18];
4253
4254 u8 reserved_3[0x20];
4255
Haggai Abramonvsky01949d02015-06-04 19:30:38 +0300[diff] [blame]4256 struct mlx5_ifc_rmp_bitmask_bits bitmask;
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]4257
4258 u8 reserved_4[0x40];
4259
4260 struct mlx5_ifc_rmpc_bits ctx;
4261};
4262
4263struct mlx5_ifc_modify_nic_vport_context_out_bits {
4264 u8 status[0x8];
4265 u8 reserved_0[0x18];
4266
4267 u8 syndrome[0x20];
4268
4269 u8 reserved_1[0x40];
4270};
4271
4272struct mlx5_ifc_modify_nic_vport_field_select_bits {
Saeed Mahameedd82b7312015-12-01 18:03:14 +0200[diff] [blame]4273 u8 reserved_0[0x19];
4274 u8 mtu[0x1];
4275 u8 change_event[0x1];
4276 u8 promisc[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]4277 u8 permanent_address[0x1];
4278 u8 addresses_list[0x1];
4279 u8 roce_en[0x1];
4280 u8 reserved_1[0x1];
4281};
4282
4283struct mlx5_ifc_modify_nic_vport_context_in_bits {
4284 u8 opcode[0x10];
4285 u8 reserved_0[0x10];
4286
4287 u8 reserved_1[0x10];
4288 u8 op_mod[0x10];
4289
4290 u8 other_vport[0x1];
4291 u8 reserved_2[0xf];
4292 u8 vport_number[0x10];
4293
4294 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4295
4296 u8 reserved_3[0x780];
4297
4298 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4299};
4300
4301struct mlx5_ifc_modify_hca_vport_context_out_bits {
4302 u8 status[0x8];
4303 u8 reserved_0[0x18];
4304
4305 u8 syndrome[0x20];
4306
4307 u8 reserved_1[0x40];
4308};
4309
4310struct mlx5_ifc_modify_hca_vport_context_in_bits {
4311 u8 opcode[0x10];
4312 u8 reserved_0[0x10];
4313
4314 u8 reserved_1[0x10];
4315 u8 op_mod[0x10];
4316
4317 u8 other_vport[0x1];
Majd Dibbiny707c4602015-06-04 19:30:41 +0300[diff] [blame]4318 u8 reserved_2[0xb];
4319 u8 port_num[0x4];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]4320 u8 vport_number[0x10];
4321
4322 u8 reserved_3[0x20];
4323
4324 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4325};
4326
4327struct mlx5_ifc_modify_cq_out_bits {
4328 u8 status[0x8];
4329 u8 reserved_0[0x18];
4330
4331 u8 syndrome[0x20];
4332
4333 u8 reserved_1[0x40];
4334};
4335
4336enum {
4337 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4338 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4339};
4340
4341struct mlx5_ifc_modify_cq_in_bits {
4342 u8 opcode[0x10];
4343 u8 reserved_0[0x10];
4344
4345 u8 reserved_1[0x10];
4346 u8 op_mod[0x10];
4347
4348 u8 reserved_2[0x8];
4349 u8 cqn[0x18];
4350
4351 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4352
4353 struct mlx5_ifc_cqc_bits cq_context;
4354
4355 u8 reserved_3[0x600];
4356
4357 u8 pas[0][0x40];
4358};
4359
4360struct mlx5_ifc_modify_cong_status_out_bits {
4361 u8 status[0x8];
4362 u8 reserved_0[0x18];
4363
4364 u8 syndrome[0x20];
4365
4366 u8 reserved_1[0x40];
4367};
4368
4369struct mlx5_ifc_modify_cong_status_in_bits {
4370 u8 opcode[0x10];
4371 u8 reserved_0[0x10];
4372
4373 u8 reserved_1[0x10];
4374 u8 op_mod[0x10];
4375
4376 u8 reserved_2[0x18];
4377 u8 priority[0x4];
4378 u8 cong_protocol[0x4];
4379
4380 u8 enable[0x1];
4381 u8 tag_enable[0x1];
4382 u8 reserved_3[0x1e];
4383};
4384
4385struct mlx5_ifc_modify_cong_params_out_bits {
4386 u8 status[0x8];
4387 u8 reserved_0[0x18];
4388
4389 u8 syndrome[0x20];
4390
4391 u8 reserved_1[0x40];
4392};
4393
4394struct mlx5_ifc_modify_cong_params_in_bits {
4395 u8 opcode[0x10];
4396 u8 reserved_0[0x10];
4397
4398 u8 reserved_1[0x10];
4399 u8 op_mod[0x10];
4400
4401 u8 reserved_2[0x1c];
4402 u8 cong_protocol[0x4];
4403
4404 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4405
4406 u8 reserved_3[0x80];
4407
4408 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4409};
4410
4411struct mlx5_ifc_manage_pages_out_bits {
4412 u8 status[0x8];
4413 u8 reserved_0[0x18];
4414
4415 u8 syndrome[0x20];
4416
4417 u8 output_num_entries[0x20];
4418
4419 u8 reserved_1[0x20];
4420
4421 u8 pas[0][0x40];
4422};
4423
4424enum {
4425 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4426 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4427 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4428};
4429
4430struct mlx5_ifc_manage_pages_in_bits {
4431 u8 opcode[0x10];
4432 u8 reserved_0[0x10];
4433
4434 u8 reserved_1[0x10];
4435 u8 op_mod[0x10];
4436
4437 u8 reserved_2[0x10];
4438 u8 function_id[0x10];
4439
4440 u8 input_num_entries[0x20];
4441
4442 u8 pas[0][0x40];
4443};
4444
4445struct mlx5_ifc_mad_ifc_out_bits {
4446 u8 status[0x8];
4447 u8 reserved_0[0x18];
4448
4449 u8 syndrome[0x20];
4450
4451 u8 reserved_1[0x40];
4452
4453 u8 response_mad_packet[256][0x8];
4454};
4455
4456struct mlx5_ifc_mad_ifc_in_bits {
4457 u8 opcode[0x10];
4458 u8 reserved_0[0x10];
4459
4460 u8 reserved_1[0x10];
4461 u8 op_mod[0x10];
4462
4463 u8 remote_lid[0x10];
4464 u8 reserved_2[0x8];
4465 u8 port[0x8];
4466
4467 u8 reserved_3[0x20];
4468
4469 u8 mad[256][0x8];
4470};
4471
4472struct mlx5_ifc_init_hca_out_bits {
4473 u8 status[0x8];
4474 u8 reserved_0[0x18];
4475
4476 u8 syndrome[0x20];
4477
4478 u8 reserved_1[0x40];
4479};
4480
4481struct mlx5_ifc_init_hca_in_bits {
4482 u8 opcode[0x10];
4483 u8 reserved_0[0x10];
4484
4485 u8 reserved_1[0x10];
4486 u8 op_mod[0x10];
4487
4488 u8 reserved_2[0x40];
4489};
4490
4491struct mlx5_ifc_init2rtr_qp_out_bits {
4492 u8 status[0x8];
4493 u8 reserved_0[0x18];
4494
4495 u8 syndrome[0x20];
4496
4497 u8 reserved_1[0x40];
4498};
4499
4500struct mlx5_ifc_init2rtr_qp_in_bits {
4501 u8 opcode[0x10];
4502 u8 reserved_0[0x10];
4503
4504 u8 reserved_1[0x10];
4505 u8 op_mod[0x10];
4506
4507 u8 reserved_2[0x8];
4508 u8 qpn[0x18];
4509
4510 u8 reserved_3[0x20];
4511
4512 u8 opt_param_mask[0x20];
4513
4514 u8 reserved_4[0x20];
4515
4516 struct mlx5_ifc_qpc_bits qpc;
4517
4518 u8 reserved_5[0x80];
4519};
4520
4521struct mlx5_ifc_init2init_qp_out_bits {
4522 u8 status[0x8];
4523 u8 reserved_0[0x18];
4524
4525 u8 syndrome[0x20];
4526
4527 u8 reserved_1[0x40];
4528};
4529
4530struct mlx5_ifc_init2init_qp_in_bits {
4531 u8 opcode[0x10];
4532 u8 reserved_0[0x10];
4533
4534 u8 reserved_1[0x10];
4535 u8 op_mod[0x10];
4536
4537 u8 reserved_2[0x8];
4538 u8 qpn[0x18];
4539
4540 u8 reserved_3[0x20];
4541
4542 u8 opt_param_mask[0x20];
4543
4544 u8 reserved_4[0x20];
4545
4546 struct mlx5_ifc_qpc_bits qpc;
4547
4548 u8 reserved_5[0x80];
4549};
4550
4551struct mlx5_ifc_get_dropped_packet_log_out_bits {
4552 u8 status[0x8];
4553 u8 reserved_0[0x18];
4554
4555 u8 syndrome[0x20];
4556
4557 u8 reserved_1[0x40];
4558
4559 u8 packet_headers_log[128][0x8];
4560
4561 u8 packet_syndrome[64][0x8];
4562};
4563
4564struct mlx5_ifc_get_dropped_packet_log_in_bits {
4565 u8 opcode[0x10];
4566 u8 reserved_0[0x10];
4567
4568 u8 reserved_1[0x10];
4569 u8 op_mod[0x10];
4570
4571 u8 reserved_2[0x40];
4572};
4573
4574struct mlx5_ifc_gen_eqe_in_bits {
4575 u8 opcode[0x10];
4576 u8 reserved_0[0x10];
4577
4578 u8 reserved_1[0x10];
4579 u8 op_mod[0x10];
4580
4581 u8 reserved_2[0x18];
4582 u8 eq_number[0x8];
4583
4584 u8 reserved_3[0x20];
4585
4586 u8 eqe[64][0x8];
4587};
4588
4589struct mlx5_ifc_gen_eq_out_bits {
4590 u8 status[0x8];
4591 u8 reserved_0[0x18];
4592
4593 u8 syndrome[0x20];
4594
4595 u8 reserved_1[0x40];
4596};
4597
4598struct mlx5_ifc_enable_hca_out_bits {
4599 u8 status[0x8];
4600 u8 reserved_0[0x18];
4601
4602 u8 syndrome[0x20];
4603
4604 u8 reserved_1[0x20];
4605};
4606
4607struct mlx5_ifc_enable_hca_in_bits {
4608 u8 opcode[0x10];
4609 u8 reserved_0[0x10];
4610
4611 u8 reserved_1[0x10];
4612 u8 op_mod[0x10];
4613
4614 u8 reserved_2[0x10];
4615 u8 function_id[0x10];
4616
4617 u8 reserved_3[0x20];
4618};
4619
4620struct mlx5_ifc_drain_dct_out_bits {
4621 u8 status[0x8];
4622 u8 reserved_0[0x18];
4623
4624 u8 syndrome[0x20];
4625
4626 u8 reserved_1[0x40];
4627};
4628
4629struct mlx5_ifc_drain_dct_in_bits {
4630 u8 opcode[0x10];
4631 u8 reserved_0[0x10];
4632
4633 u8 reserved_1[0x10];
4634 u8 op_mod[0x10];
4635
4636 u8 reserved_2[0x8];
4637 u8 dctn[0x18];
4638
4639 u8 reserved_3[0x20];
4640};
4641
4642struct mlx5_ifc_disable_hca_out_bits {
4643 u8 status[0x8];
4644 u8 reserved_0[0x18];
4645
4646 u8 syndrome[0x20];
4647
4648 u8 reserved_1[0x20];
4649};
4650
4651struct mlx5_ifc_disable_hca_in_bits {
4652 u8 opcode[0x10];
4653 u8 reserved_0[0x10];
4654
4655 u8 reserved_1[0x10];
4656 u8 op_mod[0x10];
4657
4658 u8 reserved_2[0x10];
4659 u8 function_id[0x10];
4660
4661 u8 reserved_3[0x20];
4662};
4663
4664struct mlx5_ifc_detach_from_mcg_out_bits {
4665 u8 status[0x8];
4666 u8 reserved_0[0x18];
4667
4668 u8 syndrome[0x20];
4669
4670 u8 reserved_1[0x40];
4671};
4672
4673struct mlx5_ifc_detach_from_mcg_in_bits {
4674 u8 opcode[0x10];
4675 u8 reserved_0[0x10];
4676
4677 u8 reserved_1[0x10];
4678 u8 op_mod[0x10];
4679
4680 u8 reserved_2[0x8];
4681 u8 qpn[0x18];
4682
4683 u8 reserved_3[0x20];
4684
4685 u8 multicast_gid[16][0x8];
4686};
4687
4688struct mlx5_ifc_destroy_xrc_srq_out_bits {
4689 u8 status[0x8];
4690 u8 reserved_0[0x18];
4691
4692 u8 syndrome[0x20];
4693
4694 u8 reserved_1[0x40];
4695};
4696
4697struct mlx5_ifc_destroy_xrc_srq_in_bits {
4698 u8 opcode[0x10];
4699 u8 reserved_0[0x10];
4700
4701 u8 reserved_1[0x10];
4702 u8 op_mod[0x10];
4703
4704 u8 reserved_2[0x8];
4705 u8 xrc_srqn[0x18];
4706
4707 u8 reserved_3[0x20];
4708};
4709
4710struct mlx5_ifc_destroy_tis_out_bits {
4711 u8 status[0x8];
4712 u8 reserved_0[0x18];
4713
4714 u8 syndrome[0x20];
4715
4716 u8 reserved_1[0x40];
4717};
4718
4719struct mlx5_ifc_destroy_tis_in_bits {
4720 u8 opcode[0x10];
4721 u8 reserved_0[0x10];
4722
4723 u8 reserved_1[0x10];
4724 u8 op_mod[0x10];
4725
4726 u8 reserved_2[0x8];
4727 u8 tisn[0x18];
4728
4729 u8 reserved_3[0x20];
4730};
4731
4732struct mlx5_ifc_destroy_tir_out_bits {
4733 u8 status[0x8];
4734 u8 reserved_0[0x18];
4735
4736 u8 syndrome[0x20];
4737
4738 u8 reserved_1[0x40];
4739};
4740
4741struct mlx5_ifc_destroy_tir_in_bits {
4742 u8 opcode[0x10];
4743 u8 reserved_0[0x10];
4744
4745 u8 reserved_1[0x10];
4746 u8 op_mod[0x10];
4747
4748 u8 reserved_2[0x8];
4749 u8 tirn[0x18];
4750
4751 u8 reserved_3[0x20];
4752};
4753
4754struct mlx5_ifc_destroy_srq_out_bits {
4755 u8 status[0x8];
4756 u8 reserved_0[0x18];
4757
4758 u8 syndrome[0x20];
4759
4760 u8 reserved_1[0x40];
4761};
4762
4763struct mlx5_ifc_destroy_srq_in_bits {
4764 u8 opcode[0x10];
4765 u8 reserved_0[0x10];
4766
4767 u8 reserved_1[0x10];
4768 u8 op_mod[0x10];
4769
4770 u8 reserved_2[0x8];
4771 u8 srqn[0x18];
4772
4773 u8 reserved_3[0x20];
4774};
4775
4776struct mlx5_ifc_destroy_sq_out_bits {
4777 u8 status[0x8];
4778 u8 reserved_0[0x18];
4779
4780 u8 syndrome[0x20];
4781
4782 u8 reserved_1[0x40];
4783};
4784
4785struct mlx5_ifc_destroy_sq_in_bits {
4786 u8 opcode[0x10];
4787 u8 reserved_0[0x10];
4788
4789 u8 reserved_1[0x10];
4790 u8 op_mod[0x10];
4791
4792 u8 reserved_2[0x8];
4793 u8 sqn[0x18];
4794
4795 u8 reserved_3[0x20];
4796};
4797
4798struct mlx5_ifc_destroy_rqt_out_bits {
4799 u8 status[0x8];
4800 u8 reserved_0[0x18];
4801
4802 u8 syndrome[0x20];
4803
4804 u8 reserved_1[0x40];
4805};
4806
4807struct mlx5_ifc_destroy_rqt_in_bits {
4808 u8 opcode[0x10];
4809 u8 reserved_0[0x10];
4810
4811 u8 reserved_1[0x10];
4812 u8 op_mod[0x10];
4813
4814 u8 reserved_2[0x8];
4815 u8 rqtn[0x18];
4816
4817 u8 reserved_3[0x20];
4818};
4819
4820struct mlx5_ifc_destroy_rq_out_bits {
4821 u8 status[0x8];
4822 u8 reserved_0[0x18];
4823
4824 u8 syndrome[0x20];
4825
4826 u8 reserved_1[0x40];
4827};
4828
4829struct mlx5_ifc_destroy_rq_in_bits {
4830 u8 opcode[0x10];
4831 u8 reserved_0[0x10];
4832
4833 u8 reserved_1[0x10];
4834 u8 op_mod[0x10];
4835
4836 u8 reserved_2[0x8];
4837 u8 rqn[0x18];
4838
4839 u8 reserved_3[0x20];
4840};
4841
4842struct mlx5_ifc_destroy_rmp_out_bits {
4843 u8 status[0x8];
4844 u8 reserved_0[0x18];
4845
4846 u8 syndrome[0x20];
4847
4848 u8 reserved_1[0x40];
4849};
4850
4851struct mlx5_ifc_destroy_rmp_in_bits {
4852 u8 opcode[0x10];
4853 u8 reserved_0[0x10];
4854
4855 u8 reserved_1[0x10];
4856 u8 op_mod[0x10];
4857
4858 u8 reserved_2[0x8];
4859 u8 rmpn[0x18];
4860
4861 u8 reserved_3[0x20];
4862};
4863
4864struct mlx5_ifc_destroy_qp_out_bits {
4865 u8 status[0x8];
4866 u8 reserved_0[0x18];
4867
4868 u8 syndrome[0x20];
4869
4870 u8 reserved_1[0x40];
4871};
4872
4873struct mlx5_ifc_destroy_qp_in_bits {
4874 u8 opcode[0x10];
4875 u8 reserved_0[0x10];
4876
4877 u8 reserved_1[0x10];
4878 u8 op_mod[0x10];
4879
4880 u8 reserved_2[0x8];
4881 u8 qpn[0x18];
4882
4883 u8 reserved_3[0x20];
4884};
4885
4886struct mlx5_ifc_destroy_psv_out_bits {
4887 u8 status[0x8];
4888 u8 reserved_0[0x18];
4889
4890 u8 syndrome[0x20];
4891
4892 u8 reserved_1[0x40];
4893};
4894
4895struct mlx5_ifc_destroy_psv_in_bits {
4896 u8 opcode[0x10];
4897 u8 reserved_0[0x10];
4898
4899 u8 reserved_1[0x10];
4900 u8 op_mod[0x10];
4901
4902 u8 reserved_2[0x8];
4903 u8 psvn[0x18];
4904
4905 u8 reserved_3[0x20];
4906};
4907
4908struct mlx5_ifc_destroy_mkey_out_bits {
4909 u8 status[0x8];
4910 u8 reserved_0[0x18];
4911
4912 u8 syndrome[0x20];
4913
4914 u8 reserved_1[0x40];
4915};
4916
4917struct mlx5_ifc_destroy_mkey_in_bits {
4918 u8 opcode[0x10];
4919 u8 reserved_0[0x10];
4920
4921 u8 reserved_1[0x10];
4922 u8 op_mod[0x10];
4923
4924 u8 reserved_2[0x8];
4925 u8 mkey_index[0x18];
4926
4927 u8 reserved_3[0x20];
4928};
4929
4930struct mlx5_ifc_destroy_flow_table_out_bits {
4931 u8 status[0x8];
4932 u8 reserved_0[0x18];
4933
4934 u8 syndrome[0x20];
4935
4936 u8 reserved_1[0x40];
4937};
4938
4939struct mlx5_ifc_destroy_flow_table_in_bits {
4940 u8 opcode[0x10];
4941 u8 reserved_0[0x10];
4942
4943 u8 reserved_1[0x10];
4944 u8 op_mod[0x10];
4945
4946 u8 reserved_2[0x40];
4947
4948 u8 table_type[0x8];
4949 u8 reserved_3[0x18];
4950
4951 u8 reserved_4[0x8];
4952 u8 table_id[0x18];
4953
4954 u8 reserved_5[0x140];
4955};
4956
4957struct mlx5_ifc_destroy_flow_group_out_bits {
4958 u8 status[0x8];
4959 u8 reserved_0[0x18];
4960
4961 u8 syndrome[0x20];
4962
4963 u8 reserved_1[0x40];
4964};
4965
4966struct mlx5_ifc_destroy_flow_group_in_bits {
4967 u8 opcode[0x10];
4968 u8 reserved_0[0x10];
4969
4970 u8 reserved_1[0x10];
4971 u8 op_mod[0x10];
4972
4973 u8 reserved_2[0x40];
4974
4975 u8 table_type[0x8];
4976 u8 reserved_3[0x18];
4977
4978 u8 reserved_4[0x8];
4979 u8 table_id[0x18];
4980
4981 u8 group_id[0x20];
4982
4983 u8 reserved_5[0x120];
4984};
4985
4986struct mlx5_ifc_destroy_eq_out_bits {
4987 u8 status[0x8];
4988 u8 reserved_0[0x18];
4989
4990 u8 syndrome[0x20];
4991
4992 u8 reserved_1[0x40];
4993};
4994
4995struct mlx5_ifc_destroy_eq_in_bits {
4996 u8 opcode[0x10];
4997 u8 reserved_0[0x10];
4998
4999 u8 reserved_1[0x10];
5000 u8 op_mod[0x10];
5001
5002 u8 reserved_2[0x18];
5003 u8 eq_number[0x8];
5004
5005 u8 reserved_3[0x20];
5006};
5007
5008struct mlx5_ifc_destroy_dct_out_bits {
5009 u8 status[0x8];
5010 u8 reserved_0[0x18];
5011
5012 u8 syndrome[0x20];
5013
5014 u8 reserved_1[0x40];
5015};
5016
5017struct mlx5_ifc_destroy_dct_in_bits {
5018 u8 opcode[0x10];
5019 u8 reserved_0[0x10];
5020
5021 u8 reserved_1[0x10];
5022 u8 op_mod[0x10];
5023
5024 u8 reserved_2[0x8];
5025 u8 dctn[0x18];
5026
5027 u8 reserved_3[0x20];
5028};
5029
5030struct mlx5_ifc_destroy_cq_out_bits {
5031 u8 status[0x8];
5032 u8 reserved_0[0x18];
5033
5034 u8 syndrome[0x20];
5035
5036 u8 reserved_1[0x40];
5037};
5038
5039struct mlx5_ifc_destroy_cq_in_bits {
5040 u8 opcode[0x10];
5041 u8 reserved_0[0x10];
5042
5043 u8 reserved_1[0x10];
5044 u8 op_mod[0x10];
5045
5046 u8 reserved_2[0x8];
5047 u8 cqn[0x18];
5048
5049 u8 reserved_3[0x20];
5050};
5051
5052struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5053 u8 status[0x8];
5054 u8 reserved_0[0x18];
5055
5056 u8 syndrome[0x20];
5057
5058 u8 reserved_1[0x40];
5059};
5060
5061struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5062 u8 opcode[0x10];
5063 u8 reserved_0[0x10];
5064
5065 u8 reserved_1[0x10];
5066 u8 op_mod[0x10];
5067
5068 u8 reserved_2[0x20];
5069
5070 u8 reserved_3[0x10];
5071 u8 vxlan_udp_port[0x10];
5072};
5073
5074struct mlx5_ifc_delete_l2_table_entry_out_bits {
5075 u8 status[0x8];
5076 u8 reserved_0[0x18];
5077
5078 u8 syndrome[0x20];
5079
5080 u8 reserved_1[0x40];
5081};
5082
5083struct mlx5_ifc_delete_l2_table_entry_in_bits {
5084 u8 opcode[0x10];
5085 u8 reserved_0[0x10];
5086
5087 u8 reserved_1[0x10];
5088 u8 op_mod[0x10];
5089
5090 u8 reserved_2[0x60];
5091
5092 u8 reserved_3[0x8];
5093 u8 table_index[0x18];
5094
5095 u8 reserved_4[0x140];
5096};
5097
5098struct mlx5_ifc_delete_fte_out_bits {
5099 u8 status[0x8];
5100 u8 reserved_0[0x18];
5101
5102 u8 syndrome[0x20];
5103
5104 u8 reserved_1[0x40];
5105};
5106
5107struct mlx5_ifc_delete_fte_in_bits {
5108 u8 opcode[0x10];
5109 u8 reserved_0[0x10];
5110
5111 u8 reserved_1[0x10];
5112 u8 op_mod[0x10];
5113
5114 u8 reserved_2[0x40];
5115
5116 u8 table_type[0x8];
5117 u8 reserved_3[0x18];
5118
5119 u8 reserved_4[0x8];
5120 u8 table_id[0x18];
5121
5122 u8 reserved_5[0x40];
5123
5124 u8 flow_index[0x20];
5125
5126 u8 reserved_6[0xe0];
5127};
5128
5129struct mlx5_ifc_dealloc_xrcd_out_bits {
5130 u8 status[0x8];
5131 u8 reserved_0[0x18];
5132
5133 u8 syndrome[0x20];
5134
5135 u8 reserved_1[0x40];
5136};
5137
5138struct mlx5_ifc_dealloc_xrcd_in_bits {
5139 u8 opcode[0x10];
5140 u8 reserved_0[0x10];
5141
5142 u8 reserved_1[0x10];
5143 u8 op_mod[0x10];
5144
5145 u8 reserved_2[0x8];
5146 u8 xrcd[0x18];
5147
5148 u8 reserved_3[0x20];
5149};
5150
5151struct mlx5_ifc_dealloc_uar_out_bits {
5152 u8 status[0x8];
5153 u8 reserved_0[0x18];
5154
5155 u8 syndrome[0x20];
5156
5157 u8 reserved_1[0x40];
5158};
5159
5160struct mlx5_ifc_dealloc_uar_in_bits {
5161 u8 opcode[0x10];
5162 u8 reserved_0[0x10];
5163
5164 u8 reserved_1[0x10];
5165 u8 op_mod[0x10];
5166
5167 u8 reserved_2[0x8];
5168 u8 uar[0x18];
5169
5170 u8 reserved_3[0x20];
5171};
5172
5173struct mlx5_ifc_dealloc_transport_domain_out_bits {
5174 u8 status[0x8];
5175 u8 reserved_0[0x18];
5176
5177 u8 syndrome[0x20];
5178
5179 u8 reserved_1[0x40];
5180};
5181
5182struct mlx5_ifc_dealloc_transport_domain_in_bits {
5183 u8 opcode[0x10];
5184 u8 reserved_0[0x10];
5185
5186 u8 reserved_1[0x10];
5187 u8 op_mod[0x10];
5188
5189 u8 reserved_2[0x8];
5190 u8 transport_domain[0x18];
5191
5192 u8 reserved_3[0x20];
5193};
5194
5195struct mlx5_ifc_dealloc_q_counter_out_bits {
5196 u8 status[0x8];
5197 u8 reserved_0[0x18];
5198
5199 u8 syndrome[0x20];
5200
5201 u8 reserved_1[0x40];
5202};
5203
5204struct mlx5_ifc_dealloc_q_counter_in_bits {
5205 u8 opcode[0x10];
5206 u8 reserved_0[0x10];
5207
5208 u8 reserved_1[0x10];
5209 u8 op_mod[0x10];
5210
5211 u8 reserved_2[0x18];
5212 u8 counter_set_id[0x8];
5213
5214 u8 reserved_3[0x20];
5215};
5216
5217struct mlx5_ifc_dealloc_pd_out_bits {
5218 u8 status[0x8];
5219 u8 reserved_0[0x18];
5220
5221 u8 syndrome[0x20];
5222
5223 u8 reserved_1[0x40];
5224};
5225
5226struct mlx5_ifc_dealloc_pd_in_bits {
5227 u8 opcode[0x10];
5228 u8 reserved_0[0x10];
5229
5230 u8 reserved_1[0x10];
5231 u8 op_mod[0x10];
5232
5233 u8 reserved_2[0x8];
5234 u8 pd[0x18];
5235
5236 u8 reserved_3[0x20];
5237};
5238
5239struct mlx5_ifc_create_xrc_srq_out_bits {
5240 u8 status[0x8];
5241 u8 reserved_0[0x18];
5242
5243 u8 syndrome[0x20];
5244
5245 u8 reserved_1[0x8];
5246 u8 xrc_srqn[0x18];
5247
5248 u8 reserved_2[0x20];
5249};
5250
5251struct mlx5_ifc_create_xrc_srq_in_bits {
5252 u8 opcode[0x10];
5253 u8 reserved_0[0x10];
5254
5255 u8 reserved_1[0x10];
5256 u8 op_mod[0x10];
5257
5258 u8 reserved_2[0x40];
5259
5260 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5261
5262 u8 reserved_3[0x600];
5263
5264 u8 pas[0][0x40];
5265};
5266
5267struct mlx5_ifc_create_tis_out_bits {
5268 u8 status[0x8];
5269 u8 reserved_0[0x18];
5270
5271 u8 syndrome[0x20];
5272
5273 u8 reserved_1[0x8];
5274 u8 tisn[0x18];
5275
5276 u8 reserved_2[0x20];
5277};
5278
5279struct mlx5_ifc_create_tis_in_bits {
5280 u8 opcode[0x10];
5281 u8 reserved_0[0x10];
5282
5283 u8 reserved_1[0x10];
5284 u8 op_mod[0x10];
5285
5286 u8 reserved_2[0xc0];
5287
5288 struct mlx5_ifc_tisc_bits ctx;
5289};
5290
5291struct mlx5_ifc_create_tir_out_bits {
5292 u8 status[0x8];
5293 u8 reserved_0[0x18];
5294
5295 u8 syndrome[0x20];
5296
5297 u8 reserved_1[0x8];
5298 u8 tirn[0x18];
5299
5300 u8 reserved_2[0x20];
5301};
5302
5303struct mlx5_ifc_create_tir_in_bits {
5304 u8 opcode[0x10];
5305 u8 reserved_0[0x10];
5306
5307 u8 reserved_1[0x10];
5308 u8 op_mod[0x10];
5309
5310 u8 reserved_2[0xc0];
5311
5312 struct mlx5_ifc_tirc_bits ctx;
5313};
5314
5315struct mlx5_ifc_create_srq_out_bits {
5316 u8 status[0x8];
5317 u8 reserved_0[0x18];
5318
5319 u8 syndrome[0x20];
5320
5321 u8 reserved_1[0x8];
5322 u8 srqn[0x18];
5323
5324 u8 reserved_2[0x20];
5325};
5326
5327struct mlx5_ifc_create_srq_in_bits {
5328 u8 opcode[0x10];
5329 u8 reserved_0[0x10];
5330
5331 u8 reserved_1[0x10];
5332 u8 op_mod[0x10];
5333
5334 u8 reserved_2[0x40];
5335
5336 struct mlx5_ifc_srqc_bits srq_context_entry;
5337
5338 u8 reserved_3[0x600];
5339
5340 u8 pas[0][0x40];
5341};
5342
5343struct mlx5_ifc_create_sq_out_bits {
5344 u8 status[0x8];
5345 u8 reserved_0[0x18];
5346
5347 u8 syndrome[0x20];
5348
5349 u8 reserved_1[0x8];
5350 u8 sqn[0x18];
5351
5352 u8 reserved_2[0x20];
5353};
5354
5355struct mlx5_ifc_create_sq_in_bits {
5356 u8 opcode[0x10];
5357 u8 reserved_0[0x10];
5358
5359 u8 reserved_1[0x10];
5360 u8 op_mod[0x10];
5361
5362 u8 reserved_2[0xc0];
5363
5364 struct mlx5_ifc_sqc_bits ctx;
5365};
5366
5367struct mlx5_ifc_create_rqt_out_bits {
5368 u8 status[0x8];
5369 u8 reserved_0[0x18];
5370
5371 u8 syndrome[0x20];
5372
5373 u8 reserved_1[0x8];
5374 u8 rqtn[0x18];
5375
5376 u8 reserved_2[0x20];
5377};
5378
5379struct mlx5_ifc_create_rqt_in_bits {
5380 u8 opcode[0x10];
5381 u8 reserved_0[0x10];
5382
5383 u8 reserved_1[0x10];
5384 u8 op_mod[0x10];
5385
5386 u8 reserved_2[0xc0];
5387
5388 struct mlx5_ifc_rqtc_bits rqt_context;
5389};
5390
5391struct mlx5_ifc_create_rq_out_bits {
5392 u8 status[0x8];
5393 u8 reserved_0[0x18];
5394
5395 u8 syndrome[0x20];
5396
5397 u8 reserved_1[0x8];
5398 u8 rqn[0x18];
5399
5400 u8 reserved_2[0x20];
5401};
5402
5403struct mlx5_ifc_create_rq_in_bits {
5404 u8 opcode[0x10];
5405 u8 reserved_0[0x10];
5406
5407 u8 reserved_1[0x10];
5408 u8 op_mod[0x10];
5409
5410 u8 reserved_2[0xc0];
5411
5412 struct mlx5_ifc_rqc_bits ctx;
5413};
5414
5415struct mlx5_ifc_create_rmp_out_bits {
5416 u8 status[0x8];
5417 u8 reserved_0[0x18];
5418
5419 u8 syndrome[0x20];
5420
5421 u8 reserved_1[0x8];
5422 u8 rmpn[0x18];
5423
5424 u8 reserved_2[0x20];
5425};
5426
5427struct mlx5_ifc_create_rmp_in_bits {
5428 u8 opcode[0x10];
5429 u8 reserved_0[0x10];
5430
5431 u8 reserved_1[0x10];
5432 u8 op_mod[0x10];
5433
5434 u8 reserved_2[0xc0];
5435
5436 struct mlx5_ifc_rmpc_bits ctx;
5437};
5438
5439struct mlx5_ifc_create_qp_out_bits {
5440 u8 status[0x8];
5441 u8 reserved_0[0x18];
5442
5443 u8 syndrome[0x20];
5444
5445 u8 reserved_1[0x8];
5446 u8 qpn[0x18];
5447
5448 u8 reserved_2[0x20];
5449};
5450
5451struct mlx5_ifc_create_qp_in_bits {
5452 u8 opcode[0x10];
5453 u8 reserved_0[0x10];
5454
5455 u8 reserved_1[0x10];
5456 u8 op_mod[0x10];
5457
5458 u8 reserved_2[0x40];
5459
5460 u8 opt_param_mask[0x20];
5461
5462 u8 reserved_3[0x20];
5463
5464 struct mlx5_ifc_qpc_bits qpc;
5465
5466 u8 reserved_4[0x80];
5467
5468 u8 pas[0][0x40];
5469};
5470
5471struct mlx5_ifc_create_psv_out_bits {
5472 u8 status[0x8];
5473 u8 reserved_0[0x18];
5474
5475 u8 syndrome[0x20];
5476
5477 u8 reserved_1[0x40];
5478
5479 u8 reserved_2[0x8];
5480 u8 psv0_index[0x18];
5481
5482 u8 reserved_3[0x8];
5483 u8 psv1_index[0x18];
5484
5485 u8 reserved_4[0x8];
5486 u8 psv2_index[0x18];
5487
5488 u8 reserved_5[0x8];
5489 u8 psv3_index[0x18];
5490};
5491
5492struct mlx5_ifc_create_psv_in_bits {
5493 u8 opcode[0x10];
5494 u8 reserved_0[0x10];
5495
5496 u8 reserved_1[0x10];
5497 u8 op_mod[0x10];
5498
5499 u8 num_psv[0x4];
5500 u8 reserved_2[0x4];
5501 u8 pd[0x18];
5502
5503 u8 reserved_3[0x20];
5504};
5505
5506struct mlx5_ifc_create_mkey_out_bits {
5507 u8 status[0x8];
5508 u8 reserved_0[0x18];
5509
5510 u8 syndrome[0x20];
5511
5512 u8 reserved_1[0x8];
5513 u8 mkey_index[0x18];
5514
5515 u8 reserved_2[0x20];
5516};
5517
5518struct mlx5_ifc_create_mkey_in_bits {
5519 u8 opcode[0x10];
5520 u8 reserved_0[0x10];
5521
5522 u8 reserved_1[0x10];
5523 u8 op_mod[0x10];
5524
5525 u8 reserved_2[0x20];
5526
5527 u8 pg_access[0x1];
5528 u8 reserved_3[0x1f];
5529
5530 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5531
5532 u8 reserved_4[0x80];
5533
5534 u8 translations_octword_actual_size[0x20];
5535
5536 u8 reserved_5[0x560];
5537
5538 u8 klm_pas_mtt[0][0x20];
5539};
5540
5541struct mlx5_ifc_create_flow_table_out_bits {
5542 u8 status[0x8];
5543 u8 reserved_0[0x18];
5544
5545 u8 syndrome[0x20];
5546
5547 u8 reserved_1[0x8];
5548 u8 table_id[0x18];
5549
5550 u8 reserved_2[0x20];
5551};
5552
5553struct mlx5_ifc_create_flow_table_in_bits {
5554 u8 opcode[0x10];
5555 u8 reserved_0[0x10];
5556
5557 u8 reserved_1[0x10];
5558 u8 op_mod[0x10];
5559
5560 u8 reserved_2[0x40];
5561
5562 u8 table_type[0x8];
5563 u8 reserved_3[0x18];
5564
5565 u8 reserved_4[0x20];
5566
5567 u8 reserved_5[0x8];
5568 u8 level[0x8];
5569 u8 reserved_6[0x8];
5570 u8 log_size[0x8];
5571
5572 u8 reserved_7[0x120];
5573};
5574
5575struct mlx5_ifc_create_flow_group_out_bits {
5576 u8 status[0x8];
5577 u8 reserved_0[0x18];
5578
5579 u8 syndrome[0x20];
5580
5581 u8 reserved_1[0x8];
5582 u8 group_id[0x18];
5583
5584 u8 reserved_2[0x20];
5585};
5586
5587enum {
5588 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5589 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5590 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5591};
5592
5593struct mlx5_ifc_create_flow_group_in_bits {
5594 u8 opcode[0x10];
5595 u8 reserved_0[0x10];
5596
5597 u8 reserved_1[0x10];
5598 u8 op_mod[0x10];
5599
5600 u8 reserved_2[0x40];
5601
5602 u8 table_type[0x8];
5603 u8 reserved_3[0x18];
5604
5605 u8 reserved_4[0x8];
5606 u8 table_id[0x18];
5607
5608 u8 reserved_5[0x20];
5609
5610 u8 start_flow_index[0x20];
5611
5612 u8 reserved_6[0x20];
5613
5614 u8 end_flow_index[0x20];
5615
5616 u8 reserved_7[0xa0];
5617
5618 u8 reserved_8[0x18];
5619 u8 match_criteria_enable[0x8];
5620
5621 struct mlx5_ifc_fte_match_param_bits match_criteria;
5622
5623 u8 reserved_9[0xe00];
5624};
5625
5626struct mlx5_ifc_create_eq_out_bits {
5627 u8 status[0x8];
5628 u8 reserved_0[0x18];
5629
5630 u8 syndrome[0x20];
5631
5632 u8 reserved_1[0x18];
5633 u8 eq_number[0x8];
5634
5635 u8 reserved_2[0x20];
5636};
5637
5638struct mlx5_ifc_create_eq_in_bits {
5639 u8 opcode[0x10];
5640 u8 reserved_0[0x10];
5641
5642 u8 reserved_1[0x10];
5643 u8 op_mod[0x10];
5644
5645 u8 reserved_2[0x40];
5646
5647 struct mlx5_ifc_eqc_bits eq_context_entry;
5648
5649 u8 reserved_3[0x40];
5650
5651 u8 event_bitmask[0x40];
5652
5653 u8 reserved_4[0x580];
5654
5655 u8 pas[0][0x40];
5656};
5657
5658struct mlx5_ifc_create_dct_out_bits {
5659 u8 status[0x8];
5660 u8 reserved_0[0x18];
5661
5662 u8 syndrome[0x20];
5663
5664 u8 reserved_1[0x8];
5665 u8 dctn[0x18];
5666
5667 u8 reserved_2[0x20];
5668};
5669
5670struct mlx5_ifc_create_dct_in_bits {
5671 u8 opcode[0x10];
5672 u8 reserved_0[0x10];
5673
5674 u8 reserved_1[0x10];
5675 u8 op_mod[0x10];
5676
5677 u8 reserved_2[0x40];
5678
5679 struct mlx5_ifc_dctc_bits dct_context_entry;
5680
5681 u8 reserved_3[0x180];
5682};
5683
5684struct mlx5_ifc_create_cq_out_bits {
5685 u8 status[0x8];
5686 u8 reserved_0[0x18];
5687
5688 u8 syndrome[0x20];
5689
5690 u8 reserved_1[0x8];
5691 u8 cqn[0x18];
5692
5693 u8 reserved_2[0x20];
5694};
5695
5696struct mlx5_ifc_create_cq_in_bits {
5697 u8 opcode[0x10];
5698 u8 reserved_0[0x10];
5699
5700 u8 reserved_1[0x10];
5701 u8 op_mod[0x10];
5702
5703 u8 reserved_2[0x40];
5704
5705 struct mlx5_ifc_cqc_bits cq_context;
5706
5707 u8 reserved_3[0x600];
5708
5709 u8 pas[0][0x40];
5710};
5711
5712struct mlx5_ifc_config_int_moderation_out_bits {
5713 u8 status[0x8];
5714 u8 reserved_0[0x18];
5715
5716 u8 syndrome[0x20];
5717
5718 u8 reserved_1[0x4];
5719 u8 min_delay[0xc];
5720 u8 int_vector[0x10];
5721
5722 u8 reserved_2[0x20];
5723};
5724
5725enum {
5726 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
5727 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
5728};
5729
5730struct mlx5_ifc_config_int_moderation_in_bits {
5731 u8 opcode[0x10];
5732 u8 reserved_0[0x10];
5733
5734 u8 reserved_1[0x10];
5735 u8 op_mod[0x10];
5736
5737 u8 reserved_2[0x4];
5738 u8 min_delay[0xc];
5739 u8 int_vector[0x10];
5740
5741 u8 reserved_3[0x20];
5742};
5743
5744struct mlx5_ifc_attach_to_mcg_out_bits {
5745 u8 status[0x8];
5746 u8 reserved_0[0x18];
5747
5748 u8 syndrome[0x20];
5749
5750 u8 reserved_1[0x40];
5751};
5752
5753struct mlx5_ifc_attach_to_mcg_in_bits {
5754 u8 opcode[0x10];
5755 u8 reserved_0[0x10];
5756
5757 u8 reserved_1[0x10];
5758 u8 op_mod[0x10];
5759
5760 u8 reserved_2[0x8];
5761 u8 qpn[0x18];
5762
5763 u8 reserved_3[0x20];
5764
5765 u8 multicast_gid[16][0x8];
5766};
5767
5768struct mlx5_ifc_arm_xrc_srq_out_bits {
5769 u8 status[0x8];
5770 u8 reserved_0[0x18];
5771
5772 u8 syndrome[0x20];
5773
5774 u8 reserved_1[0x40];
5775};
5776
5777enum {
5778 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
5779};
5780
5781struct mlx5_ifc_arm_xrc_srq_in_bits {
5782 u8 opcode[0x10];
5783 u8 reserved_0[0x10];
5784
5785 u8 reserved_1[0x10];
5786 u8 op_mod[0x10];
5787
5788 u8 reserved_2[0x8];
5789 u8 xrc_srqn[0x18];
5790
5791 u8 reserved_3[0x10];
5792 u8 lwm[0x10];
5793};
5794
5795struct mlx5_ifc_arm_rq_out_bits {
5796 u8 status[0x8];
5797 u8 reserved_0[0x18];
5798
5799 u8 syndrome[0x20];
5800
5801 u8 reserved_1[0x40];
5802};
5803
5804enum {
5805 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
5806};
5807
5808struct mlx5_ifc_arm_rq_in_bits {
5809 u8 opcode[0x10];
5810 u8 reserved_0[0x10];
5811
5812 u8 reserved_1[0x10];
5813 u8 op_mod[0x10];
5814
5815 u8 reserved_2[0x8];
5816 u8 srq_number[0x18];
5817
5818 u8 reserved_3[0x10];
5819 u8 lwm[0x10];
5820};
5821
5822struct mlx5_ifc_arm_dct_out_bits {
5823 u8 status[0x8];
5824 u8 reserved_0[0x18];
5825
5826 u8 syndrome[0x20];
5827
5828 u8 reserved_1[0x40];
5829};
5830
5831struct mlx5_ifc_arm_dct_in_bits {
5832 u8 opcode[0x10];
5833 u8 reserved_0[0x10];
5834
5835 u8 reserved_1[0x10];
5836 u8 op_mod[0x10];
5837
5838 u8 reserved_2[0x8];
5839 u8 dct_number[0x18];
5840
5841 u8 reserved_3[0x20];
5842};
5843
5844struct mlx5_ifc_alloc_xrcd_out_bits {
5845 u8 status[0x8];
5846 u8 reserved_0[0x18];
5847
5848 u8 syndrome[0x20];
5849
5850 u8 reserved_1[0x8];
5851 u8 xrcd[0x18];
5852
5853 u8 reserved_2[0x20];
5854};
5855
5856struct mlx5_ifc_alloc_xrcd_in_bits {
5857 u8 opcode[0x10];
5858 u8 reserved_0[0x10];
5859
5860 u8 reserved_1[0x10];
5861 u8 op_mod[0x10];
5862
5863 u8 reserved_2[0x40];
5864};
5865
5866struct mlx5_ifc_alloc_uar_out_bits {
5867 u8 status[0x8];
5868 u8 reserved_0[0x18];
5869
5870 u8 syndrome[0x20];
5871
5872 u8 reserved_1[0x8];
5873 u8 uar[0x18];
5874
5875 u8 reserved_2[0x20];
5876};
5877
5878struct mlx5_ifc_alloc_uar_in_bits {
5879 u8 opcode[0x10];
5880 u8 reserved_0[0x10];
5881
5882 u8 reserved_1[0x10];
5883 u8 op_mod[0x10];
5884
5885 u8 reserved_2[0x40];
5886};
5887
5888struct mlx5_ifc_alloc_transport_domain_out_bits {
5889 u8 status[0x8];
5890 u8 reserved_0[0x18];
5891
5892 u8 syndrome[0x20];
5893
5894 u8 reserved_1[0x8];
5895 u8 transport_domain[0x18];
5896
5897 u8 reserved_2[0x20];
5898};
5899
5900struct mlx5_ifc_alloc_transport_domain_in_bits {
5901 u8 opcode[0x10];
5902 u8 reserved_0[0x10];
5903
5904 u8 reserved_1[0x10];
5905 u8 op_mod[0x10];
5906
5907 u8 reserved_2[0x40];
5908};
5909
5910struct mlx5_ifc_alloc_q_counter_out_bits {
5911 u8 status[0x8];
5912 u8 reserved_0[0x18];
5913
5914 u8 syndrome[0x20];
5915
5916 u8 reserved_1[0x18];
5917 u8 counter_set_id[0x8];
5918
5919 u8 reserved_2[0x20];
5920};
5921
5922struct mlx5_ifc_alloc_q_counter_in_bits {
5923 u8 opcode[0x10];
5924 u8 reserved_0[0x10];
5925
5926 u8 reserved_1[0x10];
5927 u8 op_mod[0x10];
5928
5929 u8 reserved_2[0x40];
5930};
5931
5932struct mlx5_ifc_alloc_pd_out_bits {
5933 u8 status[0x8];
5934 u8 reserved_0[0x18];
5935
5936 u8 syndrome[0x20];
5937
5938 u8 reserved_1[0x8];
5939 u8 pd[0x18];
5940
5941 u8 reserved_2[0x20];
5942};
5943
5944struct mlx5_ifc_alloc_pd_in_bits {
5945 u8 opcode[0x10];
5946 u8 reserved_0[0x10];
5947
5948 u8 reserved_1[0x10];
5949 u8 op_mod[0x10];
5950
5951 u8 reserved_2[0x40];
5952};
5953
5954struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
5955 u8 status[0x8];
5956 u8 reserved_0[0x18];
5957
5958 u8 syndrome[0x20];
5959
5960 u8 reserved_1[0x40];
5961};
5962
5963struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
5964 u8 opcode[0x10];
5965 u8 reserved_0[0x10];
5966
5967 u8 reserved_1[0x10];
5968 u8 op_mod[0x10];
5969
5970 u8 reserved_2[0x20];
5971
5972 u8 reserved_3[0x10];
5973 u8 vxlan_udp_port[0x10];
5974};
5975
5976struct mlx5_ifc_access_register_out_bits {
5977 u8 status[0x8];
5978 u8 reserved_0[0x18];
5979
5980 u8 syndrome[0x20];
5981
5982 u8 reserved_1[0x40];
5983
5984 u8 register_data[0][0x20];
5985};
5986
5987enum {
5988 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
5989 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
5990};
5991
5992struct mlx5_ifc_access_register_in_bits {
5993 u8 opcode[0x10];
5994 u8 reserved_0[0x10];
5995
5996 u8 reserved_1[0x10];
5997 u8 op_mod[0x10];
5998
5999 u8 reserved_2[0x10];
6000 u8 register_id[0x10];
6001
6002 u8 argument[0x20];
6003
6004 u8 register_data[0][0x20];
6005};
6006
6007struct mlx5_ifc_sltp_reg_bits {
6008 u8 status[0x4];
6009 u8 version[0x4];
6010 u8 local_port[0x8];
6011 u8 pnat[0x2];
6012 u8 reserved_0[0x2];
6013 u8 lane[0x4];
6014 u8 reserved_1[0x8];
6015
6016 u8 reserved_2[0x20];
6017
6018 u8 reserved_3[0x7];
6019 u8 polarity[0x1];
6020 u8 ob_tap0[0x8];
6021 u8 ob_tap1[0x8];
6022 u8 ob_tap2[0x8];
6023
6024 u8 reserved_4[0xc];
6025 u8 ob_preemp_mode[0x4];
6026 u8 ob_reg[0x8];
6027 u8 ob_bias[0x8];
6028
6029 u8 reserved_5[0x20];
6030};
6031
6032struct mlx5_ifc_slrg_reg_bits {
6033 u8 status[0x4];
6034 u8 version[0x4];
6035 u8 local_port[0x8];
6036 u8 pnat[0x2];
6037 u8 reserved_0[0x2];
6038 u8 lane[0x4];
6039 u8 reserved_1[0x8];
6040
6041 u8 time_to_link_up[0x10];
6042 u8 reserved_2[0xc];
6043 u8 grade_lane_speed[0x4];
6044
6045 u8 grade_version[0x8];
6046 u8 grade[0x18];
6047
6048 u8 reserved_3[0x4];
6049 u8 height_grade_type[0x4];
6050 u8 height_grade[0x18];
6051
6052 u8 height_dz[0x10];
6053 u8 height_dv[0x10];
6054
6055 u8 reserved_4[0x10];
6056 u8 height_sigma[0x10];
6057
6058 u8 reserved_5[0x20];
6059
6060 u8 reserved_6[0x4];
6061 u8 phase_grade_type[0x4];
6062 u8 phase_grade[0x18];
6063
6064 u8 reserved_7[0x8];
6065 u8 phase_eo_pos[0x8];
6066 u8 reserved_8[0x8];
6067 u8 phase_eo_neg[0x8];
6068
6069 u8 ffe_set_tested[0x10];
6070 u8 test_errors_per_lane[0x10];
6071};
6072
6073struct mlx5_ifc_pvlc_reg_bits {
6074 u8 reserved_0[0x8];
6075 u8 local_port[0x8];
6076 u8 reserved_1[0x10];
6077
6078 u8 reserved_2[0x1c];
6079 u8 vl_hw_cap[0x4];
6080
6081 u8 reserved_3[0x1c];
6082 u8 vl_admin[0x4];
6083
6084 u8 reserved_4[0x1c];
6085 u8 vl_operational[0x4];
6086};
6087
6088struct mlx5_ifc_pude_reg_bits {
6089 u8 swid[0x8];
6090 u8 local_port[0x8];
6091 u8 reserved_0[0x4];
6092 u8 admin_status[0x4];
6093 u8 reserved_1[0x4];
6094 u8 oper_status[0x4];
6095
6096 u8 reserved_2[0x60];
6097};
6098
6099struct mlx5_ifc_ptys_reg_bits {
6100 u8 reserved_0[0x8];
6101 u8 local_port[0x8];
6102 u8 reserved_1[0xd];
6103 u8 proto_mask[0x3];
6104
6105 u8 reserved_2[0x40];
6106
6107 u8 eth_proto_capability[0x20];
6108
6109 u8 ib_link_width_capability[0x10];
6110 u8 ib_proto_capability[0x10];
6111
6112 u8 reserved_3[0x20];
6113
6114 u8 eth_proto_admin[0x20];
6115
6116 u8 ib_link_width_admin[0x10];
6117 u8 ib_proto_admin[0x10];
6118
6119 u8 reserved_4[0x20];
6120
6121 u8 eth_proto_oper[0x20];
6122
6123 u8 ib_link_width_oper[0x10];
6124 u8 ib_proto_oper[0x10];
6125
6126 u8 reserved_5[0x20];
6127
6128 u8 eth_proto_lp_advertise[0x20];
6129
6130 u8 reserved_6[0x60];
6131};
6132
6133struct mlx5_ifc_ptas_reg_bits {
6134 u8 reserved_0[0x20];
6135
6136 u8 algorithm_options[0x10];
6137 u8 reserved_1[0x4];
6138 u8 repetitions_mode[0x4];
6139 u8 num_of_repetitions[0x8];
6140
6141 u8 grade_version[0x8];
6142 u8 height_grade_type[0x4];
6143 u8 phase_grade_type[0x4];
6144 u8 height_grade_weight[0x8];
6145 u8 phase_grade_weight[0x8];
6146
6147 u8 gisim_measure_bits[0x10];
6148 u8 adaptive_tap_measure_bits[0x10];
6149
6150 u8 ber_bath_high_error_threshold[0x10];
6151 u8 ber_bath_mid_error_threshold[0x10];
6152
6153 u8 ber_bath_low_error_threshold[0x10];
6154 u8 one_ratio_high_threshold[0x10];
6155
6156 u8 one_ratio_high_mid_threshold[0x10];
6157 u8 one_ratio_low_mid_threshold[0x10];
6158
6159 u8 one_ratio_low_threshold[0x10];
6160 u8 ndeo_error_threshold[0x10];
6161
6162 u8 mixer_offset_step_size[0x10];
6163 u8 reserved_2[0x8];
6164 u8 mix90_phase_for_voltage_bath[0x8];
6165
6166 u8 mixer_offset_start[0x10];
6167 u8 mixer_offset_end[0x10];
6168
6169 u8 reserved_3[0x15];
6170 u8 ber_test_time[0xb];
6171};
6172
6173struct mlx5_ifc_pspa_reg_bits {
6174 u8 swid[0x8];
6175 u8 local_port[0x8];
6176 u8 sub_port[0x8];
6177 u8 reserved_0[0x8];
6178
6179 u8 reserved_1[0x20];
6180};
6181
6182struct mlx5_ifc_pqdr_reg_bits {
6183 u8 reserved_0[0x8];
6184 u8 local_port[0x8];
6185 u8 reserved_1[0x5];
6186 u8 prio[0x3];
6187 u8 reserved_2[0x6];
6188 u8 mode[0x2];
6189
6190 u8 reserved_3[0x20];
6191
6192 u8 reserved_4[0x10];
6193 u8 min_threshold[0x10];
6194
6195 u8 reserved_5[0x10];
6196 u8 max_threshold[0x10];
6197
6198 u8 reserved_6[0x10];
6199 u8 mark_probability_denominator[0x10];
6200
6201 u8 reserved_7[0x60];
6202};
6203
6204struct mlx5_ifc_ppsc_reg_bits {
6205 u8 reserved_0[0x8];
6206 u8 local_port[0x8];
6207 u8 reserved_1[0x10];
6208
6209 u8 reserved_2[0x60];
6210
6211 u8 reserved_3[0x1c];
6212 u8 wrps_admin[0x4];
6213
6214 u8 reserved_4[0x1c];
6215 u8 wrps_status[0x4];
6216
6217 u8 reserved_5[0x8];
6218 u8 up_threshold[0x8];
6219 u8 reserved_6[0x8];
6220 u8 down_threshold[0x8];
6221
6222 u8 reserved_7[0x20];
6223
6224 u8 reserved_8[0x1c];
6225 u8 srps_admin[0x4];
6226
6227 u8 reserved_9[0x1c];
6228 u8 srps_status[0x4];
6229
6230 u8 reserved_10[0x40];
6231};
6232
6233struct mlx5_ifc_pplr_reg_bits {
6234 u8 reserved_0[0x8];
6235 u8 local_port[0x8];
6236 u8 reserved_1[0x10];
6237
6238 u8 reserved_2[0x8];
6239 u8 lb_cap[0x8];
6240 u8 reserved_3[0x8];
6241 u8 lb_en[0x8];
6242};
6243
6244struct mlx5_ifc_pplm_reg_bits {
6245 u8 reserved_0[0x8];
6246 u8 local_port[0x8];
6247 u8 reserved_1[0x10];
6248
6249 u8 reserved_2[0x20];
6250
6251 u8 port_profile_mode[0x8];
6252 u8 static_port_profile[0x8];
6253 u8 active_port_profile[0x8];
6254 u8 reserved_3[0x8];
6255
6256 u8 retransmission_active[0x8];
6257 u8 fec_mode_active[0x18];
6258
6259 u8 reserved_4[0x20];
6260};
6261
6262struct mlx5_ifc_ppcnt_reg_bits {
6263 u8 swid[0x8];
6264 u8 local_port[0x8];
6265 u8 pnat[0x2];
6266 u8 reserved_0[0x8];
6267 u8 grp[0x6];
6268
6269 u8 clr[0x1];
6270 u8 reserved_1[0x1c];
6271 u8 prio_tc[0x3];
6272
6273 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6274};
6275
6276struct mlx5_ifc_ppad_reg_bits {
6277 u8 reserved_0[0x3];
6278 u8 single_mac[0x1];
6279 u8 reserved_1[0x4];
6280 u8 local_port[0x8];
6281 u8 mac_47_32[0x10];
6282
6283 u8 mac_31_0[0x20];
6284
6285 u8 reserved_2[0x40];
6286};
6287
6288struct mlx5_ifc_pmtu_reg_bits {
6289 u8 reserved_0[0x8];
6290 u8 local_port[0x8];
6291 u8 reserved_1[0x10];
6292
6293 u8 max_mtu[0x10];
6294 u8 reserved_2[0x10];
6295
6296 u8 admin_mtu[0x10];
6297 u8 reserved_3[0x10];
6298
6299 u8 oper_mtu[0x10];
6300 u8 reserved_4[0x10];
6301};
6302
6303struct mlx5_ifc_pmpr_reg_bits {
6304 u8 reserved_0[0x8];
6305 u8 module[0x8];
6306 u8 reserved_1[0x10];
6307
6308 u8 reserved_2[0x18];
6309 u8 attenuation_5g[0x8];
6310
6311 u8 reserved_3[0x18];
6312 u8 attenuation_7g[0x8];
6313
6314 u8 reserved_4[0x18];
6315 u8 attenuation_12g[0x8];
6316};
6317
6318struct mlx5_ifc_pmpe_reg_bits {
6319 u8 reserved_0[0x8];
6320 u8 module[0x8];
6321 u8 reserved_1[0xc];
6322 u8 module_status[0x4];
6323
6324 u8 reserved_2[0x60];
6325};
6326
6327struct mlx5_ifc_pmpc_reg_bits {
6328 u8 module_state_updated[32][0x8];
6329};
6330
6331struct mlx5_ifc_pmlpn_reg_bits {
6332 u8 reserved_0[0x4];
6333 u8 mlpn_status[0x4];
6334 u8 local_port[0x8];
6335 u8 reserved_1[0x10];
6336
6337 u8 e[0x1];
6338 u8 reserved_2[0x1f];
6339};
6340
6341struct mlx5_ifc_pmlp_reg_bits {
6342 u8 rxtx[0x1];
6343 u8 reserved_0[0x7];
6344 u8 local_port[0x8];
6345 u8 reserved_1[0x8];
6346 u8 width[0x8];
6347
6348 u8 lane0_module_mapping[0x20];
6349
6350 u8 lane1_module_mapping[0x20];
6351
6352 u8 lane2_module_mapping[0x20];
6353
6354 u8 lane3_module_mapping[0x20];
6355
6356 u8 reserved_2[0x160];
6357};
6358
6359struct mlx5_ifc_pmaos_reg_bits {
6360 u8 reserved_0[0x8];
6361 u8 module[0x8];
6362 u8 reserved_1[0x4];
6363 u8 admin_status[0x4];
6364 u8 reserved_2[0x4];
6365 u8 oper_status[0x4];
6366
6367 u8 ase[0x1];
6368 u8 ee[0x1];
6369 u8 reserved_3[0x1c];
6370 u8 e[0x2];
6371
6372 u8 reserved_4[0x40];
6373};
6374
6375struct mlx5_ifc_plpc_reg_bits {
6376 u8 reserved_0[0x4];
6377 u8 profile_id[0xc];
6378 u8 reserved_1[0x4];
6379 u8 proto_mask[0x4];
6380 u8 reserved_2[0x8];
6381
6382 u8 reserved_3[0x10];
6383 u8 lane_speed[0x10];
6384
6385 u8 reserved_4[0x17];
6386 u8 lpbf[0x1];
6387 u8 fec_mode_policy[0x8];
6388
6389 u8 retransmission_capability[0x8];
6390 u8 fec_mode_capability[0x18];
6391
6392 u8 retransmission_support_admin[0x8];
6393 u8 fec_mode_support_admin[0x18];
6394
6395 u8 retransmission_request_admin[0x8];
6396 u8 fec_mode_request_admin[0x18];
6397
6398 u8 reserved_5[0x80];
6399};
6400
6401struct mlx5_ifc_plib_reg_bits {
6402 u8 reserved_0[0x8];
6403 u8 local_port[0x8];
6404 u8 reserved_1[0x8];
6405 u8 ib_port[0x8];
6406
6407 u8 reserved_2[0x60];
6408};
6409
6410struct mlx5_ifc_plbf_reg_bits {
6411 u8 reserved_0[0x8];
6412 u8 local_port[0x8];
6413 u8 reserved_1[0xd];
6414 u8 lbf_mode[0x3];
6415
6416 u8 reserved_2[0x20];
6417};
6418
6419struct mlx5_ifc_pipg_reg_bits {
6420 u8 reserved_0[0x8];
6421 u8 local_port[0x8];
6422 u8 reserved_1[0x10];
6423
6424 u8 dic[0x1];
6425 u8 reserved_2[0x19];
6426 u8 ipg[0x4];
6427 u8 reserved_3[0x2];
6428};
6429
6430struct mlx5_ifc_pifr_reg_bits {
6431 u8 reserved_0[0x8];
6432 u8 local_port[0x8];
6433 u8 reserved_1[0x10];
6434
6435 u8 reserved_2[0xe0];
6436
6437 u8 port_filter[8][0x20];
6438
6439 u8 port_filter_update_en[8][0x20];
6440};
6441
6442struct mlx5_ifc_pfcc_reg_bits {
6443 u8 reserved_0[0x8];
6444 u8 local_port[0x8];
6445 u8 reserved_1[0x10];
6446
6447 u8 ppan[0x4];
6448 u8 reserved_2[0x4];
6449 u8 prio_mask_tx[0x8];
6450 u8 reserved_3[0x8];
6451 u8 prio_mask_rx[0x8];
6452
6453 u8 pptx[0x1];
6454 u8 aptx[0x1];
6455 u8 reserved_4[0x6];
6456 u8 pfctx[0x8];
6457 u8 reserved_5[0x10];
6458
6459 u8 pprx[0x1];
6460 u8 aprx[0x1];
6461 u8 reserved_6[0x6];
6462 u8 pfcrx[0x8];
6463 u8 reserved_7[0x10];
6464
6465 u8 reserved_8[0x80];
6466};
6467
6468struct mlx5_ifc_pelc_reg_bits {
6469 u8 op[0x4];
6470 u8 reserved_0[0x4];
6471 u8 local_port[0x8];
6472 u8 reserved_1[0x10];
6473
6474 u8 op_admin[0x8];
6475 u8 op_capability[0x8];
6476 u8 op_request[0x8];
6477 u8 op_active[0x8];
6478
6479 u8 admin[0x40];
6480
6481 u8 capability[0x40];
6482
6483 u8 request[0x40];
6484
6485 u8 active[0x40];
6486
6487 u8 reserved_2[0x80];
6488};
6489
6490struct mlx5_ifc_peir_reg_bits {
6491 u8 reserved_0[0x8];
6492 u8 local_port[0x8];
6493 u8 reserved_1[0x10];
6494
6495 u8 reserved_2[0xc];
6496 u8 error_count[0x4];
6497 u8 reserved_3[0x10];
6498
6499 u8 reserved_4[0xc];
6500 u8 lane[0x4];
6501 u8 reserved_5[0x8];
6502 u8 error_type[0x8];
6503};
6504
6505struct mlx5_ifc_pcap_reg_bits {
6506 u8 reserved_0[0x8];
6507 u8 local_port[0x8];
6508 u8 reserved_1[0x10];
6509
6510 u8 port_capability_mask[4][0x20];
6511};
6512
6513struct mlx5_ifc_paos_reg_bits {
6514 u8 swid[0x8];
6515 u8 local_port[0x8];
6516 u8 reserved_0[0x4];
6517 u8 admin_status[0x4];
6518 u8 reserved_1[0x4];
6519 u8 oper_status[0x4];
6520
6521 u8 ase[0x1];
6522 u8 ee[0x1];
6523 u8 reserved_2[0x1c];
6524 u8 e[0x2];
6525
6526 u8 reserved_3[0x40];
6527};
6528
6529struct mlx5_ifc_pamp_reg_bits {
6530 u8 reserved_0[0x8];
6531 u8 opamp_group[0x8];
6532 u8 reserved_1[0xc];
6533 u8 opamp_group_type[0x4];
6534
6535 u8 start_index[0x10];
6536 u8 reserved_2[0x4];
6537 u8 num_of_indices[0xc];
6538
6539 u8 index_data[18][0x10];
6540};
6541
6542struct mlx5_ifc_lane_2_module_mapping_bits {
6543 u8 reserved_0[0x6];
6544 u8 rx_lane[0x2];
6545 u8 reserved_1[0x6];
6546 u8 tx_lane[0x2];
6547 u8 reserved_2[0x8];
6548 u8 module[0x8];
6549};
6550
6551struct mlx5_ifc_bufferx_reg_bits {
6552 u8 reserved_0[0x6];
6553 u8 lossy[0x1];
6554 u8 epsb[0x1];
6555 u8 reserved_1[0xc];
6556 u8 size[0xc];
6557
6558 u8 xoff_threshold[0x10];
6559 u8 xon_threshold[0x10];
6560};
6561
6562struct mlx5_ifc_set_node_in_bits {
6563 u8 node_description[64][0x8];
6564};
6565
6566struct mlx5_ifc_register_power_settings_bits {
6567 u8 reserved_0[0x18];
6568 u8 power_settings_level[0x8];
6569
6570 u8 reserved_1[0x60];
6571};
6572
6573struct mlx5_ifc_register_host_endianness_bits {
6574 u8 he[0x1];
6575 u8 reserved_0[0x1f];
6576
6577 u8 reserved_1[0x60];
6578};
6579
6580struct mlx5_ifc_umr_pointer_desc_argument_bits {
6581 u8 reserved_0[0x20];
6582
6583 u8 mkey[0x20];
6584
6585 u8 addressh_63_32[0x20];
6586
6587 u8 addressl_31_0[0x20];
6588};
6589
6590struct mlx5_ifc_ud_adrs_vector_bits {
6591 u8 dc_key[0x40];
6592
6593 u8 ext[0x1];
6594 u8 reserved_0[0x7];
6595 u8 destination_qp_dct[0x18];
6596
6597 u8 static_rate[0x4];
6598 u8 sl_eth_prio[0x4];
6599 u8 fl[0x1];
6600 u8 mlid[0x7];
6601 u8 rlid_udp_sport[0x10];
6602
6603 u8 reserved_1[0x20];
6604
6605 u8 rmac_47_16[0x20];
6606
6607 u8 rmac_15_0[0x10];
6608 u8 tclass[0x8];
6609 u8 hop_limit[0x8];
6610
6611 u8 reserved_2[0x1];
6612 u8 grh[0x1];
6613 u8 reserved_3[0x2];
6614 u8 src_addr_index[0x8];
6615 u8 flow_label[0x14];
6616
6617 u8 rgid_rip[16][0x8];
6618};
6619
6620struct mlx5_ifc_pages_req_event_bits {
6621 u8 reserved_0[0x10];
6622 u8 function_id[0x10];
6623
6624 u8 num_pages[0x20];
6625
6626 u8 reserved_1[0xa0];
6627};
6628
6629struct mlx5_ifc_eqe_bits {
6630 u8 reserved_0[0x8];
6631 u8 event_type[0x8];
6632 u8 reserved_1[0x8];
6633 u8 event_sub_type[0x8];
6634
6635 u8 reserved_2[0xe0];
6636
6637 union mlx5_ifc_event_auto_bits event_data;
6638
6639 u8 reserved_3[0x10];
6640 u8 signature[0x8];
6641 u8 reserved_4[0x7];
6642 u8 owner[0x1];
6643};
6644
6645enum {
6646 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
6647};
6648
6649struct mlx5_ifc_cmd_queue_entry_bits {
6650 u8 type[0x8];
6651 u8 reserved_0[0x18];
6652
6653 u8 input_length[0x20];
6654
6655 u8 input_mailbox_pointer_63_32[0x20];
6656
6657 u8 input_mailbox_pointer_31_9[0x17];
6658 u8 reserved_1[0x9];
6659
6660 u8 command_input_inline_data[16][0x8];
6661
6662 u8 command_output_inline_data[16][0x8];
6663
6664 u8 output_mailbox_pointer_63_32[0x20];
6665
6666 u8 output_mailbox_pointer_31_9[0x17];
6667 u8 reserved_2[0x9];
6668
6669 u8 output_length[0x20];
6670
6671 u8 token[0x8];
6672 u8 signature[0x8];
6673 u8 reserved_3[0x8];
6674 u8 status[0x7];
6675 u8 ownership[0x1];
6676};
6677
6678struct mlx5_ifc_cmd_out_bits {
6679 u8 status[0x8];
6680 u8 reserved_0[0x18];
6681
6682 u8 syndrome[0x20];
6683
6684 u8 command_output[0x20];
6685};
6686
6687struct mlx5_ifc_cmd_in_bits {
6688 u8 opcode[0x10];
6689 u8 reserved_0[0x10];
6690
6691 u8 reserved_1[0x10];
6692 u8 op_mod[0x10];
6693
6694 u8 command[0][0x20];
6695};
6696
6697struct mlx5_ifc_cmd_if_box_bits {
6698 u8 mailbox_data[512][0x8];
6699
6700 u8 reserved_0[0x180];
6701
6702 u8 next_pointer_63_32[0x20];
6703
6704 u8 next_pointer_31_10[0x16];
6705 u8 reserved_1[0xa];
6706
6707 u8 block_number[0x20];
6708
6709 u8 reserved_2[0x8];
6710 u8 token[0x8];
6711 u8 ctrl_signature[0x8];
6712 u8 signature[0x8];
6713};
6714
6715struct mlx5_ifc_mtt_bits {
6716 u8 ptag_63_32[0x20];
6717
6718 u8 ptag_31_8[0x18];
6719 u8 reserved_0[0x6];
6720 u8 wr_en[0x1];
6721 u8 rd_en[0x1];
6722};
6723
6724enum {
6725 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
6726 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
6727 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
6728};
6729
6730enum {
6731 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
6732 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
6733 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
6734};
6735
6736enum {
6737 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
6738 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
6739 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
6740 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
6741 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
6742 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
6743 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
6744 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
6745 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
6746 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
6747 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
6748};
6749
6750struct mlx5_ifc_initial_seg_bits {
6751 u8 fw_rev_minor[0x10];
6752 u8 fw_rev_major[0x10];
6753
6754 u8 cmd_interface_rev[0x10];
6755 u8 fw_rev_subminor[0x10];
6756
6757 u8 reserved_0[0x40];
6758
6759 u8 cmdq_phy_addr_63_32[0x20];
6760
6761 u8 cmdq_phy_addr_31_12[0x14];
6762 u8 reserved_1[0x2];
6763 u8 nic_interface[0x2];
6764 u8 log_cmdq_size[0x4];
6765 u8 log_cmdq_stride[0x4];
6766
6767 u8 command_doorbell_vector[0x20];
6768
6769 u8 reserved_2[0xf00];
6770
6771 u8 initializing[0x1];
6772 u8 reserved_3[0x4];
6773 u8 nic_interface_supported[0x3];
6774 u8 reserved_4[0x18];
6775
6776 struct mlx5_ifc_health_buffer_bits health_buffer;
6777
6778 u8 no_dram_nic_offset[0x20];
6779
6780 u8 reserved_5[0x6e40];
6781
6782 u8 reserved_6[0x1f];
6783 u8 clear_int[0x1];
6784
6785 u8 health_syndrome[0x8];
6786 u8 health_counter[0x18];
6787
6788 u8 reserved_7[0x17fc0];
6789};
6790
6791union mlx5_ifc_ports_control_registers_document_bits {
6792 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6793 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6794 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6795 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6796 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6797 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6798 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6799 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6800 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6801 struct mlx5_ifc_pamp_reg_bits pamp_reg;
6802 struct mlx5_ifc_paos_reg_bits paos_reg;
6803 struct mlx5_ifc_pcap_reg_bits pcap_reg;
6804 struct mlx5_ifc_peir_reg_bits peir_reg;
6805 struct mlx5_ifc_pelc_reg_bits pelc_reg;
6806 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6807 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6808 struct mlx5_ifc_pifr_reg_bits pifr_reg;
6809 struct mlx5_ifc_pipg_reg_bits pipg_reg;
6810 struct mlx5_ifc_plbf_reg_bits plbf_reg;
6811 struct mlx5_ifc_plib_reg_bits plib_reg;
6812 struct mlx5_ifc_plpc_reg_bits plpc_reg;
6813 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6814 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
6815 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
6816 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
6817 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
6818 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
6819 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
6820 struct mlx5_ifc_ppad_reg_bits ppad_reg;
6821 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
6822 struct mlx5_ifc_pplm_reg_bits pplm_reg;
6823 struct mlx5_ifc_pplr_reg_bits pplr_reg;
6824 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
6825 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
6826 struct mlx5_ifc_pspa_reg_bits pspa_reg;
6827 struct mlx5_ifc_ptas_reg_bits ptas_reg;
6828 struct mlx5_ifc_ptys_reg_bits ptys_reg;
6829 struct mlx5_ifc_pude_reg_bits pude_reg;
6830 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
6831 struct mlx5_ifc_slrg_reg_bits slrg_reg;
6832 struct mlx5_ifc_sltp_reg_bits sltp_reg;
6833 u8 reserved_0[0x60e0];
6834};
6835
6836union mlx5_ifc_debug_enhancements_document_bits {
6837 struct mlx5_ifc_health_buffer_bits health_buffer;
6838 u8 reserved_0[0x200];
6839};
6840
6841union mlx5_ifc_uplink_pci_interface_document_bits {
6842 struct mlx5_ifc_initial_seg_bits initial_seg;
6843 u8 reserved_0[0x20060];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]6844};
6845
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]6846#endif /* MLX5_IFC_H */