| Suzuki K Poulose | 7520fa9 | 2018-01-02 11:25:33 +0000 | [diff] [blame] | 1 | ARM DynamIQ Shared Unit (DSU) PMU |
| 2 | ================================== |
| 3 | |
| 4 | ARM DynamIQ Shared Unit integrates one or more cores with an L3 memory system, |
| 5 | control logic and external interfaces to form a multicore cluster. The PMU |
| 6 | allows counting the various events related to the L3 cache, Snoop Control Unit |
| 7 | etc, using 32bit independent counters. It also provides a 64bit cycle counter. |
| 8 | |
| 9 | The PMU can only be accessed via CPU system registers and are common to the |
| 10 | cores connected to the same DSU. Like most of the other uncore PMUs, DSU |
| 11 | PMU doesn't support process specific events and cannot be used in sampling mode. |
| 12 | |
| 13 | The DSU provides a bitmap for a subset of implemented events via hardware |
| 14 | registers. There is no way for the driver to determine if the other events |
| 15 | are available or not. Hence the driver exposes only those events advertised |
| 16 | by the DSU, in "events" directory under : |
| 17 | |
| 18 | /sys/bus/event_sources/devices/arm_dsu_<N>/ |
| 19 | |
| 20 | The user should refer to the TRM of the product to figure out the supported events |
| 21 | and use the raw event code for the unlisted events. |
| 22 | |
| 23 | The driver also exposes the CPUs connected to the DSU instance in "associated_cpus". |
| 24 | |
| 25 | |
| 26 | e.g usage : |
| 27 | |
| 28 | perf stat -a -e arm_dsu_0/cycles/ |