Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Machine check handler. |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 3 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 5 | * Rest from unknown author(s). |
| 6 | * 2004 Andi Kleen. Rewrote most of it. |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 7 | * Copyright 2008 Intel Corporation |
| 8 | * Author: Andi Kleen |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | */ |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 10 | #include <linux/thread_info.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 11 | #include <linux/capability.h> |
| 12 | #include <linux/miscdevice.h> |
Andi Kleen | ccc3c31 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 13 | #include <linux/interrupt.h> |
Andi Kleen | 8457c84 | 2009-02-12 13:49:33 +0100 | [diff] [blame] | 14 | #include <linux/ratelimit.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 15 | #include <linux/kallsyms.h> |
| 16 | #include <linux/rcupdate.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 17 | #include <linux/kobject.h> |
Hidetoshi Seto | 14a0253 | 2009-04-30 16:04:51 +0900 | [diff] [blame] | 18 | #include <linux/uaccess.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 19 | #include <linux/kdebug.h> |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/percpu.h> |
| 22 | #include <linux/string.h> |
| 23 | #include <linux/sysdev.h> |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 24 | #include <linux/delay.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 25 | #include <linux/ctype.h> |
| 26 | #include <linux/sched.h> |
| 27 | #include <linux/sysfs.h> |
| 28 | #include <linux/types.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 30 | #include <linux/init.h> |
| 31 | #include <linux/kmod.h> |
| 32 | #include <linux/poll.h> |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 33 | #include <linux/nmi.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 34 | #include <linux/cpu.h> |
Hidetoshi Seto | 14a0253 | 2009-04-30 16:04:51 +0900 | [diff] [blame] | 35 | #include <linux/smp.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 36 | #include <linux/fs.h> |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 37 | #include <linux/mm.h> |
Huang Ying | 5be9ed2 | 2009-07-31 09:41:42 +0800 | [diff] [blame] | 38 | #include <linux/debugfs.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 40 | #include <asm/processor.h> |
Andi Kleen | ccc3c31 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 41 | #include <asm/hw_irq.h> |
| 42 | #include <asm/apic.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 43 | #include <asm/idle.h> |
Andi Kleen | ccc3c31 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 44 | #include <asm/ipi.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 45 | #include <asm/mce.h> |
| 46 | #include <asm/msr.h> |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 47 | |
Andi Kleen | bd19a5e | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 48 | #include "mce-internal.h" |
Ingo Molnar | 711c2e4 | 2009-04-08 12:31:26 +0200 | [diff] [blame] | 49 | |
Ingo Molnar | 2aa2b50dd | 2010-03-14 08:57:03 +0100 | [diff] [blame] | 50 | static DEFINE_MUTEX(mce_read_mutex); |
| 51 | |
Paul E. McKenney | f56e8a0 | 2010-03-05 15:03:27 -0800 | [diff] [blame] | 52 | #define rcu_dereference_check_mce(p) \ |
| 53 | rcu_dereference_check((p), \ |
| 54 | rcu_read_lock_sched_held() || \ |
| 55 | lockdep_is_held(&mce_read_mutex)) |
| 56 | |
Hidetoshi Seto | 8968f9d | 2009-10-13 16:19:41 +0900 | [diff] [blame] | 57 | #define CREATE_TRACE_POINTS |
| 58 | #include <trace/events/mce.h> |
| 59 | |
Hidetoshi Seto | 4e5b3e6 | 2009-06-15 17:20:20 +0900 | [diff] [blame] | 60 | int mce_disabled __read_mostly; |
Andi Kleen | 04b2b1a | 2009-04-28 22:50:19 +0200 | [diff] [blame] | 61 | |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 62 | #define MISC_MCELOG_MINOR 227 |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 63 | |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 64 | #define SPINUNIT 100 /* 100ns */ |
| 65 | |
Andi Kleen | 553f265 | 2006-04-07 19:49:57 +0200 | [diff] [blame] | 66 | atomic_t mce_entry; |
| 67 | |
Andi Kleen | 01ca79f | 2009-05-27 21:56:52 +0200 | [diff] [blame] | 68 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
| 69 | |
Tim Hockin | bd78432 | 2007-07-21 17:10:37 +0200 | [diff] [blame] | 70 | /* |
| 71 | * Tolerant levels: |
| 72 | * 0: always panic on uncorrected errors, log corrected errors |
| 73 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors |
| 74 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors |
| 75 | * 3: never panic or SIGBUS, log all errors (for testing only) |
| 76 | */ |
Hidetoshi Seto | 4e5b3e6 | 2009-06-15 17:20:20 +0900 | [diff] [blame] | 77 | static int tolerant __read_mostly = 1; |
| 78 | static int banks __read_mostly; |
Hidetoshi Seto | 4e5b3e6 | 2009-06-15 17:20:20 +0900 | [diff] [blame] | 79 | static int rip_msr __read_mostly; |
| 80 | static int mce_bootlog __read_mostly = -1; |
| 81 | static int monarch_timeout __read_mostly = -1; |
| 82 | static int mce_panic_timeout __read_mostly; |
| 83 | static int mce_dont_log_ce __read_mostly; |
| 84 | int mce_cmci_disabled __read_mostly; |
| 85 | int mce_ignore_ce __read_mostly; |
| 86 | int mce_ser __read_mostly; |
Andi Kleen | a98f0dd | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 87 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 88 | struct mce_bank *mce_banks __read_mostly; |
| 89 | |
Hidetoshi Seto | 1020bcb | 2009-06-15 17:20:57 +0900 | [diff] [blame] | 90 | /* User mode helper program triggered by machine check event */ |
| 91 | static unsigned long mce_need_notify; |
| 92 | static char mce_helper[128]; |
| 93 | static char *mce_helper_argv[2] = { mce_helper, NULL }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 94 | |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 95 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 96 | static DEFINE_PER_CPU(struct mce, mces_seen); |
| 97 | static int cpu_missing; |
| 98 | |
Borislav Petkov | fb25319 | 2009-10-07 13:20:38 +0200 | [diff] [blame] | 99 | /* |
| 100 | * CPU/chipset specific EDAC code can register a notifier call here to print |
| 101 | * MCE errors in a human-readable form. |
| 102 | */ |
| 103 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); |
| 104 | EXPORT_SYMBOL_GPL(x86_mce_decoder_chain); |
| 105 | |
| 106 | static int default_decode_mce(struct notifier_block *nb, unsigned long val, |
| 107 | void *data) |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame] | 108 | { |
| 109 | pr_emerg("No human readable MCE decoding support on this CPU type.\n"); |
| 110 | pr_emerg("Run the message through 'mcelog --ascii' to decode.\n"); |
Borislav Petkov | fb25319 | 2009-10-07 13:20:38 +0200 | [diff] [blame] | 111 | |
| 112 | return NOTIFY_STOP; |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame] | 113 | } |
| 114 | |
Borislav Petkov | fb25319 | 2009-10-07 13:20:38 +0200 | [diff] [blame] | 115 | static struct notifier_block mce_dec_nb = { |
| 116 | .notifier_call = default_decode_mce, |
| 117 | .priority = -1, |
| 118 | }; |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 119 | |
Andi Kleen | ee031c3 | 2009-02-12 13:49:34 +0100 | [diff] [blame] | 120 | /* MCA banks polled by the period polling timer for corrected events */ |
| 121 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { |
| 122 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL |
| 123 | }; |
| 124 | |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 125 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
| 126 | |
Andi Kleen | b5f2fa4 | 2009-02-12 13:43:22 +0100 | [diff] [blame] | 127 | /* Do initial initialization of a struct mce */ |
| 128 | void mce_setup(struct mce *m) |
| 129 | { |
| 130 | memset(m, 0, sizeof(struct mce)); |
Andi Kleen | d620c67 | 2009-05-27 21:56:56 +0200 | [diff] [blame] | 131 | m->cpu = m->extcpu = smp_processor_id(); |
Andi Kleen | b5f2fa4 | 2009-02-12 13:43:22 +0100 | [diff] [blame] | 132 | rdtscll(m->tsc); |
Andi Kleen | 8ee0834 | 2009-05-27 21:56:56 +0200 | [diff] [blame] | 133 | /* We hope get_seconds stays lockless */ |
| 134 | m->time = get_seconds(); |
| 135 | m->cpuvendor = boot_cpu_data.x86_vendor; |
| 136 | m->cpuid = cpuid_eax(1); |
| 137 | #ifdef CONFIG_SMP |
| 138 | m->socketid = cpu_data(m->extcpu).phys_proc_id; |
| 139 | #endif |
| 140 | m->apicid = cpu_data(m->extcpu).initial_apicid; |
| 141 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); |
Andi Kleen | b5f2fa4 | 2009-02-12 13:43:22 +0100 | [diff] [blame] | 142 | } |
| 143 | |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 144 | DEFINE_PER_CPU(struct mce, injectm); |
| 145 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); |
| 146 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 147 | /* |
| 148 | * Lockless MCE logging infrastructure. |
| 149 | * This avoids deadlocks on printk locks without having to break locks. Also |
| 150 | * separate MCEs from kernel messages to avoid bogus bug reports. |
| 151 | */ |
| 152 | |
Adrian Bunk | 231fd90 | 2008-01-30 13:30:30 +0100 | [diff] [blame] | 153 | static struct mce_log mcelog = { |
Andi Kleen | f6fb0ac | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 154 | .signature = MCE_LOG_SIGNATURE, |
| 155 | .len = MCE_LOG_LEN, |
| 156 | .recordlen = sizeof(struct mce), |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 157 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 158 | |
| 159 | void mce_log(struct mce *mce) |
| 160 | { |
| 161 | unsigned next, entry; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 162 | |
Hidetoshi Seto | 8968f9d | 2009-10-13 16:19:41 +0900 | [diff] [blame] | 163 | /* Emit the trace record: */ |
| 164 | trace_mce_record(mce); |
| 165 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 166 | mce->finished = 0; |
Mike Waychison | 7644143 | 2005-09-30 00:01:27 +0200 | [diff] [blame] | 167 | wmb(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 168 | for (;;) { |
Paul E. McKenney | f56e8a0 | 2010-03-05 15:03:27 -0800 | [diff] [blame] | 169 | entry = rcu_dereference_check_mce(mcelog.next); |
Andi Kleen | 673242c | 2005-09-12 18:49:24 +0200 | [diff] [blame] | 170 | for (;;) { |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 171 | /* |
| 172 | * When the buffer fills up discard new entries. |
| 173 | * Assume that the earlier errors are the more |
| 174 | * interesting ones: |
| 175 | */ |
Andi Kleen | 673242c | 2005-09-12 18:49:24 +0200 | [diff] [blame] | 176 | if (entry >= MCE_LOG_LEN) { |
Hidetoshi Seto | 14a0253 | 2009-04-30 16:04:51 +0900 | [diff] [blame] | 177 | set_bit(MCE_OVERFLOW, |
| 178 | (unsigned long *)&mcelog.flags); |
Andi Kleen | 673242c | 2005-09-12 18:49:24 +0200 | [diff] [blame] | 179 | return; |
| 180 | } |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 181 | /* Old left over entry. Skip: */ |
Andi Kleen | 673242c | 2005-09-12 18:49:24 +0200 | [diff] [blame] | 182 | if (mcelog.entry[entry].finished) { |
| 183 | entry++; |
| 184 | continue; |
| 185 | } |
Mike Waychison | 7644143 | 2005-09-30 00:01:27 +0200 | [diff] [blame] | 186 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 187 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 188 | smp_rmb(); |
| 189 | next = entry + 1; |
| 190 | if (cmpxchg(&mcelog.next, entry, next) == entry) |
| 191 | break; |
| 192 | } |
| 193 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); |
Mike Waychison | 7644143 | 2005-09-30 00:01:27 +0200 | [diff] [blame] | 194 | wmb(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 195 | mcelog.entry[entry].finished = 1; |
Mike Waychison | 7644143 | 2005-09-30 00:01:27 +0200 | [diff] [blame] | 196 | wmb(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 197 | |
Andi Kleen | a0189c7 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 198 | mce->finished = 1; |
Hidetoshi Seto | 1020bcb | 2009-06-15 17:20:57 +0900 | [diff] [blame] | 199 | set_bit(0, &mce_need_notify); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 200 | } |
| 201 | |
Hidetoshi Seto | 77e26cc | 2009-06-11 16:04:35 +0900 | [diff] [blame] | 202 | static void print_mce(struct mce *m) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 203 | { |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame] | 204 | pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", |
Andi Kleen | d620c67 | 2009-05-27 21:56:56 +0200 | [diff] [blame] | 205 | m->extcpu, m->mcgstatus, m->bank, m->status); |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame] | 206 | |
H. Peter Anvin | 65ea5b0 | 2008-01-30 13:30:56 +0100 | [diff] [blame] | 207 | if (m->ip) { |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame] | 208 | pr_emerg("RIP%s %02x:<%016Lx> ", |
| 209 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
| 210 | m->cs, m->ip); |
| 211 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | if (m->cs == __KERNEL_CS) |
H. Peter Anvin | 65ea5b0 | 2008-01-30 13:30:56 +0100 | [diff] [blame] | 213 | print_symbol("{%s}", m->ip); |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame] | 214 | pr_cont("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 215 | } |
Borislav Petkov | 549d042 | 2009-07-24 13:51:42 +0200 | [diff] [blame] | 216 | |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame] | 217 | pr_emerg("TSC %llx ", m->tsc); |
| 218 | if (m->addr) |
| 219 | pr_cont("ADDR %llx ", m->addr); |
| 220 | if (m->misc) |
| 221 | pr_cont("MISC %llx ", m->misc); |
| 222 | |
| 223 | pr_cont("\n"); |
| 224 | pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", |
| 225 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid); |
| 226 | |
| 227 | /* |
| 228 | * Print out human-readable details about the MCE error, |
Borislav Petkov | fb25319 | 2009-10-07 13:20:38 +0200 | [diff] [blame] | 229 | * (if the CPU has an implementation for that) |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame] | 230 | */ |
Borislav Petkov | fb25319 | 2009-10-07 13:20:38 +0200 | [diff] [blame] | 231 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
Andi Kleen | 8650356 | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 232 | } |
| 233 | |
Hidetoshi Seto | 77e26cc | 2009-06-11 16:04:35 +0900 | [diff] [blame] | 234 | static void print_mce_head(void) |
| 235 | { |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame] | 236 | pr_emerg("\nHARDWARE ERROR\n"); |
Hidetoshi Seto | 77e26cc | 2009-06-11 16:04:35 +0900 | [diff] [blame] | 237 | } |
| 238 | |
Andi Kleen | 8650356 | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 239 | static void print_mce_tail(void) |
| 240 | { |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame] | 241 | pr_emerg("This is not a software problem!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 242 | } |
| 243 | |
Andi Kleen | f94b61c | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 244 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
| 245 | |
| 246 | static atomic_t mce_paniced; |
| 247 | |
Huang Ying | bf783f9 | 2009-07-31 09:41:43 +0800 | [diff] [blame] | 248 | static int fake_panic; |
| 249 | static atomic_t mce_fake_paniced; |
| 250 | |
Andi Kleen | f94b61c | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 251 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
| 252 | static void wait_for_panic(void) |
| 253 | { |
| 254 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame] | 255 | |
Andi Kleen | f94b61c | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 256 | preempt_disable(); |
| 257 | local_irq_enable(); |
| 258 | while (timeout-- > 0) |
| 259 | udelay(1); |
Andi Kleen | 29b0f59 | 2009-05-27 21:56:56 +0200 | [diff] [blame] | 260 | if (panic_timeout == 0) |
| 261 | panic_timeout = mce_panic_timeout; |
Andi Kleen | f94b61c | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 262 | panic("Panicing machine check CPU died"); |
| 263 | } |
| 264 | |
Andi Kleen | bd19a5e | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 265 | static void mce_panic(char *msg, struct mce *final, char *exp) |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 266 | { |
Huang Ying | 482908b | 2010-05-18 14:35:22 +0800 | [diff] [blame^] | 267 | int i, apei_err = 0; |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 268 | |
Huang Ying | bf783f9 | 2009-07-31 09:41:43 +0800 | [diff] [blame] | 269 | if (!fake_panic) { |
| 270 | /* |
| 271 | * Make sure only one CPU runs in machine check panic |
| 272 | */ |
| 273 | if (atomic_inc_return(&mce_paniced) > 1) |
| 274 | wait_for_panic(); |
| 275 | barrier(); |
Andi Kleen | f94b61c | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 276 | |
Huang Ying | bf783f9 | 2009-07-31 09:41:43 +0800 | [diff] [blame] | 277 | bust_spinlocks(1); |
| 278 | console_verbose(); |
| 279 | } else { |
| 280 | /* Don't log too much for fake panic */ |
| 281 | if (atomic_inc_return(&mce_fake_paniced) > 1) |
| 282 | return; |
| 283 | } |
Hidetoshi Seto | 77e26cc | 2009-06-11 16:04:35 +0900 | [diff] [blame] | 284 | print_mce_head(); |
Andi Kleen | a0189c7 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 285 | /* First print corrected ones that are still unlogged */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 286 | for (i = 0; i < MCE_LOG_LEN; i++) { |
Andi Kleen | a0189c7 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 287 | struct mce *m = &mcelog.entry[i]; |
Hidetoshi Seto | 77e26cc | 2009-06-11 16:04:35 +0900 | [diff] [blame] | 288 | if (!(m->status & MCI_STATUS_VAL)) |
| 289 | continue; |
Huang Ying | 482908b | 2010-05-18 14:35:22 +0800 | [diff] [blame^] | 290 | if (!(m->status & MCI_STATUS_UC)) { |
Hidetoshi Seto | 77e26cc | 2009-06-11 16:04:35 +0900 | [diff] [blame] | 291 | print_mce(m); |
Huang Ying | 482908b | 2010-05-18 14:35:22 +0800 | [diff] [blame^] | 292 | if (!apei_err) |
| 293 | apei_err = apei_write_mce(m); |
| 294 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 295 | } |
Andi Kleen | a0189c7 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 296 | /* Now print uncorrected but with the final one last */ |
| 297 | for (i = 0; i < MCE_LOG_LEN; i++) { |
| 298 | struct mce *m = &mcelog.entry[i]; |
| 299 | if (!(m->status & MCI_STATUS_VAL)) |
| 300 | continue; |
Hidetoshi Seto | 77e26cc | 2009-06-11 16:04:35 +0900 | [diff] [blame] | 301 | if (!(m->status & MCI_STATUS_UC)) |
| 302 | continue; |
Huang Ying | 482908b | 2010-05-18 14:35:22 +0800 | [diff] [blame^] | 303 | if (!final || memcmp(m, final, sizeof(struct mce))) { |
Hidetoshi Seto | 77e26cc | 2009-06-11 16:04:35 +0900 | [diff] [blame] | 304 | print_mce(m); |
Huang Ying | 482908b | 2010-05-18 14:35:22 +0800 | [diff] [blame^] | 305 | if (!apei_err) |
| 306 | apei_err = apei_write_mce(m); |
| 307 | } |
Andi Kleen | a0189c7 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 308 | } |
Huang Ying | 482908b | 2010-05-18 14:35:22 +0800 | [diff] [blame^] | 309 | if (final) { |
Hidetoshi Seto | 77e26cc | 2009-06-11 16:04:35 +0900 | [diff] [blame] | 310 | print_mce(final); |
Huang Ying | 482908b | 2010-05-18 14:35:22 +0800 | [diff] [blame^] | 311 | if (!apei_err) |
| 312 | apei_err = apei_write_mce(final); |
| 313 | } |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 314 | if (cpu_missing) |
| 315 | printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n"); |
Andi Kleen | 8650356 | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 316 | print_mce_tail(); |
Andi Kleen | bd19a5e | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 317 | if (exp) |
| 318 | printk(KERN_EMERG "Machine check: %s\n", exp); |
Huang Ying | bf783f9 | 2009-07-31 09:41:43 +0800 | [diff] [blame] | 319 | if (!fake_panic) { |
| 320 | if (panic_timeout == 0) |
| 321 | panic_timeout = mce_panic_timeout; |
| 322 | panic(msg); |
| 323 | } else |
| 324 | printk(KERN_EMERG "Fake kernel panic: %s\n", msg); |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 325 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 326 | |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 327 | /* Support code for software error injection */ |
| 328 | |
| 329 | static int msr_to_offset(u32 msr) |
| 330 | { |
| 331 | unsigned bank = __get_cpu_var(injectm.bank); |
Ingo Molnar | f436f8b | 2009-10-01 16:14:32 +0200 | [diff] [blame] | 332 | |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 333 | if (msr == rip_msr) |
| 334 | return offsetof(struct mce, ip); |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 335 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 336 | return offsetof(struct mce, status); |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 337 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 338 | return offsetof(struct mce, addr); |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 339 | if (msr == MSR_IA32_MCx_MISC(bank)) |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 340 | return offsetof(struct mce, misc); |
| 341 | if (msr == MSR_IA32_MCG_STATUS) |
| 342 | return offsetof(struct mce, mcgstatus); |
| 343 | return -1; |
| 344 | } |
| 345 | |
Andi Kleen | 5f8c1a5 | 2009-04-29 19:29:12 +0200 | [diff] [blame] | 346 | /* MSR access wrappers used for error injection */ |
| 347 | static u64 mce_rdmsrl(u32 msr) |
| 348 | { |
| 349 | u64 v; |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 350 | |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 351 | if (__get_cpu_var(injectm).finished) { |
| 352 | int offset = msr_to_offset(msr); |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 353 | |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 354 | if (offset < 0) |
| 355 | return 0; |
| 356 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); |
| 357 | } |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 358 | |
| 359 | if (rdmsrl_safe(msr, &v)) { |
| 360 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); |
| 361 | /* |
| 362 | * Return zero in case the access faulted. This should |
| 363 | * not happen normally but can happen if the CPU does |
| 364 | * something weird, or if the code is buggy. |
| 365 | */ |
| 366 | v = 0; |
| 367 | } |
| 368 | |
Andi Kleen | 5f8c1a5 | 2009-04-29 19:29:12 +0200 | [diff] [blame] | 369 | return v; |
| 370 | } |
| 371 | |
| 372 | static void mce_wrmsrl(u32 msr, u64 v) |
| 373 | { |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 374 | if (__get_cpu_var(injectm).finished) { |
| 375 | int offset = msr_to_offset(msr); |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 376 | |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 377 | if (offset >= 0) |
| 378 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; |
| 379 | return; |
| 380 | } |
Andi Kleen | 5f8c1a5 | 2009-04-29 19:29:12 +0200 | [diff] [blame] | 381 | wrmsrl(msr, v); |
| 382 | } |
| 383 | |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 384 | /* |
| 385 | * Simple lockless ring to communicate PFNs from the exception handler with the |
| 386 | * process context work function. This is vastly simplified because there's |
| 387 | * only a single reader and a single writer. |
| 388 | */ |
| 389 | #define MCE_RING_SIZE 16 /* we use one entry less */ |
| 390 | |
| 391 | struct mce_ring { |
| 392 | unsigned short start; |
| 393 | unsigned short end; |
| 394 | unsigned long ring[MCE_RING_SIZE]; |
| 395 | }; |
| 396 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); |
| 397 | |
| 398 | /* Runs with CPU affinity in workqueue */ |
| 399 | static int mce_ring_empty(void) |
| 400 | { |
| 401 | struct mce_ring *r = &__get_cpu_var(mce_ring); |
| 402 | |
| 403 | return r->start == r->end; |
| 404 | } |
| 405 | |
| 406 | static int mce_ring_get(unsigned long *pfn) |
| 407 | { |
| 408 | struct mce_ring *r; |
| 409 | int ret = 0; |
| 410 | |
| 411 | *pfn = 0; |
| 412 | get_cpu(); |
| 413 | r = &__get_cpu_var(mce_ring); |
| 414 | if (r->start == r->end) |
| 415 | goto out; |
| 416 | *pfn = r->ring[r->start]; |
| 417 | r->start = (r->start + 1) % MCE_RING_SIZE; |
| 418 | ret = 1; |
| 419 | out: |
| 420 | put_cpu(); |
| 421 | return ret; |
| 422 | } |
| 423 | |
| 424 | /* Always runs in MCE context with preempt off */ |
| 425 | static int mce_ring_add(unsigned long pfn) |
| 426 | { |
| 427 | struct mce_ring *r = &__get_cpu_var(mce_ring); |
| 428 | unsigned next; |
| 429 | |
| 430 | next = (r->end + 1) % MCE_RING_SIZE; |
| 431 | if (next == r->start) |
| 432 | return -1; |
| 433 | r->ring[r->end] = pfn; |
| 434 | wmb(); |
| 435 | r->end = next; |
| 436 | return 0; |
| 437 | } |
| 438 | |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 439 | int mce_available(struct cpuinfo_x86 *c) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 440 | { |
Andi Kleen | 04b2b1a | 2009-04-28 22:50:19 +0200 | [diff] [blame] | 441 | if (mce_disabled) |
Andi Kleen | 5b4408f | 2009-02-12 13:39:30 +0100 | [diff] [blame] | 442 | return 0; |
Akinobu Mita | 3d1712c | 2006-03-24 03:15:11 -0800 | [diff] [blame] | 443 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 444 | } |
| 445 | |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 446 | static void mce_schedule_work(void) |
| 447 | { |
| 448 | if (!mce_ring_empty()) { |
| 449 | struct work_struct *work = &__get_cpu_var(mce_work); |
| 450 | if (!work_pending(work)) |
| 451 | schedule_work(work); |
| 452 | } |
| 453 | } |
| 454 | |
Huang Ying | 1b2797d | 2009-05-27 21:56:51 +0200 | [diff] [blame] | 455 | /* |
| 456 | * Get the address of the instruction at the time of the machine check |
| 457 | * error. |
| 458 | */ |
Andi Kleen | 94ad847 | 2005-04-16 15:25:09 -0700 | [diff] [blame] | 459 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
| 460 | { |
Huang Ying | 1b2797d | 2009-05-27 21:56:51 +0200 | [diff] [blame] | 461 | |
| 462 | if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) { |
H. Peter Anvin | 65ea5b0 | 2008-01-30 13:30:56 +0100 | [diff] [blame] | 463 | m->ip = regs->ip; |
Andi Kleen | 94ad847 | 2005-04-16 15:25:09 -0700 | [diff] [blame] | 464 | m->cs = regs->cs; |
| 465 | } else { |
H. Peter Anvin | 65ea5b0 | 2008-01-30 13:30:56 +0100 | [diff] [blame] | 466 | m->ip = 0; |
Andi Kleen | 94ad847 | 2005-04-16 15:25:09 -0700 | [diff] [blame] | 467 | m->cs = 0; |
| 468 | } |
Huang Ying | 1b2797d | 2009-05-27 21:56:51 +0200 | [diff] [blame] | 469 | if (rip_msr) |
Andi Kleen | 5f8c1a5 | 2009-04-29 19:29:12 +0200 | [diff] [blame] | 470 | m->ip = mce_rdmsrl(rip_msr); |
Andi Kleen | 94ad847 | 2005-04-16 15:25:09 -0700 | [diff] [blame] | 471 | } |
| 472 | |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 473 | #ifdef CONFIG_X86_LOCAL_APIC |
Andi Kleen | ccc3c31 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 474 | /* |
| 475 | * Called after interrupts have been reenabled again |
| 476 | * when a MCE happened during an interrupts off region |
| 477 | * in the kernel. |
| 478 | */ |
| 479 | asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs) |
| 480 | { |
| 481 | ack_APIC_irq(); |
| 482 | exit_idle(); |
| 483 | irq_enter(); |
Andi Kleen | 9ff36ee | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 484 | mce_notify_irq(); |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 485 | mce_schedule_work(); |
Andi Kleen | ccc3c31 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 486 | irq_exit(); |
| 487 | } |
| 488 | #endif |
| 489 | |
| 490 | static void mce_report_event(struct pt_regs *regs) |
| 491 | { |
| 492 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { |
Andi Kleen | 9ff36ee | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 493 | mce_notify_irq(); |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 494 | /* |
| 495 | * Triggering the work queue here is just an insurance |
| 496 | * policy in case the syscall exit notify handler |
| 497 | * doesn't run soon enough or ends up running on the |
| 498 | * wrong CPU (can happen when audit sleeps) |
| 499 | */ |
| 500 | mce_schedule_work(); |
Andi Kleen | ccc3c31 | 2009-05-27 21:56:54 +0200 | [diff] [blame] | 501 | return; |
| 502 | } |
| 503 | |
| 504 | #ifdef CONFIG_X86_LOCAL_APIC |
| 505 | /* |
| 506 | * Without APIC do not notify. The event will be picked |
| 507 | * up eventually. |
| 508 | */ |
| 509 | if (!cpu_has_apic) |
| 510 | return; |
| 511 | |
| 512 | /* |
| 513 | * When interrupts are disabled we cannot use |
| 514 | * kernel services safely. Trigger an self interrupt |
| 515 | * through the APIC to instead do the notification |
| 516 | * after interrupts are reenabled again. |
| 517 | */ |
| 518 | apic->send_IPI_self(MCE_SELF_VECTOR); |
| 519 | |
| 520 | /* |
| 521 | * Wait for idle afterwards again so that we don't leave the |
| 522 | * APIC in a non idle state because the normal APIC writes |
| 523 | * cannot exclude us. |
| 524 | */ |
| 525 | apic_wait_icr_idle(); |
| 526 | #endif |
| 527 | } |
| 528 | |
Andi Kleen | ca84f69 | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 529 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
| 530 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 531 | /* |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 532 | * Poll for corrected events or events that happened before reset. |
| 533 | * Those are just logged through /dev/mcelog. |
| 534 | * |
| 535 | * This is executed in standard interrupt context. |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 536 | * |
| 537 | * Note: spec recommends to panic for fatal unsignalled |
| 538 | * errors here. However this would be quite problematic -- |
| 539 | * we would need to reimplement the Monarch handling and |
| 540 | * it would mess up the exclusion between exception handler |
| 541 | * and poll hander -- * so we skip this for now. |
| 542 | * These cases should not happen anyways, or only when the CPU |
| 543 | * is already totally * confused. In this case it's likely it will |
| 544 | * not fully execute the machine check handler either. |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 545 | */ |
Andi Kleen | ee031c3 | 2009-02-12 13:49:34 +0100 | [diff] [blame] | 546 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 547 | { |
| 548 | struct mce m; |
| 549 | int i; |
| 550 | |
Andi Kleen | ca84f69 | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 551 | __get_cpu_var(mce_poll_count)++; |
| 552 | |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 553 | mce_setup(&m); |
| 554 | |
Andi Kleen | 5f8c1a5 | 2009-04-29 19:29:12 +0200 | [diff] [blame] | 555 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 556 | for (i = 0; i < banks; i++) { |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 557 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 558 | continue; |
| 559 | |
| 560 | m.misc = 0; |
| 561 | m.addr = 0; |
| 562 | m.bank = i; |
| 563 | m.tsc = 0; |
| 564 | |
| 565 | barrier(); |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 566 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 567 | if (!(m.status & MCI_STATUS_VAL)) |
| 568 | continue; |
| 569 | |
| 570 | /* |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 571 | * Uncorrected or signalled events are handled by the exception |
| 572 | * handler when it is enabled, so don't process those here. |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 573 | * |
| 574 | * TBD do the same check for MCI_STATUS_EN here? |
| 575 | */ |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 576 | if (!(flags & MCP_UC) && |
| 577 | (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 578 | continue; |
| 579 | |
| 580 | if (m.status & MCI_STATUS_MISCV) |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 581 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 582 | if (m.status & MCI_STATUS_ADDRV) |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 583 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 584 | |
| 585 | if (!(flags & MCP_TIMESTAMP)) |
| 586 | m.tsc = 0; |
| 587 | /* |
| 588 | * Don't get the IP here because it's unlikely to |
| 589 | * have anything to do with the actual error location. |
| 590 | */ |
Hidetoshi Seto | 62fdac5 | 2009-06-11 16:06:07 +0900 | [diff] [blame] | 591 | if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) { |
Andi Kleen | 5679af4 | 2009-04-07 17:06:55 +0200 | [diff] [blame] | 592 | mce_log(&m); |
| 593 | add_taint(TAINT_MACHINE_CHECK); |
| 594 | } |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 595 | |
| 596 | /* |
| 597 | * Clear state for this bank. |
| 598 | */ |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 599 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 600 | } |
| 601 | |
| 602 | /* |
| 603 | * Don't clear MCG_STATUS here because it's only defined for |
| 604 | * exceptions. |
| 605 | */ |
Andi Kleen | 88921be | 2009-05-27 21:56:51 +0200 | [diff] [blame] | 606 | |
| 607 | sync_core(); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 608 | } |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 609 | EXPORT_SYMBOL_GPL(machine_check_poll); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 610 | |
| 611 | /* |
Andi Kleen | bd19a5e | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 612 | * Do a quick check if any of the events requires a panic. |
| 613 | * This decides if we keep the events around or clear them. |
| 614 | */ |
| 615 | static int mce_no_way_out(struct mce *m, char **msg) |
| 616 | { |
| 617 | int i; |
| 618 | |
| 619 | for (i = 0; i < banks; i++) { |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 620 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
Andi Kleen | bd19a5e | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 621 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) |
| 622 | return 1; |
| 623 | } |
| 624 | return 0; |
| 625 | } |
| 626 | |
| 627 | /* |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 628 | * Variable to establish order between CPUs while scanning. |
| 629 | * Each CPU spins initially until executing is equal its number. |
| 630 | */ |
| 631 | static atomic_t mce_executing; |
| 632 | |
| 633 | /* |
| 634 | * Defines order of CPUs on entry. First CPU becomes Monarch. |
| 635 | */ |
| 636 | static atomic_t mce_callin; |
| 637 | |
| 638 | /* |
| 639 | * Check if a timeout waiting for other CPUs happened. |
| 640 | */ |
| 641 | static int mce_timed_out(u64 *t) |
| 642 | { |
| 643 | /* |
| 644 | * The others already did panic for some reason. |
| 645 | * Bail out like in a timeout. |
| 646 | * rmb() to tell the compiler that system_state |
| 647 | * might have been modified by someone else. |
| 648 | */ |
| 649 | rmb(); |
| 650 | if (atomic_read(&mce_paniced)) |
| 651 | wait_for_panic(); |
| 652 | if (!monarch_timeout) |
| 653 | goto out; |
| 654 | if ((s64)*t < SPINUNIT) { |
| 655 | /* CHECKME: Make panic default for 1 too? */ |
| 656 | if (tolerant < 1) |
| 657 | mce_panic("Timeout synchronizing machine check over CPUs", |
| 658 | NULL, NULL); |
| 659 | cpu_missing = 1; |
| 660 | return 1; |
| 661 | } |
| 662 | *t -= SPINUNIT; |
| 663 | out: |
| 664 | touch_nmi_watchdog(); |
| 665 | return 0; |
| 666 | } |
| 667 | |
| 668 | /* |
| 669 | * The Monarch's reign. The Monarch is the CPU who entered |
| 670 | * the machine check handler first. It waits for the others to |
| 671 | * raise the exception too and then grades them. When any |
| 672 | * error is fatal panic. Only then let the others continue. |
| 673 | * |
| 674 | * The other CPUs entering the MCE handler will be controlled by the |
| 675 | * Monarch. They are called Subjects. |
| 676 | * |
| 677 | * This way we prevent any potential data corruption in a unrecoverable case |
| 678 | * and also makes sure always all CPU's errors are examined. |
| 679 | * |
Hidetoshi Seto | 680b6cf | 2009-08-26 16:20:36 +0900 | [diff] [blame] | 680 | * Also this detects the case of a machine check event coming from outer |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 681 | * space (not detected by any CPUs) In this case some external agent wants |
| 682 | * us to shut down, so panic too. |
| 683 | * |
| 684 | * The other CPUs might still decide to panic if the handler happens |
| 685 | * in a unrecoverable place, but in this case the system is in a semi-stable |
| 686 | * state and won't corrupt anything by itself. It's ok to let the others |
| 687 | * continue for a bit first. |
| 688 | * |
| 689 | * All the spin loops have timeouts; when a timeout happens a CPU |
| 690 | * typically elects itself to be Monarch. |
| 691 | */ |
| 692 | static void mce_reign(void) |
| 693 | { |
| 694 | int cpu; |
| 695 | struct mce *m = NULL; |
| 696 | int global_worst = 0; |
| 697 | char *msg = NULL; |
| 698 | char *nmsg = NULL; |
| 699 | |
| 700 | /* |
| 701 | * This CPU is the Monarch and the other CPUs have run |
| 702 | * through their handlers. |
| 703 | * Grade the severity of the errors of all the CPUs. |
| 704 | */ |
| 705 | for_each_possible_cpu(cpu) { |
| 706 | int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, |
| 707 | &nmsg); |
| 708 | if (severity > global_worst) { |
| 709 | msg = nmsg; |
| 710 | global_worst = severity; |
| 711 | m = &per_cpu(mces_seen, cpu); |
| 712 | } |
| 713 | } |
| 714 | |
| 715 | /* |
| 716 | * Cannot recover? Panic here then. |
| 717 | * This dumps all the mces in the log buffer and stops the |
| 718 | * other CPUs. |
| 719 | */ |
| 720 | if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) |
Andi Kleen | ac96037 | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 721 | mce_panic("Fatal Machine check", m, msg); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 722 | |
| 723 | /* |
| 724 | * For UC somewhere we let the CPU who detects it handle it. |
| 725 | * Also must let continue the others, otherwise the handling |
| 726 | * CPU could deadlock on a lock. |
| 727 | */ |
| 728 | |
| 729 | /* |
| 730 | * No machine check event found. Must be some external |
| 731 | * source or one CPU is hung. Panic. |
| 732 | */ |
Hidetoshi Seto | 680b6cf | 2009-08-26 16:20:36 +0900 | [diff] [blame] | 733 | if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3) |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 734 | mce_panic("Machine check from unknown source", NULL, NULL); |
| 735 | |
| 736 | /* |
| 737 | * Now clear all the mces_seen so that they don't reappear on |
| 738 | * the next mce. |
| 739 | */ |
| 740 | for_each_possible_cpu(cpu) |
| 741 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); |
| 742 | } |
| 743 | |
| 744 | static atomic_t global_nwo; |
| 745 | |
| 746 | /* |
| 747 | * Start of Monarch synchronization. This waits until all CPUs have |
| 748 | * entered the exception handler and then determines if any of them |
| 749 | * saw a fatal event that requires panic. Then it executes them |
| 750 | * in the entry order. |
| 751 | * TBD double check parallel CPU hotunplug |
| 752 | */ |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 753 | static int mce_start(int *no_way_out) |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 754 | { |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 755 | int order; |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 756 | int cpus = num_online_cpus(); |
| 757 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; |
| 758 | |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 759 | if (!timeout) |
| 760 | return -1; |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 761 | |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 762 | atomic_add(*no_way_out, &global_nwo); |
Huang Ying | 184e1fd | 2009-06-15 15:37:07 +0800 | [diff] [blame] | 763 | /* |
| 764 | * global_nwo should be updated before mce_callin |
| 765 | */ |
| 766 | smp_wmb(); |
Borislav Petkov | a95436e | 2009-06-20 23:28:22 -0700 | [diff] [blame] | 767 | order = atomic_inc_return(&mce_callin); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 768 | |
| 769 | /* |
| 770 | * Wait for everyone. |
| 771 | */ |
| 772 | while (atomic_read(&mce_callin) != cpus) { |
| 773 | if (mce_timed_out(&timeout)) { |
| 774 | atomic_set(&global_nwo, 0); |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 775 | return -1; |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 776 | } |
| 777 | ndelay(SPINUNIT); |
| 778 | } |
| 779 | |
| 780 | /* |
Huang Ying | 184e1fd | 2009-06-15 15:37:07 +0800 | [diff] [blame] | 781 | * mce_callin should be read before global_nwo |
| 782 | */ |
| 783 | smp_rmb(); |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 784 | |
| 785 | if (order == 1) { |
| 786 | /* |
| 787 | * Monarch: Starts executing now, the others wait. |
| 788 | */ |
| 789 | atomic_set(&mce_executing, 1); |
| 790 | } else { |
| 791 | /* |
| 792 | * Subject: Now start the scanning loop one by one in |
| 793 | * the original callin order. |
| 794 | * This way when there are any shared banks it will be |
| 795 | * only seen by one CPU before cleared, avoiding duplicates. |
| 796 | */ |
| 797 | while (atomic_read(&mce_executing) < order) { |
| 798 | if (mce_timed_out(&timeout)) { |
| 799 | atomic_set(&global_nwo, 0); |
| 800 | return -1; |
| 801 | } |
| 802 | ndelay(SPINUNIT); |
| 803 | } |
| 804 | } |
| 805 | |
Huang Ying | 184e1fd | 2009-06-15 15:37:07 +0800 | [diff] [blame] | 806 | /* |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 807 | * Cache the global no_way_out state. |
| 808 | */ |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 809 | *no_way_out = atomic_read(&global_nwo); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 810 | |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 811 | return order; |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 812 | } |
| 813 | |
| 814 | /* |
| 815 | * Synchronize between CPUs after main scanning loop. |
| 816 | * This invokes the bulk of the Monarch processing. |
| 817 | */ |
| 818 | static int mce_end(int order) |
| 819 | { |
| 820 | int ret = -1; |
| 821 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; |
| 822 | |
| 823 | if (!timeout) |
| 824 | goto reset; |
| 825 | if (order < 0) |
| 826 | goto reset; |
| 827 | |
| 828 | /* |
| 829 | * Allow others to run. |
| 830 | */ |
| 831 | atomic_inc(&mce_executing); |
| 832 | |
| 833 | if (order == 1) { |
| 834 | /* CHECKME: Can this race with a parallel hotplug? */ |
| 835 | int cpus = num_online_cpus(); |
| 836 | |
| 837 | /* |
| 838 | * Monarch: Wait for everyone to go through their scanning |
| 839 | * loops. |
| 840 | */ |
| 841 | while (atomic_read(&mce_executing) <= cpus) { |
| 842 | if (mce_timed_out(&timeout)) |
| 843 | goto reset; |
| 844 | ndelay(SPINUNIT); |
| 845 | } |
| 846 | |
| 847 | mce_reign(); |
| 848 | barrier(); |
| 849 | ret = 0; |
| 850 | } else { |
| 851 | /* |
| 852 | * Subject: Wait for Monarch to finish. |
| 853 | */ |
| 854 | while (atomic_read(&mce_executing) != 0) { |
| 855 | if (mce_timed_out(&timeout)) |
| 856 | goto reset; |
| 857 | ndelay(SPINUNIT); |
| 858 | } |
| 859 | |
| 860 | /* |
| 861 | * Don't reset anything. That's done by the Monarch. |
| 862 | */ |
| 863 | return 0; |
| 864 | } |
| 865 | |
| 866 | /* |
| 867 | * Reset all global state. |
| 868 | */ |
| 869 | reset: |
| 870 | atomic_set(&global_nwo, 0); |
| 871 | atomic_set(&mce_callin, 0); |
| 872 | barrier(); |
| 873 | |
| 874 | /* |
| 875 | * Let others run again. |
| 876 | */ |
| 877 | atomic_set(&mce_executing, 0); |
| 878 | return ret; |
| 879 | } |
| 880 | |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 881 | /* |
| 882 | * Check if the address reported by the CPU is in a format we can parse. |
| 883 | * It would be possible to add code for most other cases, but all would |
| 884 | * be somewhat complicated (e.g. segment offset would require an instruction |
| 885 | * parser). So only support physical addresses upto page granuality for now. |
| 886 | */ |
| 887 | static int mce_usable_address(struct mce *m) |
| 888 | { |
| 889 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) |
| 890 | return 0; |
| 891 | if ((m->misc & 0x3f) > PAGE_SHIFT) |
| 892 | return 0; |
| 893 | if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS) |
| 894 | return 0; |
| 895 | return 1; |
| 896 | } |
| 897 | |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 898 | static void mce_clear_state(unsigned long *toclear) |
| 899 | { |
| 900 | int i; |
| 901 | |
| 902 | for (i = 0; i < banks; i++) { |
| 903 | if (test_bit(i, toclear)) |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 904 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 905 | } |
| 906 | } |
| 907 | |
| 908 | /* |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 909 | * The actual machine check handler. This only handles real |
| 910 | * exceptions when something got corrupted coming in through int 18. |
| 911 | * |
| 912 | * This is executed in NMI context not subject to normal locking rules. This |
| 913 | * implies that most kernel services cannot be safely used. Don't even |
| 914 | * think about putting a printk in there! |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 915 | * |
| 916 | * On Intel systems this is entered on all CPUs in parallel through |
| 917 | * MCE broadcast. However some CPUs might be broken beyond repair, |
| 918 | * so be always careful when synchronizing with others. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 919 | */ |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 920 | void do_machine_check(struct pt_regs *regs, long error_code) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 921 | { |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 922 | struct mce m, *final; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 923 | int i; |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 924 | int worst = 0; |
| 925 | int severity; |
| 926 | /* |
| 927 | * Establish sequential order between the CPUs entering the machine |
| 928 | * check handler. |
| 929 | */ |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 930 | int order; |
Tim Hockin | bd78432 | 2007-07-21 17:10:37 +0200 | [diff] [blame] | 931 | /* |
| 932 | * If no_way_out gets set, there is no safe way to recover from this |
| 933 | * MCE. If tolerant is cranked up, we'll try anyway. |
| 934 | */ |
| 935 | int no_way_out = 0; |
| 936 | /* |
| 937 | * If kill_it gets set, there might be a way to recover from this |
| 938 | * error. |
| 939 | */ |
| 940 | int kill_it = 0; |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 941 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
Andi Kleen | bd19a5e | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 942 | char *msg = "Unknown"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 943 | |
Andi Kleen | 553f265 | 2006-04-07 19:49:57 +0200 | [diff] [blame] | 944 | atomic_inc(&mce_entry); |
| 945 | |
Andi Kleen | 01ca79f | 2009-05-27 21:56:52 +0200 | [diff] [blame] | 946 | __get_cpu_var(mce_exception_count)++; |
| 947 | |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 948 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
Jan Beulich | 22f5991 | 2008-01-30 13:31:23 +0100 | [diff] [blame] | 949 | 18, SIGKILL) == NOTIFY_STOP) |
Andi Kleen | 3256169 | 2009-05-27 21:56:53 +0200 | [diff] [blame] | 950 | goto out; |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 951 | if (!banks) |
Andi Kleen | 3256169 | 2009-05-27 21:56:53 +0200 | [diff] [blame] | 952 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 953 | |
Andi Kleen | b5f2fa4 | 2009-02-12 13:43:22 +0100 | [diff] [blame] | 954 | mce_setup(&m); |
| 955 | |
Andi Kleen | 5f8c1a5 | 2009-04-29 19:29:12 +0200 | [diff] [blame] | 956 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 957 | final = &__get_cpu_var(mces_seen); |
| 958 | *final = m; |
| 959 | |
Hidetoshi Seto | 680b6cf | 2009-08-26 16:20:36 +0900 | [diff] [blame] | 960 | no_way_out = mce_no_way_out(&m, &msg); |
| 961 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 962 | barrier(); |
| 963 | |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 964 | /* |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 965 | * When no restart IP must always kill or panic. |
| 966 | */ |
| 967 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) |
| 968 | kill_it = 1; |
| 969 | |
| 970 | /* |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 971 | * Go through all the banks in exclusion of the other CPUs. |
| 972 | * This way we don't report duplicated events on shared banks |
| 973 | * because the first one to see it will clear it. |
| 974 | */ |
Hidetoshi Seto | 7fb06fc | 2009-06-15 18:18:43 +0900 | [diff] [blame] | 975 | order = mce_start(&no_way_out); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 976 | for (i = 0; i < banks; i++) { |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 977 | __clear_bit(i, toclear); |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 978 | if (!mce_banks[i].ctl) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 979 | continue; |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 980 | |
| 981 | m.misc = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 982 | m.addr = 0; |
| 983 | m.bank = i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 984 | |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 985 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 986 | if ((m.status & MCI_STATUS_VAL) == 0) |
| 987 | continue; |
| 988 | |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 989 | /* |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 990 | * Non uncorrected or non signaled errors are handled by |
| 991 | * machine_check_poll. Leave them alone, unless this panics. |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 992 | */ |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 993 | if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
| 994 | !no_way_out) |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 995 | continue; |
| 996 | |
| 997 | /* |
| 998 | * Set taint even when machine check was not enabled. |
| 999 | */ |
| 1000 | add_taint(TAINT_MACHINE_CHECK); |
| 1001 | |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 1002 | severity = mce_severity(&m, tolerant, NULL); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 1003 | |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 1004 | /* |
| 1005 | * When machine check was for corrected handler don't touch, |
| 1006 | * unless we're panicing. |
| 1007 | */ |
| 1008 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) |
| 1009 | continue; |
| 1010 | __set_bit(i, toclear); |
| 1011 | if (severity == MCE_NO_SEVERITY) { |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 1012 | /* |
| 1013 | * Machine check event was not enabled. Clear, but |
| 1014 | * ignore. |
| 1015 | */ |
| 1016 | continue; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1017 | } |
| 1018 | |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 1019 | /* |
| 1020 | * Kill on action required. |
| 1021 | */ |
| 1022 | if (severity == MCE_AR_SEVERITY) |
| 1023 | kill_it = 1; |
| 1024 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1025 | if (m.status & MCI_STATUS_MISCV) |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 1026 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1027 | if (m.status & MCI_STATUS_ADDRV) |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 1028 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1029 | |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 1030 | /* |
| 1031 | * Action optional error. Queue address for later processing. |
| 1032 | * When the ring overflows we just ignore the AO error. |
| 1033 | * RED-PEN add some logging mechanism when |
| 1034 | * usable_address or mce_add_ring fails. |
| 1035 | * RED-PEN don't ignore overflow for tolerant == 0 |
| 1036 | */ |
| 1037 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) |
| 1038 | mce_ring_add(m.addr >> PAGE_SHIFT); |
| 1039 | |
Andi Kleen | 94ad847 | 2005-04-16 15:25:09 -0700 | [diff] [blame] | 1040 | mce_get_rip(&m, regs); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 1041 | mce_log(&m); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1042 | |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1043 | if (severity > worst) { |
| 1044 | *final = m; |
| 1045 | worst = severity; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1046 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1047 | } |
| 1048 | |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1049 | if (!no_way_out) |
| 1050 | mce_clear_state(toclear); |
| 1051 | |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1052 | /* |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1053 | * Do most of the synchronization with other CPUs. |
| 1054 | * When there's any problem use only local no_way_out state. |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1055 | */ |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1056 | if (mce_end(order) < 0) |
| 1057 | no_way_out = worst >= MCE_PANIC_SEVERITY; |
Tim Hockin | bd78432 | 2007-07-21 17:10:37 +0200 | [diff] [blame] | 1058 | |
| 1059 | /* |
| 1060 | * If we have decided that we just CAN'T continue, and the user |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1061 | * has not set tolerant to an insane level, give up and die. |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1062 | * |
| 1063 | * This is mainly used in the case when the system doesn't |
| 1064 | * support MCE broadcasting or it has been disabled. |
Tim Hockin | bd78432 | 2007-07-21 17:10:37 +0200 | [diff] [blame] | 1065 | */ |
| 1066 | if (no_way_out && tolerant < 3) |
Andi Kleen | ac96037 | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 1067 | mce_panic("Fatal machine check on current CPU", final, msg); |
Tim Hockin | bd78432 | 2007-07-21 17:10:37 +0200 | [diff] [blame] | 1068 | |
| 1069 | /* |
| 1070 | * If the error seems to be unrecoverable, something should be |
| 1071 | * done. Try to kill as little as possible. If we can kill just |
| 1072 | * one task, do that. If the user has set the tolerance very |
| 1073 | * high, don't try to do anything at all. |
| 1074 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1075 | |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 1076 | if (kill_it && tolerant < 3) |
| 1077 | force_sig(SIGBUS, current); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1078 | |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1079 | /* notify userspace ASAP */ |
| 1080 | set_thread_flag(TIF_MCE_NOTIFY); |
| 1081 | |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1082 | if (worst > 0) |
| 1083 | mce_report_event(regs); |
Andi Kleen | 5f8c1a5 | 2009-04-29 19:29:12 +0200 | [diff] [blame] | 1084 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
Andi Kleen | 3256169 | 2009-05-27 21:56:53 +0200 | [diff] [blame] | 1085 | out: |
Andi Kleen | 553f265 | 2006-04-07 19:49:57 +0200 | [diff] [blame] | 1086 | atomic_dec(&mce_entry); |
Andi Kleen | 88921be | 2009-05-27 21:56:51 +0200 | [diff] [blame] | 1087 | sync_core(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1088 | } |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 1089 | EXPORT_SYMBOL_GPL(do_machine_check); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1090 | |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 1091 | /* dummy to break dependency. actual code is in mm/memory-failure.c */ |
| 1092 | void __attribute__((weak)) memory_failure(unsigned long pfn, int vector) |
| 1093 | { |
| 1094 | printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn); |
| 1095 | } |
| 1096 | |
| 1097 | /* |
| 1098 | * Called after mce notification in process context. This code |
| 1099 | * is allowed to sleep. Call the high level VM handler to process |
| 1100 | * any corrupted pages. |
| 1101 | * Assume that the work queue code only calls this one at a time |
| 1102 | * per CPU. |
| 1103 | * Note we don't disable preemption, so this code might run on the wrong |
| 1104 | * CPU. In this case the event is picked up by the scheduled work queue. |
| 1105 | * This is merely a fast path to expedite processing in some common |
| 1106 | * cases. |
| 1107 | */ |
| 1108 | void mce_notify_process(void) |
| 1109 | { |
| 1110 | unsigned long pfn; |
| 1111 | mce_notify_irq(); |
| 1112 | while (mce_ring_get(&pfn)) |
| 1113 | memory_failure(pfn, MCE_VECTOR); |
| 1114 | } |
| 1115 | |
| 1116 | static void mce_process_work(struct work_struct *dummy) |
| 1117 | { |
| 1118 | mce_notify_process(); |
| 1119 | } |
| 1120 | |
Dmitriy Zavin | 15d5f83 | 2006-09-26 10:52:42 +0200 | [diff] [blame] | 1121 | #ifdef CONFIG_X86_MCE_INTEL |
| 1122 | /*** |
| 1123 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog |
Simon Arlott | 676b185 | 2007-10-20 01:25:36 +0200 | [diff] [blame] | 1124 | * @cpu: The CPU on which the event occurred. |
Dmitriy Zavin | 15d5f83 | 2006-09-26 10:52:42 +0200 | [diff] [blame] | 1125 | * @status: Event status information |
| 1126 | * |
| 1127 | * This function should be called by the thermal interrupt after the |
| 1128 | * event has been processed and the decision was made to log the event |
| 1129 | * further. |
| 1130 | * |
| 1131 | * The status parameter will be saved to the 'status' field of 'struct mce' |
| 1132 | * and historically has been the register value of the |
| 1133 | * MSR_IA32_THERMAL_STATUS (Intel) msr. |
| 1134 | */ |
Andi Kleen | b5f2fa4 | 2009-02-12 13:43:22 +0100 | [diff] [blame] | 1135 | void mce_log_therm_throt_event(__u64 status) |
Dmitriy Zavin | 15d5f83 | 2006-09-26 10:52:42 +0200 | [diff] [blame] | 1136 | { |
| 1137 | struct mce m; |
| 1138 | |
Andi Kleen | b5f2fa4 | 2009-02-12 13:43:22 +0100 | [diff] [blame] | 1139 | mce_setup(&m); |
Dmitriy Zavin | 15d5f83 | 2006-09-26 10:52:42 +0200 | [diff] [blame] | 1140 | m.bank = MCE_THERMAL_BANK; |
| 1141 | m.status = status; |
Dmitriy Zavin | 15d5f83 | 2006-09-26 10:52:42 +0200 | [diff] [blame] | 1142 | mce_log(&m); |
| 1143 | } |
| 1144 | #endif /* CONFIG_X86_MCE_INTEL */ |
| 1145 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1146 | /* |
Tim Hockin | 8a336b0 | 2007-05-02 19:27:19 +0200 | [diff] [blame] | 1147 | * Periodic polling timer for "silent" machine check errors. If the |
| 1148 | * poller finds an MCE, poll 2x faster. When the poller finds no more |
| 1149 | * errors, poll 2x slower (up to check_interval seconds). |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1150 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1151 | static int check_interval = 5 * 60; /* 5 minutes */ |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1152 | |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1153 | static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */ |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1154 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1155 | |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 1156 | static void mce_start_timer(unsigned long data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1157 | { |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1158 | struct timer_list *t = &per_cpu(mce_timer, data); |
Andi Kleen | 6298c51 | 2009-04-09 12:28:22 +0200 | [diff] [blame] | 1159 | int *n; |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1160 | |
| 1161 | WARN_ON(smp_processor_id() != data); |
| 1162 | |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1163 | if (mce_available(¤t_cpu_data)) { |
Andi Kleen | ee031c3 | 2009-02-12 13:49:34 +0100 | [diff] [blame] | 1164 | machine_check_poll(MCP_TIMESTAMP, |
| 1165 | &__get_cpu_var(mce_poll_banks)); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1166 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1167 | |
| 1168 | /* |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1169 | * Alert userspace if needed. If we logged an MCE, reduce the |
| 1170 | * polling interval, otherwise increase the polling interval. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1171 | */ |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1172 | n = &__get_cpu_var(mce_next_interval); |
Andi Kleen | 9ff36ee | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 1173 | if (mce_notify_irq()) |
Andi Kleen | 6298c51 | 2009-04-09 12:28:22 +0200 | [diff] [blame] | 1174 | *n = max(*n/2, HZ/100); |
Hidetoshi Seto | 14a0253 | 2009-04-30 16:04:51 +0900 | [diff] [blame] | 1175 | else |
Andi Kleen | 6298c51 | 2009-04-09 12:28:22 +0200 | [diff] [blame] | 1176 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
Tim Hockin | 8a336b0 | 2007-05-02 19:27:19 +0200 | [diff] [blame] | 1177 | |
Andi Kleen | 6298c51 | 2009-04-09 12:28:22 +0200 | [diff] [blame] | 1178 | t->expires = jiffies + *n; |
Hidetoshi Seto | 5be6066 | 2009-06-24 09:21:10 +0900 | [diff] [blame] | 1179 | add_timer_on(t, smp_processor_id()); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1180 | } |
| 1181 | |
Andi Kleen | 9bd9840 | 2009-02-12 13:39:28 +0100 | [diff] [blame] | 1182 | static void mce_do_trigger(struct work_struct *work) |
| 1183 | { |
Hidetoshi Seto | 1020bcb | 2009-06-15 17:20:57 +0900 | [diff] [blame] | 1184 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
Andi Kleen | 9bd9840 | 2009-02-12 13:39:28 +0100 | [diff] [blame] | 1185 | } |
| 1186 | |
| 1187 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); |
| 1188 | |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1189 | /* |
Andi Kleen | 9bd9840 | 2009-02-12 13:39:28 +0100 | [diff] [blame] | 1190 | * Notify the user(s) about new machine check events. |
| 1191 | * Can be called from interrupt context, but not from machine check/NMI |
| 1192 | * context. |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1193 | */ |
Andi Kleen | 9ff36ee | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 1194 | int mce_notify_irq(void) |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1195 | { |
Andi Kleen | 8457c84 | 2009-02-12 13:49:33 +0100 | [diff] [blame] | 1196 | /* Not more than two messages every minute */ |
| 1197 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); |
| 1198 | |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1199 | clear_thread_flag(TIF_MCE_NOTIFY); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1200 | |
Hidetoshi Seto | 1020bcb | 2009-06-15 17:20:57 +0900 | [diff] [blame] | 1201 | if (test_and_clear_bit(0, &mce_need_notify)) { |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1202 | wake_up_interruptible(&mce_wait); |
Andi Kleen | 9bd9840 | 2009-02-12 13:39:28 +0100 | [diff] [blame] | 1203 | |
| 1204 | /* |
| 1205 | * There is no risk of missing notifications because |
| 1206 | * work_pending is always cleared before the function is |
| 1207 | * executed. |
| 1208 | */ |
Hidetoshi Seto | 1020bcb | 2009-06-15 17:20:57 +0900 | [diff] [blame] | 1209 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
Andi Kleen | 9bd9840 | 2009-02-12 13:39:28 +0100 | [diff] [blame] | 1210 | schedule_work(&mce_trigger_work); |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1211 | |
Andi Kleen | 8457c84 | 2009-02-12 13:49:33 +0100 | [diff] [blame] | 1212 | if (__ratelimit(&ratelimit)) |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1213 | printk(KERN_INFO "Machine check events logged\n"); |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1214 | |
| 1215 | return 1; |
| 1216 | } |
| 1217 | return 0; |
| 1218 | } |
Andi Kleen | 9ff36ee | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 1219 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1220 | |
Hidetoshi Seto | cffd377 | 2009-11-12 15:52:40 +0900 | [diff] [blame] | 1221 | static int __cpuinit __mcheck_cpu_mce_banks_init(void) |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1222 | { |
| 1223 | int i; |
| 1224 | |
| 1225 | mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL); |
| 1226 | if (!mce_banks) |
| 1227 | return -ENOMEM; |
| 1228 | for (i = 0; i < banks; i++) { |
| 1229 | struct mce_bank *b = &mce_banks[i]; |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 1230 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1231 | b->ctl = -1ULL; |
| 1232 | b->init = 1; |
| 1233 | } |
| 1234 | return 0; |
| 1235 | } |
| 1236 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1237 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1238 | * Initialize Machine Checks for a CPU. |
| 1239 | */ |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 1240 | static int __cpuinit __mcheck_cpu_cap_init(void) |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1241 | { |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1242 | unsigned b; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1243 | u64 cap; |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1244 | |
| 1245 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
Thomas Gleixner | 01c6680 | 2009-04-08 12:31:24 +0200 | [diff] [blame] | 1246 | |
| 1247 | b = cap & MCG_BANKCNT_MASK; |
Roland Dreier | 93ae501 | 2009-10-15 14:21:14 -0700 | [diff] [blame] | 1248 | if (!banks) |
| 1249 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); |
Ingo Molnar | b659294 | 2009-04-08 12:31:27 +0200 | [diff] [blame] | 1250 | |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1251 | if (b > MAX_NR_BANKS) { |
| 1252 | printk(KERN_WARNING |
| 1253 | "MCE: Using only %u machine check banks out of %u\n", |
| 1254 | MAX_NR_BANKS, b); |
| 1255 | b = MAX_NR_BANKS; |
| 1256 | } |
| 1257 | |
| 1258 | /* Don't support asymmetric configurations today */ |
| 1259 | WARN_ON(banks != 0 && b != banks); |
| 1260 | banks = b; |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1261 | if (!mce_banks) { |
Hidetoshi Seto | cffd377 | 2009-11-12 15:52:40 +0900 | [diff] [blame] | 1262 | int err = __mcheck_cpu_mce_banks_init(); |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 1263 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1264 | if (err) |
| 1265 | return err; |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1266 | } |
| 1267 | |
| 1268 | /* Use accurate RIP reporting if available. */ |
Thomas Gleixner | 01c6680 | 2009-04-08 12:31:24 +0200 | [diff] [blame] | 1269 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1270 | rip_msr = MSR_IA32_MCG_EIP; |
| 1271 | |
Andi Kleen | ed7290d | 2009-05-27 21:56:57 +0200 | [diff] [blame] | 1272 | if (cap & MCG_SER_P) |
| 1273 | mce_ser = 1; |
| 1274 | |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1275 | return 0; |
| 1276 | } |
| 1277 | |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 1278 | static void __mcheck_cpu_init_generic(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1279 | { |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1280 | mce_banks_t all_banks; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1281 | u64 cap; |
| 1282 | int i; |
| 1283 | |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 1284 | /* |
| 1285 | * Log the machine checks left over from the previous reset. |
| 1286 | */ |
Andi Kleen | ee031c3 | 2009-02-12 13:49:34 +0100 | [diff] [blame] | 1287 | bitmap_fill(all_banks, MAX_NR_BANKS); |
Andi Kleen | 5679af4 | 2009-04-07 17:06:55 +0200 | [diff] [blame] | 1288 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1289 | |
| 1290 | set_in_cr4(X86_CR4_MCE); |
| 1291 | |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1292 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1293 | if (cap & MCG_CTL_P) |
| 1294 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); |
| 1295 | |
| 1296 | for (i = 0; i < banks; i++) { |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1297 | struct mce_bank *b = &mce_banks[i]; |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 1298 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1299 | if (!b->init) |
Andi Kleen | 06b7a7a | 2009-04-27 18:37:43 +0200 | [diff] [blame] | 1300 | continue; |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 1301 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
| 1302 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1303 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1304 | } |
| 1305 | |
| 1306 | /* Add per CPU specific workarounds here */ |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 1307 | static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1308 | { |
Ingo Molnar | e412cd2 | 2009-08-17 10:19:00 +0200 | [diff] [blame] | 1309 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
| 1310 | pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); |
| 1311 | return -EOPNOTSUPP; |
| 1312 | } |
| 1313 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1314 | /* This should be disabled by the BIOS, but isn't always */ |
Jan Beulich | 911f6a7 | 2008-04-22 16:22:21 +0100 | [diff] [blame] | 1315 | if (c->x86_vendor == X86_VENDOR_AMD) { |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1316 | if (c->x86 == 15 && banks > 4) { |
| 1317 | /* |
| 1318 | * disable GART TBL walk error reporting, which |
| 1319 | * trips off incorrectly with the IOMMU & 3ware |
| 1320 | * & Cerberus: |
| 1321 | */ |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1322 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1323 | } |
| 1324 | if (c->x86 <= 17 && mce_bootlog < 0) { |
| 1325 | /* |
| 1326 | * Lots of broken BIOS around that don't clear them |
| 1327 | * by default and leave crap in there. Don't log: |
| 1328 | */ |
Jan Beulich | 911f6a7 | 2008-04-22 16:22:21 +0100 | [diff] [blame] | 1329 | mce_bootlog = 0; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1330 | } |
Andi Kleen | 2e6f694 | 2009-04-27 18:42:48 +0200 | [diff] [blame] | 1331 | /* |
| 1332 | * Various K7s with broken bank 0 around. Always disable |
| 1333 | * by default. |
| 1334 | */ |
Andi Kleen | 203abd6 | 2009-06-15 14:52:01 +0200 | [diff] [blame] | 1335 | if (c->x86 == 6 && banks > 0) |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1336 | mce_banks[0].ctl = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1337 | } |
Andi Kleen | e583538 | 2005-11-05 17:25:54 +0100 | [diff] [blame] | 1338 | |
Andi Kleen | 06b7a7a | 2009-04-27 18:37:43 +0200 | [diff] [blame] | 1339 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
| 1340 | /* |
| 1341 | * SDM documents that on family 6 bank 0 should not be written |
| 1342 | * because it aliases to another special BIOS controlled |
| 1343 | * register. |
| 1344 | * But it's not aliased anymore on model 0x1a+ |
| 1345 | * Don't ignore bank 0 completely because there could be a |
| 1346 | * valid event later, merely don't write CTL0. |
| 1347 | */ |
| 1348 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1349 | if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0) |
| 1350 | mce_banks[0].init = 0; |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1351 | |
| 1352 | /* |
| 1353 | * All newer Intel systems support MCE broadcasting. Enable |
| 1354 | * synchronization with a one second timeout. |
| 1355 | */ |
| 1356 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && |
| 1357 | monarch_timeout < 0) |
| 1358 | monarch_timeout = USEC_PER_SEC; |
Bartlomiej Zolnierkiewicz | c7f6fa4 | 2009-07-28 23:52:54 +0200 | [diff] [blame] | 1359 | |
Ingo Molnar | e412cd2 | 2009-08-17 10:19:00 +0200 | [diff] [blame] | 1360 | /* |
| 1361 | * There are also broken BIOSes on some Pentium M and |
| 1362 | * earlier systems: |
| 1363 | */ |
| 1364 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) |
Bartlomiej Zolnierkiewicz | c7f6fa4 | 2009-07-28 23:52:54 +0200 | [diff] [blame] | 1365 | mce_bootlog = 0; |
Andi Kleen | 06b7a7a | 2009-04-27 18:37:43 +0200 | [diff] [blame] | 1366 | } |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1367 | if (monarch_timeout < 0) |
| 1368 | monarch_timeout = 0; |
Andi Kleen | 29b0f59 | 2009-05-27 21:56:56 +0200 | [diff] [blame] | 1369 | if (mce_bootlog != 0) |
| 1370 | mce_panic_timeout = 30; |
Ingo Molnar | e412cd2 | 2009-08-17 10:19:00 +0200 | [diff] [blame] | 1371 | |
| 1372 | return 0; |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1373 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1374 | |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 1375 | static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 1376 | { |
| 1377 | if (c->x86 != 5) |
| 1378 | return; |
| 1379 | switch (c->x86_vendor) { |
| 1380 | case X86_VENDOR_INTEL: |
Hidetoshi Seto | c697836 | 2009-06-15 17:22:49 +0900 | [diff] [blame] | 1381 | intel_p5_mcheck_init(c); |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 1382 | break; |
| 1383 | case X86_VENDOR_CENTAUR: |
| 1384 | winchip_mcheck_init(c); |
| 1385 | break; |
| 1386 | } |
| 1387 | } |
| 1388 | |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 1389 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1390 | { |
| 1391 | switch (c->x86_vendor) { |
| 1392 | case X86_VENDOR_INTEL: |
| 1393 | mce_intel_feature_init(c); |
| 1394 | break; |
Jacob Shin | 89b831e | 2005-11-05 17:25:53 +0100 | [diff] [blame] | 1395 | case X86_VENDOR_AMD: |
| 1396 | mce_amd_feature_init(c); |
| 1397 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1398 | default: |
| 1399 | break; |
| 1400 | } |
| 1401 | } |
| 1402 | |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 1403 | static void __mcheck_cpu_init_timer(void) |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1404 | { |
| 1405 | struct timer_list *t = &__get_cpu_var(mce_timer); |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1406 | int *n = &__get_cpu_var(mce_next_interval); |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1407 | |
Jan Beulich | bc09eff | 2009-12-08 11:21:37 +0900 | [diff] [blame] | 1408 | setup_timer(t, mce_start_timer, smp_processor_id()); |
| 1409 | |
Hidetoshi Seto | 62fdac5 | 2009-06-11 16:06:07 +0900 | [diff] [blame] | 1410 | if (mce_ignore_ce) |
| 1411 | return; |
| 1412 | |
Andi Kleen | 6298c51 | 2009-04-09 12:28:22 +0200 | [diff] [blame] | 1413 | *n = check_interval * HZ; |
| 1414 | if (!*n) |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1415 | return; |
Andi Kleen | 6298c51 | 2009-04-09 12:28:22 +0200 | [diff] [blame] | 1416 | t->expires = round_jiffies(jiffies + *n); |
Hidetoshi Seto | 5be6066 | 2009-06-24 09:21:10 +0900 | [diff] [blame] | 1417 | add_timer_on(t, smp_processor_id()); |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1418 | } |
| 1419 | |
Andi Kleen | 9eda8cb | 2009-07-09 00:31:42 +0200 | [diff] [blame] | 1420 | /* Handle unconfigured int18 (should never happen) */ |
| 1421 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) |
| 1422 | { |
| 1423 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", |
| 1424 | smp_processor_id()); |
| 1425 | } |
| 1426 | |
| 1427 | /* Call the installed machine check handler for this CPU setup. */ |
| 1428 | void (*machine_check_vector)(struct pt_regs *, long error_code) = |
| 1429 | unexpected_machine_check; |
| 1430 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1431 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1432 | * Called for each booted CPU to set up machine checks. |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1433 | * Must be called with preempt off: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1434 | */ |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 1435 | void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1436 | { |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 1437 | if (mce_disabled) |
| 1438 | return; |
| 1439 | |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 1440 | __mcheck_cpu_ancient_init(c); |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 1441 | |
Andi Kleen | 5b4408f | 2009-02-12 13:39:30 +0100 | [diff] [blame] | 1442 | if (!mce_available(c)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1443 | return; |
| 1444 | |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 1445 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
Andi Kleen | 04b2b1a | 2009-04-28 22:50:19 +0200 | [diff] [blame] | 1446 | mce_disabled = 1; |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1447 | return; |
| 1448 | } |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1449 | |
Andi Kleen | 5d72792 | 2009-04-27 19:25:48 +0200 | [diff] [blame] | 1450 | machine_check_vector = do_machine_check; |
| 1451 | |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 1452 | __mcheck_cpu_init_generic(); |
| 1453 | __mcheck_cpu_init_vendor(c); |
| 1454 | __mcheck_cpu_init_timer(); |
Andi Kleen | 9b1beaf | 2009-05-27 21:56:59 +0200 | [diff] [blame] | 1455 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
Borislav Petkov | fb25319 | 2009-10-07 13:20:38 +0200 | [diff] [blame] | 1456 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1457 | } |
| 1458 | |
| 1459 | /* |
| 1460 | * Character device to read and clear the MCE log. |
| 1461 | */ |
| 1462 | |
Tim Hockin | f528e7b | 2007-07-21 17:10:35 +0200 | [diff] [blame] | 1463 | static DEFINE_SPINLOCK(mce_state_lock); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1464 | static int open_count; /* #times opened */ |
| 1465 | static int open_exclu; /* already open exclusive? */ |
Tim Hockin | f528e7b | 2007-07-21 17:10:35 +0200 | [diff] [blame] | 1466 | |
| 1467 | static int mce_open(struct inode *inode, struct file *file) |
| 1468 | { |
| 1469 | spin_lock(&mce_state_lock); |
| 1470 | |
| 1471 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { |
| 1472 | spin_unlock(&mce_state_lock); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1473 | |
Tim Hockin | f528e7b | 2007-07-21 17:10:35 +0200 | [diff] [blame] | 1474 | return -EBUSY; |
| 1475 | } |
| 1476 | |
| 1477 | if (file->f_flags & O_EXCL) |
| 1478 | open_exclu = 1; |
| 1479 | open_count++; |
| 1480 | |
| 1481 | spin_unlock(&mce_state_lock); |
| 1482 | |
Tim Hockin | bd78432 | 2007-07-21 17:10:37 +0200 | [diff] [blame] | 1483 | return nonseekable_open(inode, file); |
Tim Hockin | f528e7b | 2007-07-21 17:10:35 +0200 | [diff] [blame] | 1484 | } |
| 1485 | |
| 1486 | static int mce_release(struct inode *inode, struct file *file) |
| 1487 | { |
| 1488 | spin_lock(&mce_state_lock); |
| 1489 | |
| 1490 | open_count--; |
| 1491 | open_exclu = 0; |
| 1492 | |
| 1493 | spin_unlock(&mce_state_lock); |
| 1494 | |
| 1495 | return 0; |
| 1496 | } |
| 1497 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1498 | static void collect_tscs(void *data) |
| 1499 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1500 | unsigned long *cpu_tsc = (unsigned long *)data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1501 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1502 | rdtscll(cpu_tsc[smp_processor_id()]); |
| 1503 | } |
| 1504 | |
Huang Ying | 482908b | 2010-05-18 14:35:22 +0800 | [diff] [blame^] | 1505 | static int mce_apei_read_done; |
| 1506 | |
| 1507 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ |
| 1508 | static int __mce_read_apei(char __user **ubuf, size_t usize) |
| 1509 | { |
| 1510 | int rc; |
| 1511 | u64 record_id; |
| 1512 | struct mce m; |
| 1513 | |
| 1514 | if (usize < sizeof(struct mce)) |
| 1515 | return -EINVAL; |
| 1516 | |
| 1517 | rc = apei_read_mce(&m, &record_id); |
| 1518 | /* Error or no more MCE record */ |
| 1519 | if (rc <= 0) { |
| 1520 | mce_apei_read_done = 1; |
| 1521 | return rc; |
| 1522 | } |
| 1523 | rc = -EFAULT; |
| 1524 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) |
| 1525 | return rc; |
| 1526 | /* |
| 1527 | * In fact, we should have cleared the record after that has |
| 1528 | * been flushed to the disk or sent to network in |
| 1529 | * /sbin/mcelog, but we have no interface to support that now, |
| 1530 | * so just clear it to avoid duplication. |
| 1531 | */ |
| 1532 | rc = apei_clear_mce(record_id); |
| 1533 | if (rc) { |
| 1534 | mce_apei_read_done = 1; |
| 1535 | return rc; |
| 1536 | } |
| 1537 | *ubuf += sizeof(struct mce); |
| 1538 | |
| 1539 | return 0; |
| 1540 | } |
| 1541 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1542 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
| 1543 | loff_t *off) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1544 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1545 | char __user *buf = ubuf; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1546 | unsigned long *cpu_tsc; |
| 1547 | unsigned prev, next; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1548 | int i, err; |
| 1549 | |
Mike Travis | 6bca67f | 2008-07-18 18:11:27 -0700 | [diff] [blame] | 1550 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
Andi Kleen | f0de53b | 2005-04-16 15:25:10 -0700 | [diff] [blame] | 1551 | if (!cpu_tsc) |
| 1552 | return -ENOMEM; |
| 1553 | |
Daniel Walker | 8c8b885 | 2008-01-30 13:31:17 +0100 | [diff] [blame] | 1554 | mutex_lock(&mce_read_mutex); |
Huang Ying | 482908b | 2010-05-18 14:35:22 +0800 | [diff] [blame^] | 1555 | |
| 1556 | if (!mce_apei_read_done) { |
| 1557 | err = __mce_read_apei(&buf, usize); |
| 1558 | if (err || buf != ubuf) |
| 1559 | goto out; |
| 1560 | } |
| 1561 | |
Paul E. McKenney | f56e8a0 | 2010-03-05 15:03:27 -0800 | [diff] [blame] | 1562 | next = rcu_dereference_check_mce(mcelog.next); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1563 | |
| 1564 | /* Only supports full reads right now */ |
Huang Ying | 482908b | 2010-05-18 14:35:22 +0800 | [diff] [blame^] | 1565 | err = -EINVAL; |
| 1566 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) |
| 1567 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1568 | |
| 1569 | err = 0; |
Huang Ying | ef41df434 | 2009-02-12 13:39:34 +0100 | [diff] [blame] | 1570 | prev = 0; |
| 1571 | do { |
| 1572 | for (i = prev; i < next; i++) { |
| 1573 | unsigned long start = jiffies; |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1574 | |
Huang Ying | ef41df434 | 2009-02-12 13:39:34 +0100 | [diff] [blame] | 1575 | while (!mcelog.entry[i].finished) { |
| 1576 | if (time_after_eq(jiffies, start + 2)) { |
| 1577 | memset(mcelog.entry + i, 0, |
| 1578 | sizeof(struct mce)); |
| 1579 | goto timeout; |
| 1580 | } |
| 1581 | cpu_relax(); |
Andi Kleen | 673242c | 2005-09-12 18:49:24 +0200 | [diff] [blame] | 1582 | } |
Huang Ying | ef41df434 | 2009-02-12 13:39:34 +0100 | [diff] [blame] | 1583 | smp_rmb(); |
| 1584 | err |= copy_to_user(buf, mcelog.entry + i, |
| 1585 | sizeof(struct mce)); |
| 1586 | buf += sizeof(struct mce); |
| 1587 | timeout: |
| 1588 | ; |
Andi Kleen | 673242c | 2005-09-12 18:49:24 +0200 | [diff] [blame] | 1589 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1590 | |
Huang Ying | ef41df434 | 2009-02-12 13:39:34 +0100 | [diff] [blame] | 1591 | memset(mcelog.entry + prev, 0, |
| 1592 | (next - prev) * sizeof(struct mce)); |
| 1593 | prev = next; |
| 1594 | next = cmpxchg(&mcelog.next, prev, 0); |
| 1595 | } while (next != prev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1596 | |
Paul E. McKenney | b2b1866 | 2005-06-25 14:55:38 -0700 | [diff] [blame] | 1597 | synchronize_sched(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1598 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1599 | /* |
| 1600 | * Collect entries that were still getting written before the |
| 1601 | * synchronize. |
| 1602 | */ |
Jens Axboe | 15c8b6c | 2008-05-09 09:39:44 +0200 | [diff] [blame] | 1603 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1604 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1605 | for (i = next; i < MCE_LOG_LEN; i++) { |
| 1606 | if (mcelog.entry[i].finished && |
| 1607 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { |
| 1608 | err |= copy_to_user(buf, mcelog.entry+i, |
| 1609 | sizeof(struct mce)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1610 | smp_rmb(); |
| 1611 | buf += sizeof(struct mce); |
| 1612 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); |
| 1613 | } |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1614 | } |
Huang Ying | 482908b | 2010-05-18 14:35:22 +0800 | [diff] [blame^] | 1615 | |
| 1616 | if (err) |
| 1617 | err = -EFAULT; |
| 1618 | |
| 1619 | out: |
Daniel Walker | 8c8b885 | 2008-01-30 13:31:17 +0100 | [diff] [blame] | 1620 | mutex_unlock(&mce_read_mutex); |
Andi Kleen | f0de53b | 2005-04-16 15:25:10 -0700 | [diff] [blame] | 1621 | kfree(cpu_tsc); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1622 | |
Huang Ying | 482908b | 2010-05-18 14:35:22 +0800 | [diff] [blame^] | 1623 | return err ? err : buf - ubuf; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1624 | } |
| 1625 | |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1626 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
| 1627 | { |
| 1628 | poll_wait(file, &mce_wait, wait); |
Paul E. McKenney | f56e8a0 | 2010-03-05 15:03:27 -0800 | [diff] [blame] | 1629 | if (rcu_dereference_check_mce(mcelog.next)) |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1630 | return POLLIN | POLLRDNORM; |
Huang Ying | 482908b | 2010-05-18 14:35:22 +0800 | [diff] [blame^] | 1631 | if (!mce_apei_read_done && apei_check_mce()) |
| 1632 | return POLLIN | POLLRDNORM; |
Tim Hockin | e02e68d | 2007-07-21 17:10:36 +0200 | [diff] [blame] | 1633 | return 0; |
| 1634 | } |
| 1635 | |
Nikanth Karthikesan | c68461b | 2008-01-30 13:32:59 +0100 | [diff] [blame] | 1636 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1637 | { |
| 1638 | int __user *p = (int __user *)arg; |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1639 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1640 | if (!capable(CAP_SYS_ADMIN)) |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1641 | return -EPERM; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1642 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1643 | switch (cmd) { |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1644 | case MCE_GET_RECORD_LEN: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1645 | return put_user(sizeof(struct mce), p); |
| 1646 | case MCE_GET_LOG_LEN: |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1647 | return put_user(MCE_LOG_LEN, p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1648 | case MCE_GETCLEAR_FLAGS: { |
| 1649 | unsigned flags; |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1650 | |
| 1651 | do { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1652 | flags = mcelog.flags; |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1653 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1654 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1655 | return put_user(flags, p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1656 | } |
| 1657 | default: |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1658 | return -ENOTTY; |
| 1659 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1660 | } |
| 1661 | |
H. Peter Anvin | a1ff41b | 2009-05-25 22:16:14 -0700 | [diff] [blame] | 1662 | /* Modified in mce-inject.c, so not static or const */ |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 1663 | struct file_operations mce_chrdev_ops = { |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1664 | .open = mce_open, |
| 1665 | .release = mce_release, |
| 1666 | .read = mce_read, |
| 1667 | .poll = mce_poll, |
| 1668 | .unlocked_ioctl = mce_ioctl, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1669 | }; |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 1670 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1671 | |
| 1672 | static struct miscdevice mce_log_device = { |
| 1673 | MISC_MCELOG_MINOR, |
| 1674 | "mcelog", |
| 1675 | &mce_chrdev_ops, |
| 1676 | }; |
| 1677 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1678 | /* |
Hidetoshi Seto | 62fdac5 | 2009-06-11 16:06:07 +0900 | [diff] [blame] | 1679 | * mce=off Disables machine check |
| 1680 | * mce=no_cmci Disables CMCI |
| 1681 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. |
| 1682 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1683 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
| 1684 | * monarchtimeout is how long to wait for other CPUs on machine |
| 1685 | * check, or 0 to not wait |
Hidetoshi Seto | 13503fa | 2009-03-26 17:39:20 +0900 | [diff] [blame] | 1686 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
| 1687 | * mce=nobootlog Don't log MCEs from before booting. |
| 1688 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1689 | static int __init mcheck_enable(char *str) |
| 1690 | { |
Bartlomiej Zolnierkiewicz | e3346fc | 2009-07-28 23:55:09 +0200 | [diff] [blame] | 1691 | if (*str == 0) { |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 1692 | enable_p5_mce(); |
Bartlomiej Zolnierkiewicz | e3346fc | 2009-07-28 23:55:09 +0200 | [diff] [blame] | 1693 | return 1; |
| 1694 | } |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 1695 | if (*str == '=') |
| 1696 | str++; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1697 | if (!strcmp(str, "off")) |
Andi Kleen | 04b2b1a | 2009-04-28 22:50:19 +0200 | [diff] [blame] | 1698 | mce_disabled = 1; |
Hidetoshi Seto | 62fdac5 | 2009-06-11 16:06:07 +0900 | [diff] [blame] | 1699 | else if (!strcmp(str, "no_cmci")) |
| 1700 | mce_cmci_disabled = 1; |
| 1701 | else if (!strcmp(str, "dont_log_ce")) |
| 1702 | mce_dont_log_ce = 1; |
| 1703 | else if (!strcmp(str, "ignore_ce")) |
| 1704 | mce_ignore_ce = 1; |
Hidetoshi Seto | 13503fa | 2009-03-26 17:39:20 +0900 | [diff] [blame] | 1705 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
| 1706 | mce_bootlog = (str[0] == 'b'); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1707 | else if (isdigit(str[0])) { |
Andi Kleen | 8c566ef | 2005-09-12 18:49:24 +0200 | [diff] [blame] | 1708 | get_option(&str, &tolerant); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1709 | if (*str == ',') { |
| 1710 | ++str; |
| 1711 | get_option(&str, &monarch_timeout); |
| 1712 | } |
| 1713 | } else { |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 1714 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
Hidetoshi Seto | 13503fa | 2009-03-26 17:39:20 +0900 | [diff] [blame] | 1715 | str); |
| 1716 | return 0; |
| 1717 | } |
OGAWA Hirofumi | 9b41046 | 2006-03-31 02:30:33 -0800 | [diff] [blame] | 1718 | return 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1719 | } |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 1720 | __setup("mce", mcheck_enable); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1721 | |
Yong Wang | a2202aa | 2009-11-10 09:38:24 +0800 | [diff] [blame] | 1722 | int __init mcheck_init(void) |
Borislav Petkov | b33a636 | 2009-10-16 12:31:33 +0200 | [diff] [blame] | 1723 | { |
| 1724 | atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb); |
| 1725 | |
Yong Wang | a2202aa | 2009-11-10 09:38:24 +0800 | [diff] [blame] | 1726 | mcheck_intel_therm_init(); |
| 1727 | |
Borislav Petkov | b33a636 | 2009-10-16 12:31:33 +0200 | [diff] [blame] | 1728 | return 0; |
| 1729 | } |
Borislav Petkov | b33a636 | 2009-10-16 12:31:33 +0200 | [diff] [blame] | 1730 | |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1731 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1732 | * Sysfs support |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1733 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1734 | |
Andi Kleen | 973a2dd | 2009-02-12 13:39:32 +0100 | [diff] [blame] | 1735 | /* |
| 1736 | * Disable machine checks on suspend and shutdown. We can't really handle |
| 1737 | * them later. |
| 1738 | */ |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 1739 | static int mce_disable_error_reporting(void) |
Andi Kleen | 973a2dd | 2009-02-12 13:39:32 +0100 | [diff] [blame] | 1740 | { |
| 1741 | int i; |
| 1742 | |
Andi Kleen | 06b7a7a | 2009-04-27 18:37:43 +0200 | [diff] [blame] | 1743 | for (i = 0; i < banks; i++) { |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1744 | struct mce_bank *b = &mce_banks[i]; |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 1745 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1746 | if (b->init) |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 1747 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
Andi Kleen | 06b7a7a | 2009-04-27 18:37:43 +0200 | [diff] [blame] | 1748 | } |
Andi Kleen | 973a2dd | 2009-02-12 13:39:32 +0100 | [diff] [blame] | 1749 | return 0; |
| 1750 | } |
| 1751 | |
| 1752 | static int mce_suspend(struct sys_device *dev, pm_message_t state) |
| 1753 | { |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 1754 | return mce_disable_error_reporting(); |
Andi Kleen | 973a2dd | 2009-02-12 13:39:32 +0100 | [diff] [blame] | 1755 | } |
| 1756 | |
| 1757 | static int mce_shutdown(struct sys_device *dev) |
| 1758 | { |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 1759 | return mce_disable_error_reporting(); |
Andi Kleen | 973a2dd | 2009-02-12 13:39:32 +0100 | [diff] [blame] | 1760 | } |
| 1761 | |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1762 | /* |
| 1763 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. |
| 1764 | * Only one CPU is active at this time, the others get re-added later using |
| 1765 | * CPU hotplug: |
| 1766 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1767 | static int mce_resume(struct sys_device *dev) |
| 1768 | { |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 1769 | __mcheck_cpu_init_generic(); |
| 1770 | __mcheck_cpu_init_vendor(¤t_cpu_data); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1771 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1772 | return 0; |
| 1773 | } |
| 1774 | |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1775 | static void mce_cpu_restart(void *data) |
| 1776 | { |
| 1777 | del_timer_sync(&__get_cpu_var(mce_timer)); |
Hidetoshi Seto | 33edbf0 | 2009-06-15 17:18:45 +0900 | [diff] [blame] | 1778 | if (!mce_available(¤t_cpu_data)) |
| 1779 | return; |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 1780 | __mcheck_cpu_init_generic(); |
| 1781 | __mcheck_cpu_init_timer(); |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1782 | } |
| 1783 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1784 | /* Reinit MCEs after user configuration changes */ |
Thomas Gleixner | d88203d | 2007-10-23 22:37:23 +0200 | [diff] [blame] | 1785 | static void mce_restart(void) |
| 1786 | { |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 1787 | on_each_cpu(mce_cpu_restart, NULL, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1788 | } |
| 1789 | |
Hidetoshi Seto | 9af43b5 | 2009-06-15 17:21:36 +0900 | [diff] [blame] | 1790 | /* Toggle features for corrected errors */ |
| 1791 | static void mce_disable_ce(void *all) |
| 1792 | { |
| 1793 | if (!mce_available(¤t_cpu_data)) |
| 1794 | return; |
| 1795 | if (all) |
| 1796 | del_timer_sync(&__get_cpu_var(mce_timer)); |
| 1797 | cmci_clear(); |
| 1798 | } |
| 1799 | |
| 1800 | static void mce_enable_ce(void *all) |
| 1801 | { |
| 1802 | if (!mce_available(¤t_cpu_data)) |
| 1803 | return; |
| 1804 | cmci_reenable(); |
| 1805 | cmci_recheck(); |
| 1806 | if (all) |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 1807 | __mcheck_cpu_init_timer(); |
Hidetoshi Seto | 9af43b5 | 2009-06-15 17:21:36 +0900 | [diff] [blame] | 1808 | } |
| 1809 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1810 | static struct sysdev_class mce_sysclass = { |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1811 | .suspend = mce_suspend, |
| 1812 | .shutdown = mce_shutdown, |
| 1813 | .resume = mce_resume, |
| 1814 | .name = "machinecheck", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1815 | }; |
| 1816 | |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1817 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1818 | |
| 1819 | __cpuinitdata |
| 1820 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1821 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1822 | static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr) |
| 1823 | { |
| 1824 | return container_of(attr, struct mce_bank, attr); |
| 1825 | } |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1826 | |
| 1827 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, |
| 1828 | char *buf) |
| 1829 | { |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1830 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1831 | } |
| 1832 | |
| 1833 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, |
Hidetoshi Seto | 9319cec | 2009-04-14 17:26:30 +0900 | [diff] [blame] | 1834 | const char *buf, size_t size) |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1835 | { |
Hidetoshi Seto | 9319cec | 2009-04-14 17:26:30 +0900 | [diff] [blame] | 1836 | u64 new; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1837 | |
Hidetoshi Seto | 9319cec | 2009-04-14 17:26:30 +0900 | [diff] [blame] | 1838 | if (strict_strtoull(buf, 0, &new) < 0) |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1839 | return -EINVAL; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1840 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1841 | attr_to_bank(attr)->ctl = new; |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1842 | mce_restart(); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1843 | |
Hidetoshi Seto | 9319cec | 2009-04-14 17:26:30 +0900 | [diff] [blame] | 1844 | return size; |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1845 | } |
Andi Kleen | a98f0dd | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 1846 | |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1847 | static ssize_t |
| 1848 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) |
Andi Kleen | a98f0dd | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 1849 | { |
Hidetoshi Seto | 1020bcb | 2009-06-15 17:20:57 +0900 | [diff] [blame] | 1850 | strcpy(buf, mce_helper); |
Andi Kleen | a98f0dd | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 1851 | strcat(buf, "\n"); |
Hidetoshi Seto | 1020bcb | 2009-06-15 17:20:57 +0900 | [diff] [blame] | 1852 | return strlen(mce_helper) + 1; |
Andi Kleen | a98f0dd | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 1853 | } |
| 1854 | |
Andi Kleen | 4a0b2b4 | 2008-07-01 18:48:41 +0200 | [diff] [blame] | 1855 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1856 | const char *buf, size_t siz) |
Andi Kleen | a98f0dd | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 1857 | { |
| 1858 | char *p; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1859 | |
Hidetoshi Seto | 1020bcb | 2009-06-15 17:20:57 +0900 | [diff] [blame] | 1860 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
| 1861 | mce_helper[sizeof(mce_helper)-1] = 0; |
Hidetoshi Seto | 1020bcb | 2009-06-15 17:20:57 +0900 | [diff] [blame] | 1862 | p = strchr(mce_helper, '\n'); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1863 | |
Jan Beulich | e9084ec | 2009-07-16 09:45:11 +0100 | [diff] [blame] | 1864 | if (p) |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1865 | *p = 0; |
| 1866 | |
Jan Beulich | e9084ec | 2009-07-16 09:45:11 +0100 | [diff] [blame] | 1867 | return strlen(mce_helper) + !!p; |
Andi Kleen | a98f0dd | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 1868 | } |
| 1869 | |
Hidetoshi Seto | 9af43b5 | 2009-06-15 17:21:36 +0900 | [diff] [blame] | 1870 | static ssize_t set_ignore_ce(struct sys_device *s, |
| 1871 | struct sysdev_attribute *attr, |
| 1872 | const char *buf, size_t size) |
| 1873 | { |
| 1874 | u64 new; |
| 1875 | |
| 1876 | if (strict_strtoull(buf, 0, &new) < 0) |
| 1877 | return -EINVAL; |
| 1878 | |
| 1879 | if (mce_ignore_ce ^ !!new) { |
| 1880 | if (new) { |
| 1881 | /* disable ce features */ |
| 1882 | on_each_cpu(mce_disable_ce, (void *)1, 1); |
| 1883 | mce_ignore_ce = 1; |
| 1884 | } else { |
| 1885 | /* enable ce features */ |
| 1886 | mce_ignore_ce = 0; |
| 1887 | on_each_cpu(mce_enable_ce, (void *)1, 1); |
| 1888 | } |
| 1889 | } |
| 1890 | return size; |
| 1891 | } |
| 1892 | |
| 1893 | static ssize_t set_cmci_disabled(struct sys_device *s, |
| 1894 | struct sysdev_attribute *attr, |
| 1895 | const char *buf, size_t size) |
| 1896 | { |
| 1897 | u64 new; |
| 1898 | |
| 1899 | if (strict_strtoull(buf, 0, &new) < 0) |
| 1900 | return -EINVAL; |
| 1901 | |
| 1902 | if (mce_cmci_disabled ^ !!new) { |
| 1903 | if (new) { |
| 1904 | /* disable cmci */ |
| 1905 | on_each_cpu(mce_disable_ce, NULL, 1); |
| 1906 | mce_cmci_disabled = 1; |
| 1907 | } else { |
| 1908 | /* enable cmci */ |
| 1909 | mce_cmci_disabled = 0; |
| 1910 | on_each_cpu(mce_enable_ce, NULL, 1); |
| 1911 | } |
| 1912 | } |
| 1913 | return size; |
| 1914 | } |
| 1915 | |
Andi Kleen | b56f642 | 2009-05-27 21:56:52 +0200 | [diff] [blame] | 1916 | static ssize_t store_int_with_restart(struct sys_device *s, |
| 1917 | struct sysdev_attribute *attr, |
| 1918 | const char *buf, size_t size) |
| 1919 | { |
| 1920 | ssize_t ret = sysdev_store_int(s, attr, buf, size); |
| 1921 | mce_restart(); |
| 1922 | return ret; |
| 1923 | } |
| 1924 | |
Andi Kleen | a98f0dd | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 1925 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
Andi Kleen | d95d62c | 2008-07-01 18:48:43 +0200 | [diff] [blame] | 1926 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1927 | static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout); |
Hidetoshi Seto | 9af43b5 | 2009-06-15 17:21:36 +0900 | [diff] [blame] | 1928 | static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1929 | |
Andi Kleen | b56f642 | 2009-05-27 21:56:52 +0200 | [diff] [blame] | 1930 | static struct sysdev_ext_attribute attr_check_interval = { |
| 1931 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, |
| 1932 | store_int_with_restart), |
| 1933 | &check_interval |
| 1934 | }; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1935 | |
Hidetoshi Seto | 9af43b5 | 2009-06-15 17:21:36 +0900 | [diff] [blame] | 1936 | static struct sysdev_ext_attribute attr_ignore_ce = { |
| 1937 | _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce), |
| 1938 | &mce_ignore_ce |
| 1939 | }; |
| 1940 | |
| 1941 | static struct sysdev_ext_attribute attr_cmci_disabled = { |
Yinghai Lu | 74b602c | 2009-06-17 14:43:32 -0700 | [diff] [blame] | 1942 | _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled), |
Hidetoshi Seto | 9af43b5 | 2009-06-15 17:21:36 +0900 | [diff] [blame] | 1943 | &mce_cmci_disabled |
| 1944 | }; |
| 1945 | |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1946 | static struct sysdev_attribute *mce_attrs[] = { |
Hidetoshi Seto | 9af43b5 | 2009-06-15 17:21:36 +0900 | [diff] [blame] | 1947 | &attr_tolerant.attr, |
| 1948 | &attr_check_interval.attr, |
| 1949 | &attr_trigger, |
Andi Kleen | 3c07979 | 2009-05-27 21:56:55 +0200 | [diff] [blame] | 1950 | &attr_monarch_timeout.attr, |
Hidetoshi Seto | 9af43b5 | 2009-06-15 17:21:36 +0900 | [diff] [blame] | 1951 | &attr_dont_log_ce.attr, |
| 1952 | &attr_ignore_ce.attr, |
| 1953 | &attr_cmci_disabled.attr, |
Andi Kleen | a98f0dd | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 1954 | NULL |
| 1955 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1956 | |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1957 | static cpumask_var_t mce_dev_initialized; |
Andreas Herrmann | bae19fe | 2007-11-14 17:00:44 -0800 | [diff] [blame] | 1958 | |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1959 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1960 | static __cpuinit int mce_create_device(unsigned int cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1961 | { |
| 1962 | int err; |
Hidetoshi Seto | b1f49f9 | 2009-06-18 14:53:24 +0900 | [diff] [blame] | 1963 | int i, j; |
Mike Travis | 92cb761 | 2007-10-19 20:35:04 +0200 | [diff] [blame] | 1964 | |
Andreas Herrmann | 9036755 | 2007-11-07 02:12:58 +0100 | [diff] [blame] | 1965 | if (!mce_available(&boot_cpu_data)) |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1966 | return -EIO; |
| 1967 | |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1968 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
| 1969 | per_cpu(mce_dev, cpu).id = cpu; |
| 1970 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1971 | |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1972 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
Akinobu Mita | d435d86 | 2007-10-18 03:05:15 -0700 | [diff] [blame] | 1973 | if (err) |
| 1974 | return err; |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1975 | |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1976 | for (i = 0; mce_attrs[i]; i++) { |
| 1977 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); |
Akinobu Mita | d435d86 | 2007-10-18 03:05:15 -0700 | [diff] [blame] | 1978 | if (err) |
| 1979 | goto error; |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1980 | } |
Hidetoshi Seto | b1f49f9 | 2009-06-18 14:53:24 +0900 | [diff] [blame] | 1981 | for (j = 0; j < banks; j++) { |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1982 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1983 | &mce_banks[j].attr); |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1984 | if (err) |
| 1985 | goto error2; |
| 1986 | } |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1987 | cpumask_set_cpu(cpu, mce_dev_initialized); |
Akinobu Mita | d435d86 | 2007-10-18 03:05:15 -0700 | [diff] [blame] | 1988 | |
| 1989 | return 0; |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 1990 | error2: |
Hidetoshi Seto | b1f49f9 | 2009-06-18 14:53:24 +0900 | [diff] [blame] | 1991 | while (--j >= 0) |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 1992 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr); |
Akinobu Mita | d435d86 | 2007-10-18 03:05:15 -0700 | [diff] [blame] | 1993 | error: |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1994 | while (--i >= 0) |
Hidetoshi Seto | 5c0e9f2 | 2009-12-08 16:52:44 +0900 | [diff] [blame] | 1995 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 1996 | |
| 1997 | sysdev_unregister(&per_cpu(mce_dev, cpu)); |
Akinobu Mita | d435d86 | 2007-10-18 03:05:15 -0700 | [diff] [blame] | 1998 | |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 1999 | return err; |
| 2000 | } |
| 2001 | |
Jan Beulich | 2d9cd6c | 2008-08-29 13:15:04 +0100 | [diff] [blame] | 2002 | static __cpuinit void mce_remove_device(unsigned int cpu) |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2003 | { |
Shaohua Li | 73ca535 | 2006-01-11 22:43:06 +0100 | [diff] [blame] | 2004 | int i; |
| 2005 | |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 2006 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
Andreas Herrmann | bae19fe | 2007-11-14 17:00:44 -0800 | [diff] [blame] | 2007 | return; |
| 2008 | |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 2009 | for (i = 0; mce_attrs[i]; i++) |
| 2010 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); |
| 2011 | |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 2012 | for (i = 0; i < banks; i++) |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 2013 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr); |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 2014 | |
| 2015 | sysdev_unregister(&per_cpu(mce_dev, cpu)); |
| 2016 | cpumask_clear_cpu(cpu, mce_dev_initialized); |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2017 | } |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2018 | |
Andi Kleen | d6b7558 | 2009-02-12 13:39:31 +0100 | [diff] [blame] | 2019 | /* Make sure there are no machine checks on offlined CPUs. */ |
Hidetoshi Seto | 767df1b | 2009-11-26 17:29:02 +0900 | [diff] [blame] | 2020 | static void __cpuinit mce_disable_cpu(void *h) |
Andi Kleen | d6b7558 | 2009-02-12 13:39:31 +0100 | [diff] [blame] | 2021 | { |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 2022 | unsigned long action = *(unsigned long *)h; |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 2023 | int i; |
Andi Kleen | d6b7558 | 2009-02-12 13:39:31 +0100 | [diff] [blame] | 2024 | |
| 2025 | if (!mce_available(¤t_cpu_data)) |
| 2026 | return; |
Hidetoshi Seto | 767df1b | 2009-11-26 17:29:02 +0900 | [diff] [blame] | 2027 | |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 2028 | if (!(action & CPU_TASKS_FROZEN)) |
| 2029 | cmci_clear(); |
Andi Kleen | 06b7a7a | 2009-04-27 18:37:43 +0200 | [diff] [blame] | 2030 | for (i = 0; i < banks; i++) { |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 2031 | struct mce_bank *b = &mce_banks[i]; |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 2032 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 2033 | if (b->init) |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 2034 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
Andi Kleen | 06b7a7a | 2009-04-27 18:37:43 +0200 | [diff] [blame] | 2035 | } |
Andi Kleen | d6b7558 | 2009-02-12 13:39:31 +0100 | [diff] [blame] | 2036 | } |
| 2037 | |
Hidetoshi Seto | 767df1b | 2009-11-26 17:29:02 +0900 | [diff] [blame] | 2038 | static void __cpuinit mce_reenable_cpu(void *h) |
Andi Kleen | d6b7558 | 2009-02-12 13:39:31 +0100 | [diff] [blame] | 2039 | { |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 2040 | unsigned long action = *(unsigned long *)h; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 2041 | int i; |
Andi Kleen | d6b7558 | 2009-02-12 13:39:31 +0100 | [diff] [blame] | 2042 | |
| 2043 | if (!mce_available(¤t_cpu_data)) |
| 2044 | return; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 2045 | |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 2046 | if (!(action & CPU_TASKS_FROZEN)) |
| 2047 | cmci_reenable(); |
Andi Kleen | 06b7a7a | 2009-04-27 18:37:43 +0200 | [diff] [blame] | 2048 | for (i = 0; i < banks; i++) { |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 2049 | struct mce_bank *b = &mce_banks[i]; |
Ingo Molnar | 11868a2 | 2009-09-23 17:49:55 +0200 | [diff] [blame] | 2050 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 2051 | if (b->init) |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 2052 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
Andi Kleen | 06b7a7a | 2009-04-27 18:37:43 +0200 | [diff] [blame] | 2053 | } |
Andi Kleen | d6b7558 | 2009-02-12 13:39:31 +0100 | [diff] [blame] | 2054 | } |
| 2055 | |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2056 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 2057 | static int __cpuinit |
| 2058 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2059 | { |
| 2060 | unsigned int cpu = (unsigned long)hcpu; |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 2061 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2062 | |
| 2063 | switch (action) { |
Andreas Herrmann | bae19fe | 2007-11-14 17:00:44 -0800 | [diff] [blame] | 2064 | case CPU_ONLINE: |
| 2065 | case CPU_ONLINE_FROZEN: |
| 2066 | mce_create_device(cpu); |
Rafael J. Wysocki | 8735728 | 2008-08-22 22:23:09 +0200 | [diff] [blame] | 2067 | if (threshold_cpu_callback) |
| 2068 | threshold_cpu_callback(action, cpu); |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2069 | break; |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2070 | case CPU_DEAD: |
Rafael J. Wysocki | 8bb7844 | 2007-05-09 02:35:10 -0700 | [diff] [blame] | 2071 | case CPU_DEAD_FROZEN: |
Rafael J. Wysocki | 8735728 | 2008-08-22 22:23:09 +0200 | [diff] [blame] | 2072 | if (threshold_cpu_callback) |
| 2073 | threshold_cpu_callback(action, cpu); |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2074 | mce_remove_device(cpu); |
| 2075 | break; |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 2076 | case CPU_DOWN_PREPARE: |
| 2077 | case CPU_DOWN_PREPARE_FROZEN: |
| 2078 | del_timer_sync(t); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 2079 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 2080 | break; |
| 2081 | case CPU_DOWN_FAILED: |
| 2082 | case CPU_DOWN_FAILED_FROZEN: |
Hidetoshi Seto | fe5ed91 | 2009-12-03 11:33:08 +0900 | [diff] [blame] | 2083 | if (!mce_ignore_ce && check_interval) { |
| 2084 | t->expires = round_jiffies(jiffies + |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 2085 | __get_cpu_var(mce_next_interval)); |
Hidetoshi Seto | fe5ed91 | 2009-12-03 11:33:08 +0900 | [diff] [blame] | 2086 | add_timer_on(t, cpu); |
| 2087 | } |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 2088 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
| 2089 | break; |
| 2090 | case CPU_POST_DEAD: |
| 2091 | /* intentionally ignoring frozen here */ |
| 2092 | cmci_rediscover(cpu); |
Andi Kleen | 52d168e | 2009-02-12 13:39:29 +0100 | [diff] [blame] | 2093 | break; |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2094 | } |
Andreas Herrmann | bae19fe | 2007-11-14 17:00:44 -0800 | [diff] [blame] | 2095 | return NOTIFY_OK; |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2096 | } |
| 2097 | |
Sam Ravnborg | 1e35669 | 2008-01-30 13:33:36 +0100 | [diff] [blame] | 2098 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2099 | .notifier_call = mce_cpu_callback, |
| 2100 | }; |
| 2101 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 2102 | static __init void mce_init_banks(void) |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 2103 | { |
| 2104 | int i; |
| 2105 | |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 2106 | for (i = 0; i < banks; i++) { |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 2107 | struct mce_bank *b = &mce_banks[i]; |
| 2108 | struct sysdev_attribute *a = &b->attr; |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 2109 | |
Eric W. Biederman | a07e415 | 2010-02-11 15:23:05 -0800 | [diff] [blame] | 2110 | sysfs_attr_init(&a->attr); |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 2111 | a->attr.name = b->attrname; |
| 2112 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 2113 | |
| 2114 | a->attr.mode = 0644; |
| 2115 | a->show = show_bank; |
| 2116 | a->store = set_bank; |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 2117 | } |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 2118 | } |
| 2119 | |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 2120 | static __init int mcheck_init_device(void) |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2121 | { |
| 2122 | int err; |
| 2123 | int i = 0; |
| 2124 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2125 | if (!mce_available(&boot_cpu_data)) |
| 2126 | return -EIO; |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 2127 | |
Yinghai Lu | e92fae0 | 2009-06-17 16:21:33 -0700 | [diff] [blame] | 2128 | zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
Rusty Russell | 996867d | 2009-03-13 14:49:51 +1030 | [diff] [blame] | 2129 | |
Andi Kleen | cebe182 | 2009-07-09 00:31:43 +0200 | [diff] [blame] | 2130 | mce_init_banks(); |
Andi Kleen | 0d7482e3 | 2009-02-17 23:07:13 +0100 | [diff] [blame] | 2131 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2132 | err = sysdev_class_register(&mce_sysclass); |
Akinobu Mita | d435d86 | 2007-10-18 03:05:15 -0700 | [diff] [blame] | 2133 | if (err) |
| 2134 | return err; |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2135 | |
| 2136 | for_each_online_cpu(i) { |
Akinobu Mita | d435d86 | 2007-10-18 03:05:15 -0700 | [diff] [blame] | 2137 | err = mce_create_device(i); |
| 2138 | if (err) |
| 2139 | return err; |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2140 | } |
| 2141 | |
Chandra Seetharaman | be6b5a3 | 2006-07-30 03:03:37 -0700 | [diff] [blame] | 2142 | register_hotcpu_notifier(&mce_cpu_notifier); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2143 | misc_register(&mce_log_device); |
Ingo Molnar | e9eee03 | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 2144 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2145 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2146 | } |
Andi Kleen | 91c6d40 | 2005-07-28 21:15:39 -0700 | [diff] [blame] | 2147 | |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 2148 | device_initcall(mcheck_init_device); |
Ingo Molnar | a988d33 | 2009-04-08 12:31:25 +0200 | [diff] [blame] | 2149 | |
Andi Kleen | d7c3c9a | 2009-04-28 23:07:25 +0200 | [diff] [blame] | 2150 | /* |
| 2151 | * Old style boot options parsing. Only for compatibility. |
| 2152 | */ |
| 2153 | static int __init mcheck_disable(char *str) |
| 2154 | { |
| 2155 | mce_disabled = 1; |
| 2156 | return 1; |
| 2157 | } |
| 2158 | __setup("nomce", mcheck_disable); |
Huang Ying | 5be9ed2 | 2009-07-31 09:41:42 +0800 | [diff] [blame] | 2159 | |
| 2160 | #ifdef CONFIG_DEBUG_FS |
| 2161 | struct dentry *mce_get_debugfs_dir(void) |
| 2162 | { |
| 2163 | static struct dentry *dmce; |
| 2164 | |
| 2165 | if (!dmce) |
| 2166 | dmce = debugfs_create_dir("mce", NULL); |
| 2167 | |
| 2168 | return dmce; |
| 2169 | } |
Huang Ying | bf783f9 | 2009-07-31 09:41:43 +0800 | [diff] [blame] | 2170 | |
| 2171 | static void mce_reset(void) |
| 2172 | { |
| 2173 | cpu_missing = 0; |
| 2174 | atomic_set(&mce_fake_paniced, 0); |
| 2175 | atomic_set(&mce_executing, 0); |
| 2176 | atomic_set(&mce_callin, 0); |
| 2177 | atomic_set(&global_nwo, 0); |
| 2178 | } |
| 2179 | |
| 2180 | static int fake_panic_get(void *data, u64 *val) |
| 2181 | { |
| 2182 | *val = fake_panic; |
| 2183 | return 0; |
| 2184 | } |
| 2185 | |
| 2186 | static int fake_panic_set(void *data, u64 val) |
| 2187 | { |
| 2188 | mce_reset(); |
| 2189 | fake_panic = val; |
| 2190 | return 0; |
| 2191 | } |
| 2192 | |
| 2193 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
| 2194 | fake_panic_set, "%llu\n"); |
| 2195 | |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 2196 | static int __init mcheck_debugfs_init(void) |
Huang Ying | bf783f9 | 2009-07-31 09:41:43 +0800 | [diff] [blame] | 2197 | { |
| 2198 | struct dentry *dmce, *ffake_panic; |
| 2199 | |
| 2200 | dmce = mce_get_debugfs_dir(); |
| 2201 | if (!dmce) |
| 2202 | return -ENOMEM; |
| 2203 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, |
| 2204 | &fake_panic_fops); |
| 2205 | if (!ffake_panic) |
| 2206 | return -ENOMEM; |
| 2207 | |
| 2208 | return 0; |
| 2209 | } |
Borislav Petkov | 5e09954 | 2009-10-16 12:31:32 +0200 | [diff] [blame] | 2210 | late_initcall(mcheck_debugfs_init); |
Huang Ying | 5be9ed2 | 2009-07-31 09:41:42 +0800 | [diff] [blame] | 2211 | #endif |