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Russell Kinga8cbcd92009-05-16 11:51:14 +01001/*
2 * linux/arch/arm/kernel/smp_scu.c
3 *
4 * Copyright (C) 2002 ARM Ltd.
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/init.h>
12#include <linux/io.h>
13
Will Deacon0bd82ad2012-02-24 12:20:16 +010014#include <asm/smp_plat.h>
Russell Kinga8cbcd92009-05-16 11:51:14 +010015#include <asm/smp_scu.h>
Catalin Marinasaf731102009-05-18 16:26:27 +010016#include <asm/cacheflush.h>
Will Deaconf630c1b2011-09-15 11:45:15 +010017#include <asm/cputype.h>
Russell Kinga8cbcd92009-05-16 11:51:14 +010018
19#define SCU_CTRL 0x00
20#define SCU_CONFIG 0x04
21#define SCU_CPU_STATUS 0x08
22#define SCU_INVALIDATE 0x0c
23#define SCU_FPGA_REVISION 0x10
24
Rob Herring10cdc7e2011-06-13 15:28:53 +010025#ifdef CONFIG_SMP
Russell Kinga8cbcd92009-05-16 11:51:14 +010026/*
27 * Get the number of CPU cores from the SCU configuration
28 */
29unsigned int __init scu_get_core_count(void __iomem *scu_base)
30{
Ben Dooks099a4802013-02-07 11:14:21 +000031 unsigned int ncores = readl_relaxed(scu_base + SCU_CONFIG);
Russell Kinga8cbcd92009-05-16 11:51:14 +010032 return (ncores & 0x03) + 1;
33}
34
35/*
36 * Enable the SCU
37 */
Shawn Guo26a527e2011-09-25 08:25:43 +010038void scu_enable(void __iomem *scu_base)
Russell Kinga8cbcd92009-05-16 11:51:14 +010039{
40 u32 scu_ctrl;
41
Will Deaconf630c1b2011-09-15 11:45:15 +010042#ifdef CONFIG_ARM_ERRATA_764369
43 /* Cortex-A9 only */
Uwe Kleine-Königac52e832013-01-30 17:38:21 +010044 if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc090) {
Ben Dooks099a4802013-02-07 11:14:21 +000045 scu_ctrl = readl_relaxed(scu_base + 0x30);
Will Deaconf630c1b2011-09-15 11:45:15 +010046 if (!(scu_ctrl & 1))
Ben Dooks099a4802013-02-07 11:14:21 +000047 writel_relaxed(scu_ctrl | 0x1, scu_base + 0x30);
Will Deaconf630c1b2011-09-15 11:45:15 +010048 }
49#endif
50
Ben Dooks099a4802013-02-07 11:14:21 +000051 scu_ctrl = readl_relaxed(scu_base + SCU_CTRL);
Catalin Marinas9b229fa2009-11-04 12:16:38 +000052 /* already enabled? */
53 if (scu_ctrl & 1)
54 return;
55
Russell Kinga8cbcd92009-05-16 11:51:14 +010056 scu_ctrl |= 1;
Ben Dooks099a4802013-02-07 11:14:21 +000057 writel_relaxed(scu_ctrl, scu_base + SCU_CTRL);
Catalin Marinasaf731102009-05-18 16:26:27 +010058
59 /*
60 * Ensure that the data accessed by CPU0 before the SCU was
61 * initialised is visible to the other CPUs.
62 */
63 flush_cache_all();
Russell Kinga8cbcd92009-05-16 11:51:14 +010064}
Rob Herring10cdc7e2011-06-13 15:28:53 +010065#endif
Russell King292ec422011-02-04 10:36:39 +000066
67/*
68 * Set the executing CPUs power mode as defined. This will be in
69 * preparation for it executing a WFI instruction.
70 *
71 * This function must be called with preemption disabled, and as it
72 * has the side effect of disabling coherency, caches must have been
73 * flushed. Interrupts must also have been disabled.
74 */
75int scu_power_mode(void __iomem *scu_base, unsigned int mode)
76{
77 unsigned int val;
Rob Herringc7d5b932013-01-31 13:26:29 -060078 int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
Russell King292ec422011-02-04 10:36:39 +000079
80 if (mode > 3 || mode == 1 || cpu > 3)
81 return -EINVAL;
82
Ben Dooks099a4802013-02-07 11:14:21 +000083 val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
Russell King292ec422011-02-04 10:36:39 +000084 val |= mode;
Ben Dooks099a4802013-02-07 11:14:21 +000085 writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);
Russell King292ec422011-02-04 10:36:39 +000086
87 return 0;
88}