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Thomas Gleixner09c434b2019-05-19 13:08:20 +01001// SPDX-License-Identifier: GPL-2.0-only
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +01002/*
3 * CE4100's SPI device is more or less the same one as found on PXA
4 *
Andy Shevchenkoe379d2c2016-07-04 12:44:27 +03005 * Copyright (C) 2016, Intel Corporation
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +01006 */
Andy Shevchenkoe379d2c2016-07-04 12:44:27 +03007#include <linux/clk-provider.h>
8#include <linux/module.h>
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +01009#include <linux/pci.h>
10#include <linux/platform_device.h>
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +010011#include <linux/spi/pxa2xx_spi.h>
12
Mika Westerbergb729bf32014-08-19 20:29:19 +030013#include <linux/dmaengine.h>
14#include <linux/platform_data/dma-dw.h>
15
Chew, Chiau Eed6ba32d2014-04-18 00:26:06 +080016enum {
Andy Shevchenkoe379d2c2016-07-04 12:44:27 +030017 PORT_QUARK_X1000,
Chew, Chiau Eed6ba32d2014-04-18 00:26:06 +080018 PORT_BYT,
Andy Shevchenko4f470912016-07-04 12:44:25 +030019 PORT_MRFLD,
Mika Westerberg39d36532014-08-19 20:29:21 +030020 PORT_BSW0,
21 PORT_BSW1,
22 PORT_BSW2,
Andy Shevchenkoe379d2c2016-07-04 12:44:27 +030023 PORT_CE4100,
Andy Shevchenko54c5d3b2021-02-08 18:38:15 +020024 PORT_LPT0,
25 PORT_LPT1,
Chew, Chiau Eed6ba32d2014-04-18 00:26:06 +080026};
27
28struct pxa_spi_info {
29 enum pxa_ssp_type type;
30 int port_id;
31 int num_chipselect;
Chew, Chiau Eeafa93c92014-07-25 01:10:54 +080032 unsigned long max_clk_rate;
Mika Westerbergb729bf32014-08-19 20:29:19 +030033
34 /* DMA channel request parameters */
Andy Shevchenko743485ea2016-07-04 12:44:24 +030035 bool (*dma_filter)(struct dma_chan *chan, void *param);
Mika Westerbergb729bf32014-08-19 20:29:19 +030036 void *tx_param;
37 void *rx_param;
Andy Shevchenko743485ea2016-07-04 12:44:24 +030038
Andy Shevchenko37821a822019-03-19 17:48:42 +020039 int dma_burst_size;
40
Andy Shevchenko743485ea2016-07-04 12:44:24 +030041 int (*setup)(struct pci_dev *pdev, struct pxa_spi_info *c);
Chew, Chiau Eed6ba32d2014-04-18 00:26:06 +080042};
43
Mika Westerbergb729bf32014-08-19 20:29:19 +030044static struct dw_dma_slave byt_tx_param = { .dst_id = 0 };
45static struct dw_dma_slave byt_rx_param = { .src_id = 1 };
46
Andy Shevchenko25014522017-01-02 13:47:31 +020047static struct dw_dma_slave mrfld3_tx_param = { .dst_id = 15 };
48static struct dw_dma_slave mrfld3_rx_param = { .src_id = 14 };
49static struct dw_dma_slave mrfld5_tx_param = { .dst_id = 13 };
50static struct dw_dma_slave mrfld5_rx_param = { .src_id = 12 };
51static struct dw_dma_slave mrfld6_tx_param = { .dst_id = 11 };
52static struct dw_dma_slave mrfld6_rx_param = { .src_id = 10 };
53
Mika Westerberg39d36532014-08-19 20:29:21 +030054static struct dw_dma_slave bsw0_tx_param = { .dst_id = 0 };
55static struct dw_dma_slave bsw0_rx_param = { .src_id = 1 };
56static struct dw_dma_slave bsw1_tx_param = { .dst_id = 6 };
57static struct dw_dma_slave bsw1_rx_param = { .src_id = 7 };
58static struct dw_dma_slave bsw2_tx_param = { .dst_id = 8 };
59static struct dw_dma_slave bsw2_rx_param = { .src_id = 9 };
60
Andy Shevchenko54c5d3b2021-02-08 18:38:15 +020061static struct dw_dma_slave lpt1_tx_param = { .dst_id = 0 };
62static struct dw_dma_slave lpt1_rx_param = { .src_id = 1 };
63static struct dw_dma_slave lpt0_tx_param = { .dst_id = 2 };
64static struct dw_dma_slave lpt0_rx_param = { .src_id = 3 };
Leif Liddycaba2482016-02-20 20:20:22 +010065
Mika Westerbergb729bf32014-08-19 20:29:19 +030066static bool lpss_dma_filter(struct dma_chan *chan, void *param)
67{
68 struct dw_dma_slave *dws = param;
69
70 if (dws->dma_dev != chan->device->dev)
71 return false;
72
73 chan->private = dws;
74 return true;
75}
76
Andy Shevchenko743485ea2016-07-04 12:44:24 +030077static int lpss_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c)
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +010078{
Mika Westerbergb729bf32014-08-19 20:29:19 +030079 struct pci_dev *dma_dev;
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +010080
Andy Shevchenko743485ea2016-07-04 12:44:24 +030081 c->num_chipselect = 1;
82 c->max_clk_rate = 50000000;
Mika Westerbergb729bf32014-08-19 20:29:19 +030083
84 dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
85
86 if (c->tx_param) {
87 struct dw_dma_slave *slave = c->tx_param;
88
89 slave->dma_dev = &dma_dev->dev;
Andy Shevchenkoc4220252016-03-18 16:24:41 +020090 slave->m_master = 0;
91 slave->p_master = 1;
Mika Westerbergb729bf32014-08-19 20:29:19 +030092 }
93
94 if (c->rx_param) {
95 struct dw_dma_slave *slave = c->rx_param;
96
97 slave->dma_dev = &dma_dev->dev;
Andy Shevchenkoc4220252016-03-18 16:24:41 +020098 slave->m_master = 0;
99 slave->p_master = 1;
Mika Westerbergb729bf32014-08-19 20:29:19 +0300100 }
101
Andy Shevchenko743485ea2016-07-04 12:44:24 +0300102 c->dma_filter = lpss_dma_filter;
103 return 0;
104}
105
Andy Shevchenko4f470912016-07-04 12:44:25 +0300106static int mrfld_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c)
107{
Andy Shevchenko25014522017-01-02 13:47:31 +0200108 struct pci_dev *dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(21, 0));
109 struct dw_dma_slave *tx, *rx;
110
Andy Shevchenko4f470912016-07-04 12:44:25 +0300111 switch (PCI_FUNC(dev->devfn)) {
112 case 0:
113 c->port_id = 3;
114 c->num_chipselect = 1;
Andy Shevchenko25014522017-01-02 13:47:31 +0200115 c->tx_param = &mrfld3_tx_param;
116 c->rx_param = &mrfld3_rx_param;
Andy Shevchenko4f470912016-07-04 12:44:25 +0300117 break;
118 case 1:
119 c->port_id = 5;
120 c->num_chipselect = 4;
Andy Shevchenko25014522017-01-02 13:47:31 +0200121 c->tx_param = &mrfld5_tx_param;
122 c->rx_param = &mrfld5_rx_param;
Andy Shevchenko4f470912016-07-04 12:44:25 +0300123 break;
124 case 2:
125 c->port_id = 6;
126 c->num_chipselect = 1;
Andy Shevchenko25014522017-01-02 13:47:31 +0200127 c->tx_param = &mrfld6_tx_param;
128 c->rx_param = &mrfld6_rx_param;
Andy Shevchenko4f470912016-07-04 12:44:25 +0300129 break;
130 default:
131 return -ENODEV;
132 }
Andy Shevchenko25014522017-01-02 13:47:31 +0200133
134 tx = c->tx_param;
135 tx->dma_dev = &dma_dev->dev;
136
137 rx = c->rx_param;
138 rx->dma_dev = &dma_dev->dev;
139
140 c->dma_filter = lpss_dma_filter;
Andy Shevchenko37821a822019-03-19 17:48:42 +0200141 c->dma_burst_size = 8;
Andy Shevchenko4f470912016-07-04 12:44:25 +0300142 return 0;
143}
144
Andy Shevchenko743485ea2016-07-04 12:44:24 +0300145static struct pxa_spi_info spi_info_configs[] = {
146 [PORT_CE4100] = {
147 .type = PXA25x_SSP,
148 .port_id = -1,
149 .num_chipselect = -1,
150 .max_clk_rate = 3686400,
151 },
152 [PORT_BYT] = {
153 .type = LPSS_BYT_SSP,
154 .port_id = 0,
155 .setup = lpss_spi_setup,
156 .tx_param = &byt_tx_param,
157 .rx_param = &byt_rx_param,
158 },
159 [PORT_BSW0] = {
Andy Shevchenkoca80ef72016-07-05 23:12:05 +0300160 .type = LPSS_BSW_SSP,
Andy Shevchenko743485ea2016-07-04 12:44:24 +0300161 .port_id = 0,
162 .setup = lpss_spi_setup,
163 .tx_param = &bsw0_tx_param,
164 .rx_param = &bsw0_rx_param,
165 },
166 [PORT_BSW1] = {
Andy Shevchenkoca80ef72016-07-05 23:12:05 +0300167 .type = LPSS_BSW_SSP,
Andy Shevchenko743485ea2016-07-04 12:44:24 +0300168 .port_id = 1,
169 .setup = lpss_spi_setup,
170 .tx_param = &bsw1_tx_param,
171 .rx_param = &bsw1_rx_param,
172 },
173 [PORT_BSW2] = {
Andy Shevchenkoca80ef72016-07-05 23:12:05 +0300174 .type = LPSS_BSW_SSP,
Andy Shevchenko743485ea2016-07-04 12:44:24 +0300175 .port_id = 2,
176 .setup = lpss_spi_setup,
177 .tx_param = &bsw2_tx_param,
178 .rx_param = &bsw2_rx_param,
179 },
Andy Shevchenko4f470912016-07-04 12:44:25 +0300180 [PORT_MRFLD] = {
181 .type = PXA27x_SSP,
182 .max_clk_rate = 25000000,
183 .setup = mrfld_spi_setup,
184 },
Andy Shevchenko743485ea2016-07-04 12:44:24 +0300185 [PORT_QUARK_X1000] = {
186 .type = QUARK_X1000_SSP,
187 .port_id = -1,
188 .num_chipselect = 1,
189 .max_clk_rate = 50000000,
190 },
Andy Shevchenko54c5d3b2021-02-08 18:38:15 +0200191 [PORT_LPT0] = {
Andy Shevchenko743485ea2016-07-04 12:44:24 +0300192 .type = LPSS_LPT_SSP,
193 .port_id = 0,
194 .setup = lpss_spi_setup,
Andy Shevchenko54c5d3b2021-02-08 18:38:15 +0200195 .tx_param = &lpt0_tx_param,
196 .rx_param = &lpt0_rx_param,
197 },
198 [PORT_LPT1] = {
199 .type = LPSS_LPT_SSP,
200 .port_id = 1,
201 .setup = lpss_spi_setup,
202 .tx_param = &lpt1_tx_param,
203 .rx_param = &lpt1_rx_param,
Andy Shevchenko743485ea2016-07-04 12:44:24 +0300204 },
205};
206
207static int pxa2xx_spi_pci_probe(struct pci_dev *dev,
208 const struct pci_device_id *ent)
209{
210 struct platform_device_info pi;
211 int ret;
212 struct platform_device *pdev;
Lubomir Rintel51eea522019-01-16 16:13:31 +0100213 struct pxa2xx_spi_controller spi_pdata;
Andy Shevchenko743485ea2016-07-04 12:44:24 +0300214 struct ssp_device *ssp;
215 struct pxa_spi_info *c;
216 char buf[40];
217
218 ret = pcim_enable_device(dev);
219 if (ret)
220 return ret;
221
222 ret = pcim_iomap_regions(dev, 1 << 0, "PXA2xx SPI");
223 if (ret)
224 return ret;
225
226 c = &spi_info_configs[ent->driver_data];
227 if (c->setup) {
228 ret = c->setup(dev, c);
229 if (ret)
230 return ret;
231 }
232
233 memset(&spi_pdata, 0, sizeof(spi_pdata));
234 spi_pdata.num_chipselect = (c->num_chipselect > 0) ? c->num_chipselect : dev->devfn;
235 spi_pdata.dma_filter = c->dma_filter;
Mika Westerbergb729bf32014-08-19 20:29:19 +0300236 spi_pdata.tx_param = c->tx_param;
237 spi_pdata.rx_param = c->rx_param;
238 spi_pdata.enable_dma = c->rx_param && c->tx_param;
Andy Shevchenko37821a822019-03-19 17:48:42 +0200239 spi_pdata.dma_burst_size = c->dma_burst_size ? c->dma_burst_size : 1;
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +0100240
Mika Westerberg851bacf2013-01-07 12:44:33 +0200241 ssp = &spi_pdata.ssp;
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +0100242 ssp->phys_base = pci_resource_start(dev, 0);
Mika Westerberg02027752013-01-07 12:44:32 +0200243 ssp->mmio_base = pcim_iomap_table(dev)[0];
Chew, Chiau Eed6ba32d2014-04-18 00:26:06 +0800244 ssp->port_id = (c->port_id >= 0) ? c->port_id : dev->devfn;
245 ssp->type = c->type;
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +0100246
Jan Kiszka64e02cb2017-01-21 10:06:39 +0100247 pci_set_master(dev);
248
249 ret = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
250 if (ret < 0)
251 return ret;
252 ssp->irq = pci_irq_vector(dev, 0);
253
Chew, Chiau Eeafa93c92014-07-25 01:10:54 +0800254 snprintf(buf, sizeof(buf), "pxa2xx-spi.%d", ssp->port_id);
Stephen Boyd280af2b2016-04-19 18:10:07 -0700255 ssp->clk = clk_register_fixed_rate(&dev->dev, buf , NULL, 0,
256 c->max_clk_rate);
Chew, Chiau Eeafa93c92014-07-25 01:10:54 +0800257 if (IS_ERR(ssp->clk))
258 return PTR_ERR(ssp->clk);
259
Mika Westerberg02027752013-01-07 12:44:32 +0200260 memset(&pi, 0, sizeof(pi));
Andy Shevchenkob70cd2d2016-08-24 14:11:30 +0300261 pi.fwnode = dev->dev.fwnode;
Mika Westerberg02027752013-01-07 12:44:32 +0200262 pi.parent = &dev->dev;
263 pi.name = "pxa2xx-spi";
264 pi.id = ssp->port_id;
265 pi.data = &spi_pdata;
266 pi.size_data = sizeof(spi_pdata);
267
268 pdev = platform_device_register_full(&pi);
Chew, Chiau Eeafa93c92014-07-25 01:10:54 +0800269 if (IS_ERR(pdev)) {
270 clk_unregister(ssp->clk);
Wei Yongjund77b5382013-02-22 10:52:35 +0800271 return PTR_ERR(pdev);
Chew, Chiau Eeafa93c92014-07-25 01:10:54 +0800272 }
Mika Westerberg02027752013-01-07 12:44:32 +0200273
Mika Westerberg851bacf2013-01-07 12:44:33 +0200274 pci_set_drvdata(dev, pdev);
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +0100275
Mika Westerberg02027752013-01-07 12:44:32 +0200276 return 0;
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +0100277}
278
Chew, Chiau Eed6ba32d2014-04-18 00:26:06 +0800279static void pxa2xx_spi_pci_remove(struct pci_dev *dev)
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +0100280{
Mika Westerberg851bacf2013-01-07 12:44:33 +0200281 struct platform_device *pdev = pci_get_drvdata(dev);
Lubomir Rintel51eea522019-01-16 16:13:31 +0100282 struct pxa2xx_spi_controller *spi_pdata;
Chew, Chiau Eeafa93c92014-07-25 01:10:54 +0800283
284 spi_pdata = dev_get_platdata(&pdev->dev);
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +0100285
Mika Westerberg851bacf2013-01-07 12:44:33 +0200286 platform_device_unregister(pdev);
Chew, Chiau Eeafa93c92014-07-25 01:10:54 +0800287 clk_unregister(spi_pdata->ssp.clk);
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +0100288}
289
Chew, Chiau Eed6ba32d2014-04-18 00:26:06 +0800290static const struct pci_device_id pxa2xx_spi_pci_devices[] = {
Weike Chene5262d02014-11-26 02:35:10 -0800291 { PCI_VDEVICE(INTEL, 0x0935), PORT_QUARK_X1000 },
Chew, Chiau Eed6ba32d2014-04-18 00:26:06 +0800292 { PCI_VDEVICE(INTEL, 0x0f0e), PORT_BYT },
Andy Shevchenko4f470912016-07-04 12:44:25 +0300293 { PCI_VDEVICE(INTEL, 0x1194), PORT_MRFLD },
Mika Westerberg39d36532014-08-19 20:29:21 +0300294 { PCI_VDEVICE(INTEL, 0x228e), PORT_BSW0 },
295 { PCI_VDEVICE(INTEL, 0x2290), PORT_BSW1 },
296 { PCI_VDEVICE(INTEL, 0x22ac), PORT_BSW2 },
Andy Shevchenkoe379d2c2016-07-04 12:44:27 +0300297 { PCI_VDEVICE(INTEL, 0x2e6a), PORT_CE4100 },
Andy Shevchenko23951832021-02-08 18:38:16 +0200298 { PCI_VDEVICE(INTEL, 0x9c65), PORT_LPT0 },
299 { PCI_VDEVICE(INTEL, 0x9c66), PORT_LPT1 },
Andy Shevchenko54c5d3b2021-02-08 18:38:15 +0200300 { PCI_VDEVICE(INTEL, 0x9ce5), PORT_LPT0 },
301 { PCI_VDEVICE(INTEL, 0x9ce6), PORT_LPT1 },
302 { }
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +0100303};
Chew, Chiau Eed6ba32d2014-04-18 00:26:06 +0800304MODULE_DEVICE_TABLE(pci, pxa2xx_spi_pci_devices);
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +0100305
Chew, Chiau Eed6ba32d2014-04-18 00:26:06 +0800306static struct pci_driver pxa2xx_spi_pci_driver = {
307 .name = "pxa2xx_spi_pci",
308 .id_table = pxa2xx_spi_pci_devices,
309 .probe = pxa2xx_spi_pci_probe,
310 .remove = pxa2xx_spi_pci_remove,
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +0100311};
312
Chew, Chiau Eed6ba32d2014-04-18 00:26:06 +0800313module_pci_driver(pxa2xx_spi_pci_driver);
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +0100314
Chew, Chiau Eed6ba32d2014-04-18 00:26:06 +0800315MODULE_DESCRIPTION("CE4100/LPSS PCI-SPI glue code for PXA's driver");
Sebastian Andrzej Siewiord6ea3df2010-11-24 10:17:14 +0100316MODULE_LICENSE("GPL v2");
317MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>");