Blame - drivers/pci/pcie/Kconfig - SHIFTPHONES/mainline/linux

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Bjorn Helgaas	7328c8f	2018-01-26 11:45:16 -0600	[diff] [blame]	1	# SPDX-License-Identifier: GPL-2.0
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	2	#
				3	# PCI Express Port Bus Configuration
				4	#
				5	config PCIEPORTBUS
Ezequiel Garcia	d47af0b	2013-07-04 17:45:20 -0300	[diff] [blame]	6	bool "PCI Express Port Bus support"
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	7	help
Hou Zhiqiang	8f55ed3	2019-03-06 06:09:46 +0000	[diff] [blame]	8	This enables PCI Express Port Bus support. Users can then enable
				9	support for Native Hot-Plug, Advanced Error Reporting, Power
				10	Management Events, and Downstream Port Containment.
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	11
				12	#
				13	# Include service Kconfig here
				14	#
				15	config HOTPLUG_PCI_PCIE
Bjorn Helgaas	c10cc48	2013-07-23 10:55:56 -0600	[diff] [blame]	16	bool "PCI Express Hotplug driver"
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	17	depends on HOTPLUG_PCI && PCIEPORTBUS
				18	help
				19	Say Y here if you have a motherboard that supports PCI Express Native
				20	Hotplug
				21
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	22	When in doubt, say N.
				23
Bjorn Helgaas	4696b82	2018-06-08 08:48:47 -0500	[diff] [blame]	24	config PCIEAER
Bjorn Helgaas	0b15f1e	2018-06-08 08:48:55 -0500	[diff] [blame]	25	bool "PCI Express Advanced Error Reporting support"
Bjorn Helgaas	4696b82	2018-06-08 08:48:47 -0500	[diff] [blame]	26	depends on PCIEPORTBUS
				27	select RAS
Bjorn Helgaas	4696b82	2018-06-08 08:48:47 -0500	[diff] [blame]	28	help
				29	This enables PCI Express Root Port Advanced Error Reporting
				30	(AER) driver support. Error reporting messages sent to Root
				31	Port will be handled by PCI Express AER driver.
				32
				33	config PCIEAER_INJECT
Bjorn Helgaas	0b15f1e	2018-06-08 08:48:55 -0500	[diff] [blame]	34	tristate "PCI Express error injection support"
Bjorn Helgaas	4696b82	2018-06-08 08:48:47 -0500	[diff] [blame]	35	depends on PCIEAER
Thomas Gleixner	9ae0522	2020-03-06 14:03:48 +0100	[diff] [blame]	36	select GENERIC_IRQ_INJECTION
Bjorn Helgaas	4696b82	2018-06-08 08:48:47 -0500	[diff] [blame]	37	help
				38	This enables PCI Express Root Port Advanced Error Reporting
				39	(AER) software error injector.
				40
Bjorn Helgaas	0b15f1e	2018-06-08 08:48:55 -0500	[diff] [blame]	41	Debugging AER code is quite difficult because it is hard
				42	to trigger various real hardware errors. Software-based
Bjorn Helgaas	4696b82	2018-06-08 08:48:47 -0500	[diff] [blame]	43	error injection can fake almost all kinds of errors with the
				44	help of a user space helper tool aer-inject, which can be
				45	gotten from:
Alexander A. Klimov	7ecd4a8	2020-06-27 12:30:50 +0200	[diff] [blame]	46	https://www.kernel.org/pub/linux/utils/pci/aer-inject/
Bjorn Helgaas	4696b82	2018-06-08 08:48:47 -0500	[diff] [blame]	47
				48	#
				49	# PCI Express ECRC
				50	#
				51	config PCIE_ECRC
				52	bool "PCI Express ECRC settings control"
				53	depends on PCIEAER
				54	help
				55	Used to override firmware/bios settings for PCI Express ECRC
				56	(transaction layer end-to-end CRC checking).
				57
				58	When in doubt, say N.
Shaohua Li	7d715a6	2008-02-25 09:46:41 +0800	[diff] [blame]	59
				60	#
				61	# PCI Express ASPM
				62	#
				63	config PCIEASPM
David Rientjes	6a108a1	2011-01-20 14:44:16 -0800	[diff] [blame]	64	bool "PCI Express ASPM control" if EXPERT
Matthew Garrett	ea5f9fc	2010-06-22 17:03:03 -0400	[diff] [blame]	65	default y
Shaohua Li	7d715a6	2008-02-25 09:46:41 +0800	[diff] [blame]	66	help
Matthew Garrett	ea5f9fc	2010-06-22 17:03:03 -0400	[diff] [blame]	67	This enables OS control over PCI Express ASPM (Active State
				68	Power Management) and Clock Power Management. ASPM supports
				69	state L0/L0s/L1.
Shaohua Li	7d715a6	2008-02-25 09:46:41 +0800	[diff] [blame]	70
P. Christeas	d56641c	2011-12-06 20:48:35 +0200	[diff] [blame]	71	ASPM is initially set up by the firmware. With this option enabled,
Matthew Garrett	ea5f9fc	2010-06-22 17:03:03 -0400	[diff] [blame]	72	Linux can modify this state in order to disable ASPM on known-bad
				73	hardware or configurations and enable it when known-safe.
				74
				75	ASPM can be disabled or enabled at runtime via
				76	/sys/module/pcie_aspm/parameters/policy
				77
				78	When in doubt, say Y.
Andreas Ziegler	cc73176	2016-03-15 12:28:32 +0100	[diff] [blame]	79
Matthew Garrett	ad71c96	2012-02-03 10:18:13 -0500	[diff] [blame]	80	choice
				81	prompt "Default ASPM policy"
				82	default PCIEASPM_DEFAULT
				83	depends on PCIEASPM
				84
				85	config PCIEASPM_DEFAULT
Andreas Ziegler	cc73176	2016-03-15 12:28:32 +0100	[diff] [blame]	86	bool "BIOS default"
Matthew Garrett	ad71c96	2012-02-03 10:18:13 -0500	[diff] [blame]	87	depends on PCIEASPM
				88	help
				89	Use the BIOS defaults for PCI Express ASPM.
				90
				91	config PCIEASPM_POWERSAVE
Andreas Ziegler	cc73176	2016-03-15 12:28:32 +0100	[diff] [blame]	92	bool "Powersave"
Matthew Garrett	ad71c96	2012-02-03 10:18:13 -0500	[diff] [blame]	93	depends on PCIEASPM
				94	help
				95	Enable PCI Express ASPM L0s and L1 where possible, even if the
				96	BIOS did not.
				97
Rajat Jain	b2103cc	2017-01-02 22:34:11 -0800	[diff] [blame]	98	config PCIEASPM_POWER_SUPERSAVE
				99	bool "Power Supersave"
				100	depends on PCIEASPM
				101	help
				102	Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where
				103	possible. This would result in higher power savings while staying in L1
				104	where the components support it.
				105
Matthew Garrett	ad71c96	2012-02-03 10:18:13 -0500	[diff] [blame]	106	config PCIEASPM_PERFORMANCE
Andreas Ziegler	cc73176	2016-03-15 12:28:32 +0100	[diff] [blame]	107	bool "Performance"
Matthew Garrett	ad71c96	2012-02-03 10:18:13 -0500	[diff] [blame]	108	depends on PCIEASPM
				109	help
				110	Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
				111	endchoice
				112
Rafael J. Wysocki	c7f4865	2010-02-17 23:39:08 +0100	[diff] [blame]	113	config PCIE_PME
				114	def_bool y
Rafael J. Wysocki	fbb988b	2014-11-27 23:16:57 +0100	[diff] [blame]	115	depends on PCIEPORTBUS && PM
Keith Busch	26e5157	2016-04-28 16:24:48 -0600	[diff] [blame]	116
				117	config PCIE_DPC
Bjorn Helgaas	0b15f1e	2018-06-08 08:48:55 -0500	[diff] [blame]	118	bool "PCI Express Downstream Port Containment support"
Keith Busch	eed85ff	2018-01-24 17:03:18 -0600	[diff] [blame]	119	depends on PCIEPORTBUS && PCIEAER
Keith Busch	26e5157	2016-04-28 16:24:48 -0600	[diff] [blame]	120	help
				121	This enables PCI Express Downstream Port Containment (DPC)
				122	driver support. DPC events from Root and Downstream ports
				123	will be handled by the DPC driver. If your system doesn't
				124	have this capability or you do not want to use this feature,
				125	it is safe to answer N.
Jonathan Yong	9bb04a0	2016-06-11 14:13:38 -0500	[diff] [blame]	126
				127	config PCIE_PTM
Bjorn Helgaas	0b15f1e	2018-06-08 08:48:55 -0500	[diff] [blame]	128	bool "PCI Express Precision Time Measurement support"
Jonathan Yong	9bb04a0	2016-06-11 14:13:38 -0500	[diff] [blame]	129	help
				130	This enables PCI Express Precision Time Measurement (PTM)
				131	support.
				132
				133	This is only useful if you have devices that support PTM, but it
				134	is safe to enable even if you don't.
Keith Busch	2078e1e	2019-05-01 08:29:42 -0600	[diff] [blame]	135
Kuppuswamy Sathyanarayanan	ac1c8e3	2020-03-23 17:26:07 -0700	[diff] [blame]	136	config PCIE_EDR
				137	bool "PCI Express Error Disconnect Recover support"
				138	depends on PCIE_DPC && ACPI
				139	help
				140	This option adds Error Disconnect Recover support as specified
				141	in the Downstream Port Containment Related Enhancements ECN to
				142	the PCI Firmware Specification r3.2. Enable this if you want to
				143	support hybrid DPC model which uses both firmware and OS to
				144	implement DPC.