blob: ceacd9675044bcbcb866c6f7754e4234ac208cb4 [file] [log] [blame]
Greg Kroah-Hartmane3b3d0f2017-11-06 18:11:51 +01001// SPDX-License-Identifier: GPL-2.0
Jovi Zhang99edb3d2011-03-30 05:30:41 -04002/*
Ben Dooksb4975492008-07-03 12:32:51 +01003 * Driver core for Samsung SoC onboard UARTs.
4 *
Ben Dooksccae9412009-11-13 22:54:14 +00005 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
Ben Dooksb4975492008-07-03 12:32:51 +01006 * http://armlinux.simtec.co.uk/
Ben Dooksb4975492008-07-03 12:32:51 +01007*/
8
9/* Hote on 2410 error handling
10 *
11 * The s3c2410 manual has a love/hate affair with the contents of the
12 * UERSTAT register in the UART blocks, and keeps marking some of the
13 * error bits as reserved. Having checked with the s3c2410x01,
14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
15 * feature from the latter versions of the manual.
16 *
17 * If it becomes aparrent that latter versions of the 2410 remove these
18 * bits, then action will have to be taken to differentiate the versions
19 * and change the policy on BREAK
20 *
21 * BJD, 04-Nov-2004
22*/
23
24#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25#define SUPPORT_SYSRQ
26#endif
27
Robert Baldyga62c37ee2014-12-10 12:49:25 +010028#include <linux/dmaengine.h>
29#include <linux/dma-mapping.h>
30#include <linux/slab.h>
Ben Dooksb4975492008-07-03 12:32:51 +010031#include <linux/module.h>
32#include <linux/ioport.h>
33#include <linux/io.h>
34#include <linux/platform_device.h>
35#include <linux/init.h>
36#include <linux/sysrq.h>
37#include <linux/console.h>
38#include <linux/tty.h>
39#include <linux/tty_flip.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
Arnd Bergmann9ee51f02013-04-11 02:04:48 +020042#include <linux/serial_s3c.h>
Ben Dooksb4975492008-07-03 12:32:51 +010043#include <linux/delay.h>
44#include <linux/clk.h>
Ben Dooks30555472008-10-21 14:06:36 +010045#include <linux/cpufreq.h>
Thomas Abraham26c919e2011-11-06 22:10:44 +053046#include <linux/of.h>
Ben Dooksb4975492008-07-03 12:32:51 +010047#include <asm/irq.h>
48
Joe Perchese4ac92d2014-05-20 14:05:50 -070049#if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
Joe Perchese4ac92d2014-05-20 14:05:50 -070050 !defined(MODULE)
51
52extern void printascii(const char *);
53
54__printf(1, 2)
55static void dbg(const char *fmt, ...)
56{
57 va_list va;
58 char buff[256];
59
60 va_start(va, fmt);
Sachin Kamata859c8b2014-06-03 11:56:25 +053061 vscnprintf(buff, sizeof(buff), fmt, va);
Joe Perchese4ac92d2014-05-20 14:05:50 -070062 va_end(va);
63
64 printascii(buff);
65}
66
67#else
68#define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
69#endif
70
Ben Dooksb4975492008-07-03 12:32:51 +010071/* UART name and device definitions */
72
73#define S3C24XX_SERIAL_NAME "ttySAC"
74#define S3C24XX_SERIAL_MAJOR 204
75#define S3C24XX_SERIAL_MINOR 64
76
Robert Baldyga29bef792014-12-10 12:49:26 +010077#define S3C24XX_TX_PIO 1
78#define S3C24XX_TX_DMA 2
Robert Baldygab543c302014-12-10 12:49:27 +010079#define S3C24XX_RX_PIO 1
80#define S3C24XX_RX_DMA 2
Ben Dooksb4975492008-07-03 12:32:51 +010081/* macros to change one thing to another */
82
83#define tx_enabled(port) ((port)->unused[0])
84#define rx_enabled(port) ((port)->unused[1])
85
Lucas De Marchi25985ed2011-03-30 22:57:33 -030086/* flag to ignore all characters coming in */
Ben Dooksb4975492008-07-03 12:32:51 +010087#define RXSTAT_DUMMY_READ (0x10000000)
88
Greg Kroah-Hartman43df1702019-12-10 15:37:01 +010089struct s3c24xx_uart_info {
90 char *name;
91 unsigned int type;
92 unsigned int fifosize;
93 unsigned long rx_fifomask;
94 unsigned long rx_fifoshift;
95 unsigned long rx_fifofull;
96 unsigned long tx_fifomask;
97 unsigned long tx_fifoshift;
98 unsigned long tx_fifofull;
99 unsigned int def_clk_sel;
100 unsigned long num_clks;
101 unsigned long clksel_mask;
102 unsigned long clksel_shift;
103
104 /* uart port features */
105
106 unsigned int has_divslot:1;
107};
108
109struct s3c24xx_serial_drv_data {
110 struct s3c24xx_uart_info *info;
111 struct s3c2410_uartcfg *def_cfg;
112 unsigned int fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
113};
114
115struct s3c24xx_uart_dma {
116 unsigned int rx_chan_id;
117 unsigned int tx_chan_id;
118
119 struct dma_slave_config rx_conf;
120 struct dma_slave_config tx_conf;
121
122 struct dma_chan *rx_chan;
123 struct dma_chan *tx_chan;
124
125 dma_addr_t rx_addr;
126 dma_addr_t tx_addr;
127
128 dma_cookie_t rx_cookie;
129 dma_cookie_t tx_cookie;
130
131 char *rx_buf;
132
133 dma_addr_t tx_transfer_addr;
134
135 size_t rx_size;
136 size_t tx_size;
137
138 struct dma_async_tx_descriptor *tx_desc;
139 struct dma_async_tx_descriptor *rx_desc;
140
141 int tx_bytes_requested;
142 int rx_bytes_requested;
143};
144
145struct s3c24xx_uart_port {
146 unsigned char rx_claimed;
147 unsigned char tx_claimed;
148 unsigned int pm_level;
149 unsigned long baudclk_rate;
150 unsigned int min_dma_size;
151
152 unsigned int rx_irq;
153 unsigned int tx_irq;
154
155 unsigned int tx_in_progress;
156 unsigned int tx_mode;
157 unsigned int rx_mode;
158
159 struct s3c24xx_uart_info *info;
160 struct clk *clk;
161 struct clk *baudclk;
162 struct uart_port port;
163 struct s3c24xx_serial_drv_data *drv_data;
164
165 /* reference to platform data */
166 struct s3c2410_uartcfg *cfg;
167
168 struct s3c24xx_uart_dma *dma;
169
170#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
171 struct notifier_block freq_transition;
172#endif
173};
174
175/* conversion functions */
176
177#define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
178
179/* register access controls */
180
181#define portaddr(port, reg) ((port)->membase + (reg))
182#define portaddrl(port, reg) \
183 ((unsigned long *)(unsigned long)((port)->membase + (reg)))
184
185#define rd_regb(port, reg) (readb_relaxed(portaddr(port, reg)))
186#define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
187
188#define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg))
189#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
190
191/* Byte-order aware bit setting/clearing functions. */
192
193static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
194 unsigned int reg)
195{
196 unsigned long flags;
197 u32 val;
198
199 local_irq_save(flags);
200 val = rd_regl(port, reg);
201 val |= (1 << idx);
202 wr_regl(port, reg, val);
203 local_irq_restore(flags);
204}
205
206static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
207 unsigned int reg)
208{
209 unsigned long flags;
210 u32 val;
211
212 local_irq_save(flags);
213 val = rd_regl(port, reg);
214 val &= ~(1 << idx);
215 wr_regl(port, reg, val);
216 local_irq_restore(flags);
217}
218
Ben Dooksb4975492008-07-03 12:32:51 +0100219static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
220{
221 return container_of(port, struct s3c24xx_uart_port, port);
222}
223
224/* translate a port to the device name */
225
226static inline const char *s3c24xx_serial_portname(struct uart_port *port)
227{
228 return to_platform_device(port->dev)->name;
229}
230
231static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
232{
Sachin Kamat9303ac12012-09-05 10:30:11 +0530233 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
Ben Dooksb4975492008-07-03 12:32:51 +0100234}
235
Thomas Abraham88bb4ea2011-08-10 15:51:19 +0530236/*
237 * s3c64xx and later SoC's include the interrupt mask and status registers in
238 * the controller itself, unlike the s3c24xx SoC's which have these registers
239 * in the interrupt controller. Check if the port type is s3c64xx or higher.
240 */
241static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
242{
243 return to_ourport(port)->info->type == PORT_S3C6400;
244}
245
Ben Dooksb4975492008-07-03 12:32:51 +0100246static void s3c24xx_serial_rx_enable(struct uart_port *port)
247{
248 unsigned long flags;
249 unsigned int ucon, ufcon;
250 int count = 10000;
251
252 spin_lock_irqsave(&port->lock, flags);
253
254 while (--count && !s3c24xx_serial_txempty_nofifo(port))
255 udelay(100);
256
257 ufcon = rd_regl(port, S3C2410_UFCON);
258 ufcon |= S3C2410_UFCON_RESETRX;
259 wr_regl(port, S3C2410_UFCON, ufcon);
260
261 ucon = rd_regl(port, S3C2410_UCON);
262 ucon |= S3C2410_UCON_RXIRQMODE;
263 wr_regl(port, S3C2410_UCON, ucon);
264
265 rx_enabled(port) = 1;
266 spin_unlock_irqrestore(&port->lock, flags);
267}
268
269static void s3c24xx_serial_rx_disable(struct uart_port *port)
270{
271 unsigned long flags;
272 unsigned int ucon;
273
274 spin_lock_irqsave(&port->lock, flags);
275
276 ucon = rd_regl(port, S3C2410_UCON);
277 ucon &= ~S3C2410_UCON_RXIRQMODE;
278 wr_regl(port, S3C2410_UCON, ucon);
279
280 rx_enabled(port) = 0;
281 spin_unlock_irqrestore(&port->lock, flags);
282}
283
284static void s3c24xx_serial_stop_tx(struct uart_port *port)
285{
Ben Dooksb73c289c2008-10-21 14:07:04 +0100286 struct s3c24xx_uart_port *ourport = to_ourport(port);
Robert Baldyga29bef792014-12-10 12:49:26 +0100287 struct s3c24xx_uart_dma *dma = ourport->dma;
288 struct circ_buf *xmit = &port->state->xmit;
289 struct dma_tx_state state;
290 int count;
Ben Dooksb73c289c2008-10-21 14:07:04 +0100291
Robert Baldyga29bef792014-12-10 12:49:26 +0100292 if (!tx_enabled(port))
293 return;
294
295 if (s3c24xx_serial_has_interrupt_mask(port))
Matthew Leachbbb5ff92016-06-22 17:57:03 +0100296 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
Robert Baldyga29bef792014-12-10 12:49:26 +0100297 else
298 disable_irq_nosync(ourport->tx_irq);
299
300 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
301 dmaengine_pause(dma->tx_chan);
302 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
303 dmaengine_terminate_all(dma->tx_chan);
304 dma_sync_single_for_cpu(ourport->port.dev,
305 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
306 async_tx_ack(dma->tx_desc);
307 count = dma->tx_bytes_requested - state.residue;
308 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
309 port->icount.tx += count;
Ben Dooksb4975492008-07-03 12:32:51 +0100310 }
Robert Baldyga29bef792014-12-10 12:49:26 +0100311
312 tx_enabled(port) = 0;
313 ourport->tx_in_progress = 0;
314
315 if (port->flags & UPF_CONS_FLOW)
316 s3c24xx_serial_rx_enable(port);
317
318 ourport->tx_mode = 0;
Ben Dooksb4975492008-07-03 12:32:51 +0100319}
320
Robert Baldyga29bef792014-12-10 12:49:26 +0100321static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
322
323static void s3c24xx_serial_tx_dma_complete(void *args)
324{
325 struct s3c24xx_uart_port *ourport = args;
326 struct uart_port *port = &ourport->port;
327 struct circ_buf *xmit = &port->state->xmit;
328 struct s3c24xx_uart_dma *dma = ourport->dma;
329 struct dma_tx_state state;
330 unsigned long flags;
331 int count;
332
333
334 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
335 count = dma->tx_bytes_requested - state.residue;
336 async_tx_ack(dma->tx_desc);
337
338 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
339 dma->tx_size, DMA_TO_DEVICE);
340
341 spin_lock_irqsave(&port->lock, flags);
342
343 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
344 port->icount.tx += count;
345 ourport->tx_in_progress = 0;
346
347 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
348 uart_write_wakeup(port);
349
350 s3c24xx_serial_start_next_tx(ourport);
351 spin_unlock_irqrestore(&port->lock, flags);
352}
353
354static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
355{
356 struct uart_port *port = &ourport->port;
357 u32 ucon;
358
359 /* Mask Tx interrupt */
360 if (s3c24xx_serial_has_interrupt_mask(port))
Matthew Leachbbb5ff92016-06-22 17:57:03 +0100361 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
Robert Baldyga29bef792014-12-10 12:49:26 +0100362 else
363 disable_irq_nosync(ourport->tx_irq);
364
365 /* Enable tx dma mode */
366 ucon = rd_regl(port, S3C2410_UCON);
367 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
368 ucon |= (dma_get_cache_alignment() >= 16) ?
369 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
370 ucon |= S3C64XX_UCON_TXMODE_DMA;
371 wr_regl(port, S3C2410_UCON, ucon);
372
373 ourport->tx_mode = S3C24XX_TX_DMA;
374}
375
376static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
377{
378 struct uart_port *port = &ourport->port;
379 u32 ucon, ufcon;
380
381 /* Set ufcon txtrig */
382 ourport->tx_in_progress = S3C24XX_TX_PIO;
383 ufcon = rd_regl(port, S3C2410_UFCON);
384 wr_regl(port, S3C2410_UFCON, ufcon);
385
386 /* Enable tx pio mode */
387 ucon = rd_regl(port, S3C2410_UCON);
388 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
389 ucon |= S3C64XX_UCON_TXMODE_CPU;
390 wr_regl(port, S3C2410_UCON, ucon);
391
392 /* Unmask Tx interrupt */
393 if (s3c24xx_serial_has_interrupt_mask(port))
Matthew Leachbbb5ff92016-06-22 17:57:03 +0100394 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
395 S3C64XX_UINTM);
Robert Baldyga29bef792014-12-10 12:49:26 +0100396 else
397 enable_irq(ourport->tx_irq);
398
399 ourport->tx_mode = S3C24XX_TX_PIO;
400}
401
402static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
403{
404 if (ourport->tx_mode != S3C24XX_TX_PIO)
405 enable_tx_pio(ourport);
406}
407
408static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
409 unsigned int count)
410{
411 struct uart_port *port = &ourport->port;
412 struct circ_buf *xmit = &port->state->xmit;
413 struct s3c24xx_uart_dma *dma = ourport->dma;
414
415
416 if (ourport->tx_mode != S3C24XX_TX_DMA)
417 enable_tx_dma(ourport);
418
Robert Baldyga29bef792014-12-10 12:49:26 +0100419 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
420 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
421
422 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
423 dma->tx_size, DMA_TO_DEVICE);
424
425 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
426 dma->tx_transfer_addr, dma->tx_size,
427 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
428 if (!dma->tx_desc) {
429 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
430 return -EIO;
431 }
432
433 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
434 dma->tx_desc->callback_param = ourport;
435 dma->tx_bytes_requested = dma->tx_size;
436
437 ourport->tx_in_progress = S3C24XX_TX_DMA;
438 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
439 dma_async_issue_pending(dma->tx_chan);
440 return 0;
441}
442
443static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
444{
445 struct uart_port *port = &ourport->port;
446 struct circ_buf *xmit = &port->state->xmit;
447 unsigned long count;
448
449 /* Get data size up to the end of buffer */
450 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
451
452 if (!count) {
453 s3c24xx_serial_stop_tx(port);
454 return;
455 }
456
Marek Szyprowski81ccb2a2015-07-31 10:58:27 +0200457 if (!ourport->dma || !ourport->dma->tx_chan ||
Robert Baldyga736cd792015-07-31 10:58:28 +0200458 count < ourport->min_dma_size ||
459 xmit->tail & (dma_get_cache_alignment() - 1))
Robert Baldyga29bef792014-12-10 12:49:26 +0100460 s3c24xx_serial_start_tx_pio(ourport);
461 else
462 s3c24xx_serial_start_tx_dma(ourport, count);
463}
464
Krzysztof Kozlowski75781972015-05-02 00:40:04 +0900465static void s3c24xx_serial_start_tx(struct uart_port *port)
Ben Dooksb4975492008-07-03 12:32:51 +0100466{
Ben Dooksb73c289c2008-10-21 14:07:04 +0100467 struct s3c24xx_uart_port *ourport = to_ourport(port);
Robert Baldyga29bef792014-12-10 12:49:26 +0100468 struct circ_buf *xmit = &port->state->xmit;
Ben Dooksb73c289c2008-10-21 14:07:04 +0100469
Ben Dooksb4975492008-07-03 12:32:51 +0100470 if (!tx_enabled(port)) {
471 if (port->flags & UPF_CONS_FLOW)
472 s3c24xx_serial_rx_disable(port);
473
Ben Dooksb4975492008-07-03 12:32:51 +0100474 tx_enabled(port) = 1;
Robert Baldygaba019a32015-01-28 14:44:23 +0100475 if (!ourport->dma || !ourport->dma->tx_chan)
Robert Baldyga29bef792014-12-10 12:49:26 +0100476 s3c24xx_serial_start_tx_pio(ourport);
Robert Baldyga29bef792014-12-10 12:49:26 +0100477 }
478
479 if (ourport->dma && ourport->dma->tx_chan) {
480 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
481 s3c24xx_serial_start_next_tx(ourport);
Ben Dooksb4975492008-07-03 12:32:51 +0100482 }
483}
484
Robert Baldygab543c302014-12-10 12:49:27 +0100485static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
486 struct tty_port *tty, int count)
487{
488 struct s3c24xx_uart_dma *dma = ourport->dma;
489 int copied;
490
491 if (!count)
492 return;
493
494 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
495 dma->rx_size, DMA_FROM_DEVICE);
496
497 ourport->port.icount.rx += count;
498 if (!tty) {
499 dev_err(ourport->port.dev, "No tty port\n");
500 return;
501 }
502 copied = tty_insert_flip_string(tty,
503 ((unsigned char *)(ourport->dma->rx_buf)), count);
504 if (copied != count) {
505 WARN_ON(1);
506 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
507 }
508}
509
Ben Dooksb4975492008-07-03 12:32:51 +0100510static void s3c24xx_serial_stop_rx(struct uart_port *port)
511{
Ben Dooksb73c289c2008-10-21 14:07:04 +0100512 struct s3c24xx_uart_port *ourport = to_ourport(port);
Robert Baldygab543c302014-12-10 12:49:27 +0100513 struct s3c24xx_uart_dma *dma = ourport->dma;
514 struct tty_port *t = &port->state->port;
515 struct dma_tx_state state;
516 enum dma_status dma_status;
517 unsigned int received;
Ben Dooksb73c289c2008-10-21 14:07:04 +0100518
Ben Dooksb4975492008-07-03 12:32:51 +0100519 if (rx_enabled(port)) {
520 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
Thomas Abraham88bb4ea2011-08-10 15:51:19 +0530521 if (s3c24xx_serial_has_interrupt_mask(port))
Matthew Leachbbb5ff92016-06-22 17:57:03 +0100522 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
523 S3C64XX_UINTM);
Thomas Abraham88bb4ea2011-08-10 15:51:19 +0530524 else
525 disable_irq_nosync(ourport->rx_irq);
Ben Dooksb4975492008-07-03 12:32:51 +0100526 rx_enabled(port) = 0;
527 }
Robert Baldygab543c302014-12-10 12:49:27 +0100528 if (dma && dma->rx_chan) {
529 dmaengine_pause(dma->tx_chan);
530 dma_status = dmaengine_tx_status(dma->rx_chan,
531 dma->rx_cookie, &state);
532 if (dma_status == DMA_IN_PROGRESS ||
533 dma_status == DMA_PAUSED) {
534 received = dma->rx_bytes_requested - state.residue;
535 dmaengine_terminate_all(dma->rx_chan);
536 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
537 }
538 }
Ben Dooksb4975492008-07-03 12:32:51 +0100539}
540
Robert Baldygaef4aca72014-11-24 07:56:22 +0100541static inline struct s3c24xx_uart_info
542 *s3c24xx_port_to_info(struct uart_port *port)
Ben Dooksb4975492008-07-03 12:32:51 +0100543{
544 return to_ourport(port)->info;
545}
546
Robert Baldygaef4aca72014-11-24 07:56:22 +0100547static inline struct s3c2410_uartcfg
548 *s3c24xx_port_to_cfg(struct uart_port *port)
Ben Dooksb4975492008-07-03 12:32:51 +0100549{
Thomas Abraham4d84e972011-10-24 11:47:25 +0200550 struct s3c24xx_uart_port *ourport;
551
Ben Dooksb4975492008-07-03 12:32:51 +0100552 if (port->dev == NULL)
553 return NULL;
554
Thomas Abraham4d84e972011-10-24 11:47:25 +0200555 ourport = container_of(port, struct s3c24xx_uart_port, port);
556 return ourport->cfg;
Ben Dooksb4975492008-07-03 12:32:51 +0100557}
558
559static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
560 unsigned long ufstat)
561{
562 struct s3c24xx_uart_info *info = ourport->info;
563
564 if (ufstat & info->rx_fifofull)
Thomas Abrahamda121502011-11-02 19:23:25 +0900565 return ourport->port.fifosize;
Ben Dooksb4975492008-07-03 12:32:51 +0100566
567 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
568}
569
Robert Baldygab543c302014-12-10 12:49:27 +0100570static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
571static void s3c24xx_serial_rx_dma_complete(void *args)
572{
573 struct s3c24xx_uart_port *ourport = args;
574 struct uart_port *port = &ourport->port;
575
576 struct s3c24xx_uart_dma *dma = ourport->dma;
577 struct tty_port *t = &port->state->port;
578 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
579
580 struct dma_tx_state state;
581 unsigned long flags;
582 int received;
583
584 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
585 received = dma->rx_bytes_requested - state.residue;
586 async_tx_ack(dma->rx_desc);
587
588 spin_lock_irqsave(&port->lock, flags);
589
590 if (received)
591 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
592
593 if (tty) {
594 tty_flip_buffer_push(t);
595 tty_kref_put(tty);
596 }
597
598 s3c64xx_start_rx_dma(ourport);
599
600 spin_unlock_irqrestore(&port->lock, flags);
601}
602
603static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
604{
605 struct s3c24xx_uart_dma *dma = ourport->dma;
606
607 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
608 dma->rx_size, DMA_FROM_DEVICE);
609
610 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
611 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
612 DMA_PREP_INTERRUPT);
613 if (!dma->rx_desc) {
614 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
615 return;
616 }
617
618 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
619 dma->rx_desc->callback_param = ourport;
620 dma->rx_bytes_requested = dma->rx_size;
621
622 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
623 dma_async_issue_pending(dma->rx_chan);
624}
Ben Dooksb4975492008-07-03 12:32:51 +0100625
626/* ? - where has parity gone?? */
627#define S3C2410_UERSTAT_PARITY (0x1000)
628
Robert Baldygab543c302014-12-10 12:49:27 +0100629static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
630{
631 struct uart_port *port = &ourport->port;
632 unsigned int ucon;
633
634 /* set Rx mode to DMA mode */
635 ucon = rd_regl(port, S3C2410_UCON);
636 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
637 S3C64XX_UCON_TIMEOUT_MASK |
638 S3C64XX_UCON_EMPTYINT_EN |
639 S3C64XX_UCON_DMASUS_EN |
640 S3C64XX_UCON_TIMEOUT_EN |
641 S3C64XX_UCON_RXMODE_MASK);
642 ucon |= S3C64XX_UCON_RXBURST_16 |
643 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
644 S3C64XX_UCON_EMPTYINT_EN |
645 S3C64XX_UCON_TIMEOUT_EN |
646 S3C64XX_UCON_RXMODE_DMA;
647 wr_regl(port, S3C2410_UCON, ucon);
648
649 ourport->rx_mode = S3C24XX_RX_DMA;
650}
651
652static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
653{
654 struct uart_port *port = &ourport->port;
655 unsigned int ucon;
656
657 /* set Rx mode to DMA mode */
658 ucon = rd_regl(port, S3C2410_UCON);
659 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
660 S3C64XX_UCON_EMPTYINT_EN |
661 S3C64XX_UCON_DMASUS_EN |
662 S3C64XX_UCON_TIMEOUT_EN |
663 S3C64XX_UCON_RXMODE_MASK);
664 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
665 S3C64XX_UCON_TIMEOUT_EN |
666 S3C64XX_UCON_RXMODE_CPU;
667 wr_regl(port, S3C2410_UCON, ucon);
668
669 ourport->rx_mode = S3C24XX_RX_PIO;
670}
671
Robert Baldyga09557c02015-09-15 14:49:00 +0200672static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
673
Robert Baldygae4678af2015-09-15 14:48:57 +0200674static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
Robert Baldygab543c302014-12-10 12:49:27 +0100675{
Chen Wandun98aee0c2019-11-22 20:04:18 +0800676 unsigned int utrstat, received;
Robert Baldygab543c302014-12-10 12:49:27 +0100677 struct s3c24xx_uart_port *ourport = dev_id;
678 struct uart_port *port = &ourport->port;
679 struct s3c24xx_uart_dma *dma = ourport->dma;
680 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
681 struct tty_port *t = &port->state->port;
682 unsigned long flags;
683 struct dma_tx_state state;
684
685 utrstat = rd_regl(port, S3C2410_UTRSTAT);
Chen Wandun98aee0c2019-11-22 20:04:18 +0800686 rd_regl(port, S3C2410_UFSTAT);
Robert Baldygab543c302014-12-10 12:49:27 +0100687
688 spin_lock_irqsave(&port->lock, flags);
689
690 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
691 s3c64xx_start_rx_dma(ourport);
692 if (ourport->rx_mode == S3C24XX_RX_PIO)
693 enable_rx_dma(ourport);
694 goto finish;
695 }
696
697 if (ourport->rx_mode == S3C24XX_RX_DMA) {
698 dmaengine_pause(dma->rx_chan);
699 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
700 dmaengine_terminate_all(dma->rx_chan);
701 received = dma->rx_bytes_requested - state.residue;
702 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
703
704 enable_rx_pio(ourport);
705 }
706
Robert Baldyga09557c02015-09-15 14:49:00 +0200707 s3c24xx_serial_rx_drain_fifo(ourport);
Robert Baldygab543c302014-12-10 12:49:27 +0100708
709 if (tty) {
710 tty_flip_buffer_push(t);
711 tty_kref_put(tty);
712 }
713
714 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
715
716finish:
717 spin_unlock_irqrestore(&port->lock, flags);
718
719 return IRQ_HANDLED;
720}
721
Robert Baldyga01732dd2015-09-15 14:48:59 +0200722static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
Ben Dooksb4975492008-07-03 12:32:51 +0100723{
Ben Dooksb4975492008-07-03 12:32:51 +0100724 struct uart_port *port = &ourport->port;
Ben Dooksb4975492008-07-03 12:32:51 +0100725 unsigned int ufcon, ch, flag, ufstat, uerstat;
Youngmin Namaba06e92016-03-05 19:36:32 +0900726 unsigned int fifocnt = 0;
Robert Baldyga57850a52014-11-24 07:56:24 +0100727 int max_count = port->fifosize;
Ben Dooksb4975492008-07-03 12:32:51 +0100728
729 while (max_count-- > 0) {
Youngmin Namaba06e92016-03-05 19:36:32 +0900730 /*
731 * Receive all characters known to be in FIFO
732 * before reading FIFO level again
733 */
734 if (fifocnt == 0) {
735 ufstat = rd_regl(port, S3C2410_UFSTAT);
736 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
737 if (fifocnt == 0)
738 break;
739 }
740 fifocnt--;
Ben Dooksb4975492008-07-03 12:32:51 +0100741
742 uerstat = rd_regl(port, S3C2410_UERSTAT);
743 ch = rd_regb(port, S3C2410_URXH);
744
745 if (port->flags & UPF_CONS_FLOW) {
746 int txe = s3c24xx_serial_txempty_nofifo(port);
747
748 if (rx_enabled(port)) {
749 if (!txe) {
750 rx_enabled(port) = 0;
751 continue;
752 }
753 } else {
754 if (txe) {
Youngmin Namaba06e92016-03-05 19:36:32 +0900755 ufcon = rd_regl(port, S3C2410_UFCON);
Ben Dooksb4975492008-07-03 12:32:51 +0100756 ufcon |= S3C2410_UFCON_RESETRX;
757 wr_regl(port, S3C2410_UFCON, ufcon);
758 rx_enabled(port) = 1;
Robert Baldyga01732dd2015-09-15 14:48:59 +0200759 return;
Ben Dooksb4975492008-07-03 12:32:51 +0100760 }
761 continue;
762 }
763 }
764
765 /* insert the character into the buffer */
766
767 flag = TTY_NORMAL;
768 port->icount.rx++;
769
770 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
771 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
772 ch, uerstat);
773
774 /* check for break */
775 if (uerstat & S3C2410_UERSTAT_BREAK) {
776 dbg("break!\n");
777 port->icount.brk++;
778 if (uart_handle_break(port))
Robert Baldyga620bb212015-09-15 14:48:58 +0200779 continue; /* Ignore character */
Ben Dooksb4975492008-07-03 12:32:51 +0100780 }
781
782 if (uerstat & S3C2410_UERSTAT_FRAME)
783 port->icount.frame++;
784 if (uerstat & S3C2410_UERSTAT_OVERRUN)
785 port->icount.overrun++;
786
787 uerstat &= port->read_status_mask;
788
789 if (uerstat & S3C2410_UERSTAT_BREAK)
790 flag = TTY_BREAK;
791 else if (uerstat & S3C2410_UERSTAT_PARITY)
792 flag = TTY_PARITY;
793 else if (uerstat & (S3C2410_UERSTAT_FRAME |
794 S3C2410_UERSTAT_OVERRUN))
795 flag = TTY_FRAME;
796 }
797
798 if (uart_handle_sysrq_char(port, ch))
Robert Baldyga620bb212015-09-15 14:48:58 +0200799 continue; /* Ignore character */
Ben Dooksb4975492008-07-03 12:32:51 +0100800
801 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
802 ch, flag);
Ben Dooksb4975492008-07-03 12:32:51 +0100803 }
Viresh Kumarf5693ea2013-08-19 20:14:26 +0530804
Jiri Slaby2e124b42013-01-03 15:53:06 +0100805 tty_flip_buffer_push(&port->state->port);
Robert Baldyga01732dd2015-09-15 14:48:59 +0200806}
Ben Dooksb4975492008-07-03 12:32:51 +0100807
Robert Baldyga01732dd2015-09-15 14:48:59 +0200808static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
809{
810 struct s3c24xx_uart_port *ourport = dev_id;
811 struct uart_port *port = &ourport->port;
812 unsigned long flags;
813
814 spin_lock_irqsave(&port->lock, flags);
815 s3c24xx_serial_rx_drain_fifo(ourport);
816 spin_unlock_irqrestore(&port->lock, flags);
817
Ben Dooksb4975492008-07-03 12:32:51 +0100818 return IRQ_HANDLED;
819}
820
Robert Baldygab543c302014-12-10 12:49:27 +0100821
822static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
823{
824 struct s3c24xx_uart_port *ourport = dev_id;
825
826 if (ourport->dma && ourport->dma->rx_chan)
Robert Baldygae4678af2015-09-15 14:48:57 +0200827 return s3c24xx_serial_rx_chars_dma(dev_id);
828 return s3c24xx_serial_rx_chars_pio(dev_id);
Robert Baldygab543c302014-12-10 12:49:27 +0100829}
830
Ben Dooksb4975492008-07-03 12:32:51 +0100831static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
832{
833 struct s3c24xx_uart_port *ourport = id;
834 struct uart_port *port = &ourport->port;
Alan Coxebd2c8f2009-09-19 13:13:28 -0700835 struct circ_buf *xmit = &port->state->xmit;
Thomas Abrahamc15c3742012-11-22 18:06:28 +0530836 unsigned long flags;
Robert Baldyga736cd792015-07-31 10:58:28 +0200837 int count, dma_count = 0;
Ben Dooksb4975492008-07-03 12:32:51 +0100838
Thomas Abrahamc15c3742012-11-22 18:06:28 +0530839 spin_lock_irqsave(&port->lock, flags);
840
Robert Baldyga29bef792014-12-10 12:49:26 +0100841 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
842
Marek Szyprowski81ccb2a2015-07-31 10:58:27 +0200843 if (ourport->dma && ourport->dma->tx_chan &&
844 count >= ourport->min_dma_size) {
Robert Baldyga736cd792015-07-31 10:58:28 +0200845 int align = dma_get_cache_alignment() -
846 (xmit->tail & (dma_get_cache_alignment() - 1));
847 if (count-align >= ourport->min_dma_size) {
848 dma_count = count-align;
849 count = align;
850 }
Robert Baldyga29bef792014-12-10 12:49:26 +0100851 }
852
Ben Dooksb4975492008-07-03 12:32:51 +0100853 if (port->x_char) {
854 wr_regb(port, S3C2410_UTXH, port->x_char);
855 port->icount.tx++;
856 port->x_char = 0;
857 goto out;
858 }
859
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300860 /* if there isn't anything more to transmit, or the uart is now
Ben Dooksb4975492008-07-03 12:32:51 +0100861 * stopped, disable the uart and exit
862 */
863
864 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
865 s3c24xx_serial_stop_tx(port);
866 goto out;
867 }
868
869 /* try and drain the buffer... */
870
Robert Baldyga736cd792015-07-31 10:58:28 +0200871 if (count > port->fifosize) {
872 count = port->fifosize;
873 dma_count = 0;
874 }
875
876 while (!uart_circ_empty(xmit) && count > 0) {
Ben Dooksb4975492008-07-03 12:32:51 +0100877 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
878 break;
879
880 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
881 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
882 port->icount.tx++;
Robert Baldyga736cd792015-07-31 10:58:28 +0200883 count--;
884 }
885
886 if (!count && dma_count) {
887 s3c24xx_serial_start_tx_dma(ourport, dma_count);
888 goto out;
Ben Dooksb4975492008-07-03 12:32:51 +0100889 }
890
Thomas Abrahamc15c3742012-11-22 18:06:28 +0530891 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
892 spin_unlock(&port->lock);
Ben Dooksb4975492008-07-03 12:32:51 +0100893 uart_write_wakeup(port);
Thomas Abrahamc15c3742012-11-22 18:06:28 +0530894 spin_lock(&port->lock);
895 }
Ben Dooksb4975492008-07-03 12:32:51 +0100896
897 if (uart_circ_empty(xmit))
898 s3c24xx_serial_stop_tx(port);
899
Robert Baldygaef4aca72014-11-24 07:56:22 +0100900out:
Thomas Abrahamc15c3742012-11-22 18:06:28 +0530901 spin_unlock_irqrestore(&port->lock, flags);
Ben Dooksb4975492008-07-03 12:32:51 +0100902 return IRQ_HANDLED;
903}
904
Thomas Abraham88bb4ea2011-08-10 15:51:19 +0530905/* interrupt handler for s3c64xx and later SoC's.*/
906static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
907{
908 struct s3c24xx_uart_port *ourport = id;
909 struct uart_port *port = &ourport->port;
910 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
Thomas Abraham88bb4ea2011-08-10 15:51:19 +0530911 irqreturn_t ret = IRQ_HANDLED;
912
Thomas Abraham88bb4ea2011-08-10 15:51:19 +0530913 if (pend & S3C64XX_UINTM_RXD_MSK) {
914 ret = s3c24xx_serial_rx_chars(irq, id);
915 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
916 }
917 if (pend & S3C64XX_UINTM_TXD_MSK) {
918 ret = s3c24xx_serial_tx_chars(irq, id);
919 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
920 }
Thomas Abraham88bb4ea2011-08-10 15:51:19 +0530921 return ret;
922}
923
Ben Dooksb4975492008-07-03 12:32:51 +0100924static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
925{
926 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
927 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
928 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
929
930 if (ufcon & S3C2410_UFCON_FIFOMODE) {
931 if ((ufstat & info->tx_fifomask) != 0 ||
932 (ufstat & info->tx_fifofull))
933 return 0;
934
935 return 1;
936 }
937
938 return s3c24xx_serial_txempty_nofifo(port);
939}
940
941/* no modem control lines */
942static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
943{
944 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
945
946 if (umstat & S3C2410_UMSTAT_CTS)
947 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
948 else
949 return TIOCM_CAR | TIOCM_DSR;
950}
951
952static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
953{
José Miguel Gonçalves2d1e5a42013-09-18 16:52:49 +0100954 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
955
956 if (mctrl & TIOCM_RTS)
957 umcon |= S3C2410_UMCOM_RTS_LOW;
958 else
959 umcon &= ~S3C2410_UMCOM_RTS_LOW;
960
961 wr_regl(port, S3C2410_UMCON, umcon);
Ben Dooksb4975492008-07-03 12:32:51 +0100962}
963
964static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
965{
966 unsigned long flags;
967 unsigned int ucon;
968
969 spin_lock_irqsave(&port->lock, flags);
970
971 ucon = rd_regl(port, S3C2410_UCON);
972
973 if (break_state)
974 ucon |= S3C2410_UCON_SBREAK;
975 else
976 ucon &= ~S3C2410_UCON_SBREAK;
977
978 wr_regl(port, S3C2410_UCON, ucon);
979
980 spin_unlock_irqrestore(&port->lock, flags);
981}
982
Robert Baldyga62c37ee2014-12-10 12:49:25 +0100983static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
984{
985 struct s3c24xx_uart_dma *dma = p->dma;
Marek Szyprowskid8db8402018-05-17 13:37:14 +0200986 struct dma_slave_caps dma_caps;
987 const char *reason = NULL;
Marek Szyprowski500fcc02017-04-03 08:21:00 +0200988 int ret;
Robert Baldyga62c37ee2014-12-10 12:49:25 +0100989
990 /* Default slave configuration parameters */
991 dma->rx_conf.direction = DMA_DEV_TO_MEM;
992 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
993 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
Marek Szyprowskiaa2f80e2018-05-10 08:41:13 +0200994 dma->rx_conf.src_maxburst = 1;
Robert Baldyga62c37ee2014-12-10 12:49:25 +0100995
996 dma->tx_conf.direction = DMA_MEM_TO_DEV;
997 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
998 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
Marek Szyprowskiaa2f80e2018-05-10 08:41:13 +0200999 dma->tx_conf.dst_maxburst = 1;
Robert Baldyga62c37ee2014-12-10 12:49:25 +01001000
Marek Szyprowskiba3d6f82016-12-16 10:56:53 +01001001 dma->rx_chan = dma_request_chan(p->port.dev, "rx");
Robert Baldyga62c37ee2014-12-10 12:49:25 +01001002
Marek Szyprowskid8db8402018-05-17 13:37:14 +02001003 if (IS_ERR(dma->rx_chan)) {
1004 reason = "DMA RX channel request failed";
1005 ret = PTR_ERR(dma->rx_chan);
1006 goto err_warn;
1007 }
1008
1009 ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1010 if (ret < 0 ||
1011 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1012 reason = "insufficient DMA RX engine capabilities";
1013 ret = -EOPNOTSUPP;
1014 goto err_release_rx;
1015 }
Robert Baldyga62c37ee2014-12-10 12:49:25 +01001016
1017 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1018
Marek Szyprowskiba3d6f82016-12-16 10:56:53 +01001019 dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1020 if (IS_ERR(dma->tx_chan)) {
Marek Szyprowskid8db8402018-05-17 13:37:14 +02001021 reason = "DMA TX channel request failed";
Marek Szyprowski500fcc02017-04-03 08:21:00 +02001022 ret = PTR_ERR(dma->tx_chan);
1023 goto err_release_rx;
Robert Baldyga62c37ee2014-12-10 12:49:25 +01001024 }
1025
Marek Szyprowskid8db8402018-05-17 13:37:14 +02001026 ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1027 if (ret < 0 ||
1028 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1029 reason = "insufficient DMA TX engine capabilities";
1030 ret = -EOPNOTSUPP;
1031 goto err_release_tx;
1032 }
1033
Robert Baldyga62c37ee2014-12-10 12:49:25 +01001034 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1035
1036 /* RX buffer */
1037 dma->rx_size = PAGE_SIZE;
1038
1039 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
Robert Baldyga62c37ee2014-12-10 12:49:25 +01001040 if (!dma->rx_buf) {
Marek Szyprowski500fcc02017-04-03 08:21:00 +02001041 ret = -ENOMEM;
1042 goto err_release_tx;
Robert Baldyga62c37ee2014-12-10 12:49:25 +01001043 }
1044
Marek Szyprowski768d64f2017-04-03 08:20:59 +02001045 dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
Robert Baldyga62c37ee2014-12-10 12:49:25 +01001046 dma->rx_size, DMA_FROM_DEVICE);
Marek Szyprowski500fcc02017-04-03 08:21:00 +02001047 if (dma_mapping_error(p->port.dev, dma->rx_addr)) {
Marek Szyprowskid8db8402018-05-17 13:37:14 +02001048 reason = "DMA mapping error for RX buffer";
Marek Szyprowski500fcc02017-04-03 08:21:00 +02001049 ret = -EIO;
1050 goto err_free_rx;
1051 }
Robert Baldyga62c37ee2014-12-10 12:49:25 +01001052
Robert Baldyga62c37ee2014-12-10 12:49:25 +01001053 /* TX buffer */
Marek Szyprowski768d64f2017-04-03 08:20:59 +02001054 dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
Robert Baldyga62c37ee2014-12-10 12:49:25 +01001055 UART_XMIT_SIZE, DMA_TO_DEVICE);
Marek Szyprowski500fcc02017-04-03 08:21:00 +02001056 if (dma_mapping_error(p->port.dev, dma->tx_addr)) {
Marek Szyprowskid8db8402018-05-17 13:37:14 +02001057 reason = "DMA mapping error for TX buffer";
Marek Szyprowski500fcc02017-04-03 08:21:00 +02001058 ret = -EIO;
1059 goto err_unmap_rx;
1060 }
Robert Baldyga62c37ee2014-12-10 12:49:25 +01001061
1062 return 0;
Marek Szyprowski500fcc02017-04-03 08:21:00 +02001063
1064err_unmap_rx:
1065 dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size,
1066 DMA_FROM_DEVICE);
1067err_free_rx:
1068 kfree(dma->rx_buf);
1069err_release_tx:
1070 dma_release_channel(dma->tx_chan);
1071err_release_rx:
1072 dma_release_channel(dma->rx_chan);
Marek Szyprowskid8db8402018-05-17 13:37:14 +02001073err_warn:
1074 if (reason)
1075 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
Marek Szyprowski500fcc02017-04-03 08:21:00 +02001076 return ret;
Robert Baldyga62c37ee2014-12-10 12:49:25 +01001077}
1078
1079static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1080{
1081 struct s3c24xx_uart_dma *dma = p->dma;
1082
1083 if (dma->rx_chan) {
1084 dmaengine_terminate_all(dma->rx_chan);
Marek Szyprowski768d64f2017-04-03 08:20:59 +02001085 dma_unmap_single(p->port.dev, dma->rx_addr,
Robert Baldyga62c37ee2014-12-10 12:49:25 +01001086 dma->rx_size, DMA_FROM_DEVICE);
1087 kfree(dma->rx_buf);
1088 dma_release_channel(dma->rx_chan);
1089 dma->rx_chan = NULL;
1090 }
1091
1092 if (dma->tx_chan) {
1093 dmaengine_terminate_all(dma->tx_chan);
Marek Szyprowski768d64f2017-04-03 08:20:59 +02001094 dma_unmap_single(p->port.dev, dma->tx_addr,
Robert Baldyga62c37ee2014-12-10 12:49:25 +01001095 UART_XMIT_SIZE, DMA_TO_DEVICE);
1096 dma_release_channel(dma->tx_chan);
1097 dma->tx_chan = NULL;
1098 }
1099}
1100
Ben Dooksb4975492008-07-03 12:32:51 +01001101static void s3c24xx_serial_shutdown(struct uart_port *port)
1102{
1103 struct s3c24xx_uart_port *ourport = to_ourport(port);
1104
1105 if (ourport->tx_claimed) {
Thomas Abraham88bb4ea2011-08-10 15:51:19 +05301106 if (!s3c24xx_serial_has_interrupt_mask(port))
1107 free_irq(ourport->tx_irq, ourport);
Ben Dooksb4975492008-07-03 12:32:51 +01001108 tx_enabled(port) = 0;
1109 ourport->tx_claimed = 0;
Javier Martinez Canillase91d8632015-03-13 12:38:51 +01001110 ourport->tx_mode = 0;
Ben Dooksb4975492008-07-03 12:32:51 +01001111 }
1112
1113 if (ourport->rx_claimed) {
Thomas Abraham88bb4ea2011-08-10 15:51:19 +05301114 if (!s3c24xx_serial_has_interrupt_mask(port))
1115 free_irq(ourport->rx_irq, ourport);
Ben Dooksb4975492008-07-03 12:32:51 +01001116 ourport->rx_claimed = 0;
1117 rx_enabled(port) = 0;
1118 }
Ben Dooksb4975492008-07-03 12:32:51 +01001119
Thomas Abraham88bb4ea2011-08-10 15:51:19 +05301120 /* Clear pending interrupts and mask all interrupts */
1121 if (s3c24xx_serial_has_interrupt_mask(port)) {
Tomasz Figab6ad2932013-03-26 15:57:35 +01001122 free_irq(port->irq, ourport);
1123
Thomas Abraham88bb4ea2011-08-10 15:51:19 +05301124 wr_regl(port, S3C64XX_UINTP, 0xf);
1125 wr_regl(port, S3C64XX_UINTM, 0xf);
1126 }
Robert Baldyga62c37ee2014-12-10 12:49:25 +01001127
1128 if (ourport->dma)
1129 s3c24xx_serial_release_dma(ourport);
1130
Robert Baldyga29bef792014-12-10 12:49:26 +01001131 ourport->tx_in_progress = 0;
Thomas Abraham88bb4ea2011-08-10 15:51:19 +05301132}
Ben Dooksb4975492008-07-03 12:32:51 +01001133
1134static int s3c24xx_serial_startup(struct uart_port *port)
1135{
1136 struct s3c24xx_uart_port *ourport = to_ourport(port);
1137 int ret;
1138
Joe Perchese4ac92d2014-05-20 14:05:50 -07001139 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
1140 port, (unsigned long long)port->mapbase, port->membase);
Ben Dooksb4975492008-07-03 12:32:51 +01001141
1142 rx_enabled(port) = 1;
1143
Ben Dooksb73c289c2008-10-21 14:07:04 +01001144 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
Ben Dooksb4975492008-07-03 12:32:51 +01001145 s3c24xx_serial_portname(port), ourport);
1146
1147 if (ret != 0) {
Sachin Kamatd20925e2012-09-05 10:30:10 +05301148 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
Ben Dooksb4975492008-07-03 12:32:51 +01001149 return ret;
1150 }
1151
1152 ourport->rx_claimed = 1;
1153
1154 dbg("requesting tx irq...\n");
1155
1156 tx_enabled(port) = 1;
1157
Ben Dooksb73c289c2008-10-21 14:07:04 +01001158 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
Ben Dooksb4975492008-07-03 12:32:51 +01001159 s3c24xx_serial_portname(port), ourport);
1160
1161 if (ret) {
Sachin Kamatd20925e2012-09-05 10:30:10 +05301162 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
Ben Dooksb4975492008-07-03 12:32:51 +01001163 goto err;
1164 }
1165
1166 ourport->tx_claimed = 1;
1167
1168 dbg("s3c24xx_serial_startup ok\n");
1169
1170 /* the port reset code should have done the correct
1171 * register setup for the port controls */
1172
1173 return ret;
1174
Robert Baldygaef4aca72014-11-24 07:56:22 +01001175err:
Ben Dooksb4975492008-07-03 12:32:51 +01001176 s3c24xx_serial_shutdown(port);
1177 return ret;
1178}
1179
Thomas Abraham88bb4ea2011-08-10 15:51:19 +05301180static int s3c64xx_serial_startup(struct uart_port *port)
1181{
1182 struct s3c24xx_uart_port *ourport = to_ourport(port);
Robert Baldygab543c302014-12-10 12:49:27 +01001183 unsigned long flags;
1184 unsigned int ufcon;
Thomas Abraham88bb4ea2011-08-10 15:51:19 +05301185 int ret;
1186
Joe Perchese4ac92d2014-05-20 14:05:50 -07001187 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1188 port, (unsigned long long)port->mapbase, port->membase);
Thomas Abraham88bb4ea2011-08-10 15:51:19 +05301189
Tomasz Figab6ad2932013-03-26 15:57:35 +01001190 wr_regl(port, S3C64XX_UINTM, 0xf);
Robert Baldyga62c37ee2014-12-10 12:49:25 +01001191 if (ourport->dma) {
1192 ret = s3c24xx_serial_request_dma(ourport);
1193 if (ret < 0) {
Krzysztof Kozlowskif98c7bc2017-02-25 18:36:44 +02001194 devm_kfree(port->dev, ourport->dma);
1195 ourport->dma = NULL;
Robert Baldyga62c37ee2014-12-10 12:49:25 +01001196 }
1197 }
Tomasz Figab6ad2932013-03-26 15:57:35 +01001198
Thomas Abraham88bb4ea2011-08-10 15:51:19 +05301199 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1200 s3c24xx_serial_portname(port), ourport);
1201 if (ret) {
Sachin Kamatd20925e2012-09-05 10:30:10 +05301202 dev_err(port->dev, "cannot get irq %d\n", port->irq);
Thomas Abraham88bb4ea2011-08-10 15:51:19 +05301203 return ret;
1204 }
1205
1206 /* For compatibility with s3c24xx Soc's */
1207 rx_enabled(port) = 1;
1208 ourport->rx_claimed = 1;
1209 tx_enabled(port) = 0;
1210 ourport->tx_claimed = 1;
1211
Robert Baldyga29bef792014-12-10 12:49:26 +01001212 spin_lock_irqsave(&port->lock, flags);
1213
1214 ufcon = rd_regl(port, S3C2410_UFCON);
Robert Baldyga31c6ba92015-04-17 08:43:09 +02001215 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1216 if (!uart_console(port))
1217 ufcon |= S3C2410_UFCON_RESETTX;
Robert Baldyga29bef792014-12-10 12:49:26 +01001218 wr_regl(port, S3C2410_UFCON, ufcon);
1219
1220 enable_rx_pio(ourport);
1221
1222 spin_unlock_irqrestore(&port->lock, flags);
1223
Thomas Abraham88bb4ea2011-08-10 15:51:19 +05301224 /* Enable Rx Interrupt */
Matthew Leachbbb5ff92016-06-22 17:57:03 +01001225 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
Robert Baldyga29bef792014-12-10 12:49:26 +01001226
Thomas Abraham88bb4ea2011-08-10 15:51:19 +05301227 dbg("s3c64xx_serial_startup ok\n");
1228 return ret;
1229}
1230
Ben Dooksb4975492008-07-03 12:32:51 +01001231/* power power management control */
1232
1233static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1234 unsigned int old)
1235{
1236 struct s3c24xx_uart_port *ourport = to_ourport(port);
Robert Baldyga1ff383a2014-11-24 07:56:21 +01001237 int timeout = 10000;
Ben Dooksb4975492008-07-03 12:32:51 +01001238
Ben Dooks30555472008-10-21 14:06:36 +01001239 ourport->pm_level = level;
1240
Ben Dooksb4975492008-07-03 12:32:51 +01001241 switch (level) {
1242 case 3:
Robert Baldyga1ff383a2014-11-24 07:56:21 +01001243 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1244 udelay(100);
1245
Kyoungil Kim7cd88832012-05-20 17:45:54 +09001246 if (!IS_ERR(ourport->baudclk))
Thomas Abraham9484b002012-10-03 07:40:04 +09001247 clk_disable_unprepare(ourport->baudclk);
Ben Dooksb4975492008-07-03 12:32:51 +01001248
Thomas Abraham9484b002012-10-03 07:40:04 +09001249 clk_disable_unprepare(ourport->clk);
Ben Dooksb4975492008-07-03 12:32:51 +01001250 break;
1251
1252 case 0:
Thomas Abraham9484b002012-10-03 07:40:04 +09001253 clk_prepare_enable(ourport->clk);
Ben Dooksb4975492008-07-03 12:32:51 +01001254
Kyoungil Kim7cd88832012-05-20 17:45:54 +09001255 if (!IS_ERR(ourport->baudclk))
Thomas Abraham9484b002012-10-03 07:40:04 +09001256 clk_prepare_enable(ourport->baudclk);
Ben Dooksb4975492008-07-03 12:32:51 +01001257
1258 break;
1259 default:
Sachin Kamatd20925e2012-09-05 10:30:10 +05301260 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
Ben Dooksb4975492008-07-03 12:32:51 +01001261 }
1262}
1263
1264/* baud rate calculation
1265 *
1266 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1267 * of different sources, including the peripheral clock ("pclk") and an
1268 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1269 * with a programmable extra divisor.
1270 *
1271 * The following code goes through the clock sources, and calculates the
1272 * baud clocks (and the resultant actual baud rates) and then tries to
1273 * pick the closest one and select that.
1274 *
1275*/
1276
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001277#define MAX_CLK_NAME_LENGTH 15
Ben Dooksb4975492008-07-03 12:32:51 +01001278
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001279static inline int s3c24xx_serial_getsource(struct uart_port *port)
Ben Dooksb4975492008-07-03 12:32:51 +01001280{
1281 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001282 unsigned int ucon;
Ben Dooksb4975492008-07-03 12:32:51 +01001283
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001284 if (info->num_clks == 1)
Ben Dooksb4975492008-07-03 12:32:51 +01001285 return 0;
1286
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001287 ucon = rd_regl(port, S3C2410_UCON);
1288 ucon &= info->clksel_mask;
1289 return ucon >> info->clksel_shift;
Ben Dooksb4975492008-07-03 12:32:51 +01001290}
1291
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001292static void s3c24xx_serial_setsource(struct uart_port *port,
1293 unsigned int clk_sel)
Ben Dooksb4975492008-07-03 12:32:51 +01001294{
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001295 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1296 unsigned int ucon;
Ben Dooksb4975492008-07-03 12:32:51 +01001297
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001298 if (info->num_clks == 1)
1299 return;
Ben Dooksb4975492008-07-03 12:32:51 +01001300
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001301 ucon = rd_regl(port, S3C2410_UCON);
1302 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1303 return;
Ben Dooksb4975492008-07-03 12:32:51 +01001304
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001305 ucon &= ~info->clksel_mask;
1306 ucon |= clk_sel << info->clksel_shift;
1307 wr_regl(port, S3C2410_UCON, ucon);
1308}
Ben Dooksb4975492008-07-03 12:32:51 +01001309
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001310static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1311 unsigned int req_baud, struct clk **best_clk,
1312 unsigned int *clk_num)
1313{
1314 struct s3c24xx_uart_info *info = ourport->info;
1315 struct clk *clk;
1316 unsigned long rate;
1317 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1318 char clkname[MAX_CLK_NAME_LENGTH];
1319 int calc_deviation, deviation = (1 << 30) - 1;
1320
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001321 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1322 ourport->info->def_clk_sel;
1323 for (cnt = 0; cnt < info->num_clks; cnt++) {
1324 if (!(clk_sel & (1 << cnt)))
1325 continue;
1326
1327 sprintf(clkname, "clk_uart_baud%d", cnt);
1328 clk = clk_get(ourport->port.dev, clkname);
Kyoungil Kim7cd88832012-05-20 17:45:54 +09001329 if (IS_ERR(clk))
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001330 continue;
1331
1332 rate = clk_get_rate(clk);
1333 if (!rate)
1334 continue;
1335
1336 if (ourport->info->has_divslot) {
1337 unsigned long div = rate / req_baud;
1338
1339 /* The UDIVSLOT register on the newer UARTs allows us to
1340 * get a divisor adjustment of 1/16th on the baud clock.
1341 *
1342 * We don't keep the UDIVSLOT value (the 16ths we
1343 * calculated by not multiplying the baud by 16) as it
1344 * is easy enough to recalculate.
1345 */
1346
1347 quot = div / 16;
1348 baud = rate / div;
1349 } else {
1350 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1351 baud = rate / (quot * 16);
1352 }
1353 quot--;
1354
1355 calc_deviation = req_baud - baud;
1356 if (calc_deviation < 0)
1357 calc_deviation = -calc_deviation;
1358
1359 if (calc_deviation < deviation) {
1360 *best_clk = clk;
1361 best_quot = quot;
1362 *clk_num = cnt;
1363 deviation = calc_deviation;
Ben Dooksb4975492008-07-03 12:32:51 +01001364 }
1365 }
1366
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001367 return best_quot;
Ben Dooksb4975492008-07-03 12:32:51 +01001368}
1369
Ben Dooks090f848d2008-12-12 00:24:21 +00001370/* udivslot_table[]
1371 *
1372 * This table takes the fractional value of the baud divisor and gives
1373 * the recommended setting for the UDIVSLOT register.
1374 */
1375static u16 udivslot_table[16] = {
1376 [0] = 0x0000,
1377 [1] = 0x0080,
1378 [2] = 0x0808,
1379 [3] = 0x0888,
1380 [4] = 0x2222,
1381 [5] = 0x4924,
1382 [6] = 0x4A52,
1383 [7] = 0x54AA,
1384 [8] = 0x5555,
1385 [9] = 0xD555,
1386 [10] = 0xD5D5,
1387 [11] = 0xDDD5,
1388 [12] = 0xDDDD,
1389 [13] = 0xDFDD,
1390 [14] = 0xDFDF,
1391 [15] = 0xFFDF,
1392};
1393
Ben Dooksb4975492008-07-03 12:32:51 +01001394static void s3c24xx_serial_set_termios(struct uart_port *port,
1395 struct ktermios *termios,
1396 struct ktermios *old)
1397{
1398 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1399 struct s3c24xx_uart_port *ourport = to_ourport(port);
Kyoungil Kim7cd88832012-05-20 17:45:54 +09001400 struct clk *clk = ERR_PTR(-EINVAL);
Ben Dooksb4975492008-07-03 12:32:51 +01001401 unsigned long flags;
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001402 unsigned int baud, quot, clk_sel = 0;
Ben Dooksb4975492008-07-03 12:32:51 +01001403 unsigned int ulcon;
1404 unsigned int umcon;
Ben Dooks090f848d2008-12-12 00:24:21 +00001405 unsigned int udivslot = 0;
Ben Dooksb4975492008-07-03 12:32:51 +01001406
1407 /*
1408 * We don't support modem control lines.
1409 */
1410 termios->c_cflag &= ~(HUPCL | CMSPAR);
1411 termios->c_cflag |= CLOCAL;
1412
1413 /*
1414 * Ask the core to calculate the divisor for us.
1415 */
1416
Seung-Woo Kimec18f482018-12-14 12:34:09 +01001417 baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001418 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
Ben Dooksb4975492008-07-03 12:32:51 +01001419 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1420 quot = port->custom_divisor;
Kyoungil Kim7cd88832012-05-20 17:45:54 +09001421 if (IS_ERR(clk))
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001422 return;
Ben Dooksb4975492008-07-03 12:32:51 +01001423
1424 /* check to see if we need to change clock source */
1425
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001426 if (ourport->baudclk != clk) {
Chanwoo Choib8995f52016-04-21 18:58:31 +09001427 clk_prepare_enable(clk);
1428
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02001429 s3c24xx_serial_setsource(port, clk_sel);
Ben Dooksb4975492008-07-03 12:32:51 +01001430
Kyoungil Kim7cd88832012-05-20 17:45:54 +09001431 if (!IS_ERR(ourport->baudclk)) {
Thomas Abraham9484b002012-10-03 07:40:04 +09001432 clk_disable_unprepare(ourport->baudclk);
Kyoungil Kim7cd88832012-05-20 17:45:54 +09001433 ourport->baudclk = ERR_PTR(-EINVAL);
Ben Dooksb4975492008-07-03 12:32:51 +01001434 }
1435
Ben Dooksb4975492008-07-03 12:32:51 +01001436 ourport->baudclk = clk;
Ben Dooks30555472008-10-21 14:06:36 +01001437 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
Ben Dooksb4975492008-07-03 12:32:51 +01001438 }
1439
Ben Dooks090f848d2008-12-12 00:24:21 +00001440 if (ourport->info->has_divslot) {
1441 unsigned int div = ourport->baudclk_rate / baud;
1442
Jongpill Lee8b526ae2010-07-16 10:19:41 +09001443 if (cfg->has_fracval) {
1444 udivslot = (div & 15);
1445 dbg("fracval = %04x\n", udivslot);
1446 } else {
1447 udivslot = udivslot_table[div & 15];
1448 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1449 }
Ben Dooks090f848d2008-12-12 00:24:21 +00001450 }
1451
Ben Dooksb4975492008-07-03 12:32:51 +01001452 switch (termios->c_cflag & CSIZE) {
1453 case CS5:
1454 dbg("config: 5bits/char\n");
1455 ulcon = S3C2410_LCON_CS5;
1456 break;
1457 case CS6:
1458 dbg("config: 6bits/char\n");
1459 ulcon = S3C2410_LCON_CS6;
1460 break;
1461 case CS7:
1462 dbg("config: 7bits/char\n");
1463 ulcon = S3C2410_LCON_CS7;
1464 break;
1465 case CS8:
1466 default:
1467 dbg("config: 8bits/char\n");
1468 ulcon = S3C2410_LCON_CS8;
1469 break;
1470 }
1471
1472 /* preserve original lcon IR settings */
1473 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1474
1475 if (termios->c_cflag & CSTOPB)
1476 ulcon |= S3C2410_LCON_STOPB;
1477
Ben Dooksb4975492008-07-03 12:32:51 +01001478 if (termios->c_cflag & PARENB) {
1479 if (termios->c_cflag & PARODD)
1480 ulcon |= S3C2410_LCON_PODD;
1481 else
1482 ulcon |= S3C2410_LCON_PEVEN;
1483 } else {
1484 ulcon |= S3C2410_LCON_PNONE;
1485 }
1486
1487 spin_lock_irqsave(&port->lock, flags);
1488
Ben Dooks090f848d2008-12-12 00:24:21 +00001489 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1490 ulcon, quot, udivslot);
Ben Dooksb4975492008-07-03 12:32:51 +01001491
1492 wr_regl(port, S3C2410_ULCON, ulcon);
1493 wr_regl(port, S3C2410_UBRDIV, quot);
José Miguel Gonçalves2d1e5a42013-09-18 16:52:49 +01001494
Beomho Seo31e93362018-12-14 12:34:08 +01001495 port->status &= ~UPSTAT_AUTOCTS;
1496
José Miguel Gonçalves2d1e5a42013-09-18 16:52:49 +01001497 umcon = rd_regl(port, S3C2410_UMCON);
1498 if (termios->c_cflag & CRTSCTS) {
1499 umcon |= S3C2410_UMCOM_AFC;
1500 /* Disable RTS when RX FIFO contains 63 bytes */
1501 umcon &= ~S3C2412_UMCON_AFC_8;
Beomho Seo31e93362018-12-14 12:34:08 +01001502 port->status = UPSTAT_AUTOCTS;
José Miguel Gonçalves2d1e5a42013-09-18 16:52:49 +01001503 } else {
1504 umcon &= ~S3C2410_UMCOM_AFC;
1505 }
Ben Dooksb4975492008-07-03 12:32:51 +01001506 wr_regl(port, S3C2410_UMCON, umcon);
1507
Ben Dooks090f848d2008-12-12 00:24:21 +00001508 if (ourport->info->has_divslot)
1509 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1510
Ben Dooksb4975492008-07-03 12:32:51 +01001511 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1512 rd_regl(port, S3C2410_ULCON),
1513 rd_regl(port, S3C2410_UCON),
1514 rd_regl(port, S3C2410_UFCON));
1515
1516 /*
1517 * Update the per-port timeout.
1518 */
1519 uart_update_timeout(port, termios->c_cflag, baud);
1520
1521 /*
1522 * Which character status flags are we interested in?
1523 */
1524 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1525 if (termios->c_iflag & INPCK)
Robert Baldygaef4aca72014-11-24 07:56:22 +01001526 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1527 S3C2410_UERSTAT_PARITY;
Ben Dooksb4975492008-07-03 12:32:51 +01001528 /*
1529 * Which character status flags should we ignore?
1530 */
1531 port->ignore_status_mask = 0;
1532 if (termios->c_iflag & IGNPAR)
1533 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1534 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1535 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1536
1537 /*
1538 * Ignore all characters if CREAD is not set.
1539 */
1540 if ((termios->c_cflag & CREAD) == 0)
1541 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1542
1543 spin_unlock_irqrestore(&port->lock, flags);
1544}
1545
1546static const char *s3c24xx_serial_type(struct uart_port *port)
1547{
1548 switch (port->type) {
1549 case PORT_S3C2410:
1550 return "S3C2410";
1551 case PORT_S3C2440:
1552 return "S3C2440";
1553 case PORT_S3C2412:
1554 return "S3C2412";
Ben Dooksb690ace2008-10-21 14:07:03 +01001555 case PORT_S3C6400:
1556 return "S3C6400/10";
Ben Dooksb4975492008-07-03 12:32:51 +01001557 default:
1558 return NULL;
1559 }
1560}
1561
1562#define MAP_SIZE (0x100)
1563
1564static void s3c24xx_serial_release_port(struct uart_port *port)
1565{
1566 release_mem_region(port->mapbase, MAP_SIZE);
1567}
1568
1569static int s3c24xx_serial_request_port(struct uart_port *port)
1570{
1571 const char *name = s3c24xx_serial_portname(port);
1572 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1573}
1574
1575static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1576{
1577 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1578
1579 if (flags & UART_CONFIG_TYPE &&
1580 s3c24xx_serial_request_port(port) == 0)
1581 port->type = info->type;
1582}
1583
1584/*
1585 * verify the new serial_struct (for TIOCSSERIAL).
1586 */
1587static int
1588s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1589{
1590 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1591
1592 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1593 return -EINVAL;
1594
1595 return 0;
1596}
1597
1598
1599#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1600
1601static struct console s3c24xx_serial_console;
1602
Julien Pichon93b5c032012-09-21 23:22:31 -07001603static int __init s3c24xx_serial_console_init(void)
1604{
1605 register_console(&s3c24xx_serial_console);
1606 return 0;
1607}
1608console_initcall(s3c24xx_serial_console_init);
1609
Ben Dooksb4975492008-07-03 12:32:51 +01001610#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1611#else
1612#define S3C24XX_SERIAL_CONSOLE NULL
1613#endif
1614
Arnd Bergmann84f57d92013-04-11 02:04:49 +02001615#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
Julien Pichon93b5c032012-09-21 23:22:31 -07001616static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1617static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1618 unsigned char c);
1619#endif
1620
Ben Dooksb4975492008-07-03 12:32:51 +01001621static struct uart_ops s3c24xx_serial_ops = {
1622 .pm = s3c24xx_serial_pm,
1623 .tx_empty = s3c24xx_serial_tx_empty,
1624 .get_mctrl = s3c24xx_serial_get_mctrl,
1625 .set_mctrl = s3c24xx_serial_set_mctrl,
1626 .stop_tx = s3c24xx_serial_stop_tx,
1627 .start_tx = s3c24xx_serial_start_tx,
1628 .stop_rx = s3c24xx_serial_stop_rx,
Ben Dooksb4975492008-07-03 12:32:51 +01001629 .break_ctl = s3c24xx_serial_break_ctl,
1630 .startup = s3c24xx_serial_startup,
1631 .shutdown = s3c24xx_serial_shutdown,
1632 .set_termios = s3c24xx_serial_set_termios,
1633 .type = s3c24xx_serial_type,
1634 .release_port = s3c24xx_serial_release_port,
1635 .request_port = s3c24xx_serial_request_port,
1636 .config_port = s3c24xx_serial_config_port,
1637 .verify_port = s3c24xx_serial_verify_port,
Arnd Bergmann84f57d92013-04-11 02:04:49 +02001638#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
Julien Pichon93b5c032012-09-21 23:22:31 -07001639 .poll_get_char = s3c24xx_serial_get_poll_char,
1640 .poll_put_char = s3c24xx_serial_put_poll_char,
1641#endif
Ben Dooksb4975492008-07-03 12:32:51 +01001642};
1643
Ben Dooksb4975492008-07-03 12:32:51 +01001644static struct uart_driver s3c24xx_uart_drv = {
1645 .owner = THIS_MODULE,
Darius Augulis2cf0c582011-01-12 14:50:51 +09001646 .driver_name = "s3c2410_serial",
Ben Dooksbdd49152008-11-03 19:51:42 +00001647 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
Ben Dooksb4975492008-07-03 12:32:51 +01001648 .cons = S3C24XX_SERIAL_CONSOLE,
Darius Augulis2cf0c582011-01-12 14:50:51 +09001649 .dev_name = S3C24XX_SERIAL_NAME,
Ben Dooksb4975492008-07-03 12:32:51 +01001650 .major = S3C24XX_SERIAL_MAJOR,
1651 .minor = S3C24XX_SERIAL_MINOR,
1652};
1653
Robert Baldygaef4aca72014-11-24 07:56:22 +01001654#define __PORT_LOCK_UNLOCKED(i) \
1655 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1656static struct s3c24xx_uart_port
1657s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
Ben Dooksb4975492008-07-03 12:32:51 +01001658 [0] = {
1659 .port = {
Robert Baldygaef4aca72014-11-24 07:56:22 +01001660 .lock = __PORT_LOCK_UNLOCKED(0),
Ben Dooksb4975492008-07-03 12:32:51 +01001661 .iotype = UPIO_MEM,
Ben Dooksb4975492008-07-03 12:32:51 +01001662 .uartclk = 0,
1663 .fifosize = 16,
1664 .ops = &s3c24xx_serial_ops,
1665 .flags = UPF_BOOT_AUTOCONF,
1666 .line = 0,
1667 }
1668 },
1669 [1] = {
1670 .port = {
Robert Baldygaef4aca72014-11-24 07:56:22 +01001671 .lock = __PORT_LOCK_UNLOCKED(1),
Ben Dooksb4975492008-07-03 12:32:51 +01001672 .iotype = UPIO_MEM,
Ben Dooksb4975492008-07-03 12:32:51 +01001673 .uartclk = 0,
1674 .fifosize = 16,
1675 .ops = &s3c24xx_serial_ops,
1676 .flags = UPF_BOOT_AUTOCONF,
1677 .line = 1,
1678 }
1679 },
Ben Dooks03d5e772008-11-03 09:21:23 +00001680#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
Ben Dooksb4975492008-07-03 12:32:51 +01001681
1682 [2] = {
1683 .port = {
Robert Baldygaef4aca72014-11-24 07:56:22 +01001684 .lock = __PORT_LOCK_UNLOCKED(2),
Ben Dooksb4975492008-07-03 12:32:51 +01001685 .iotype = UPIO_MEM,
Ben Dooksb4975492008-07-03 12:32:51 +01001686 .uartclk = 0,
1687 .fifosize = 16,
1688 .ops = &s3c24xx_serial_ops,
1689 .flags = UPF_BOOT_AUTOCONF,
1690 .line = 2,
1691 }
Ben Dooks03d5e772008-11-03 09:21:23 +00001692 },
1693#endif
1694#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1695 [3] = {
1696 .port = {
Robert Baldygaef4aca72014-11-24 07:56:22 +01001697 .lock = __PORT_LOCK_UNLOCKED(3),
Ben Dooks03d5e772008-11-03 09:21:23 +00001698 .iotype = UPIO_MEM,
Ben Dooks03d5e772008-11-03 09:21:23 +00001699 .uartclk = 0,
1700 .fifosize = 16,
1701 .ops = &s3c24xx_serial_ops,
1702 .flags = UPF_BOOT_AUTOCONF,
1703 .line = 3,
1704 }
Ben Dooksb4975492008-07-03 12:32:51 +01001705 }
1706#endif
1707};
Robert Baldygaef4aca72014-11-24 07:56:22 +01001708#undef __PORT_LOCK_UNLOCKED
Ben Dooksb4975492008-07-03 12:32:51 +01001709
1710/* s3c24xx_serial_resetport
1711 *
Thomas Abraham0dfb3b42011-10-24 11:48:21 +02001712 * reset the fifos and other the settings.
Ben Dooksb4975492008-07-03 12:32:51 +01001713*/
1714
Thomas Abraham0dfb3b42011-10-24 11:48:21 +02001715static void s3c24xx_serial_resetport(struct uart_port *port,
1716 struct s3c2410_uartcfg *cfg)
Ben Dooksb4975492008-07-03 12:32:51 +01001717{
1718 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
Thomas Abraham0dfb3b42011-10-24 11:48:21 +02001719 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1720 unsigned int ucon_mask;
Ben Dooksb4975492008-07-03 12:32:51 +01001721
Thomas Abraham0dfb3b42011-10-24 11:48:21 +02001722 ucon_mask = info->clksel_mask;
1723 if (info->type == PORT_S3C2440)
1724 ucon_mask |= S3C2440_UCON0_DIVMASK;
1725
1726 ucon &= ucon_mask;
1727 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1728
1729 /* reset both fifos */
1730 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1731 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1732
1733 /* some delay is required after fifo reset */
1734 udelay(1);
Ben Dooksb4975492008-07-03 12:32:51 +01001735}
1736
Ben Dooks30555472008-10-21 14:06:36 +01001737
Krzysztof Kozlowskiebaa81c2016-06-27 13:59:08 +02001738#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
Ben Dooks30555472008-10-21 14:06:36 +01001739
1740static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1741 unsigned long val, void *data)
1742{
1743 struct s3c24xx_uart_port *port;
1744 struct uart_port *uport;
1745
1746 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1747 uport = &port->port;
1748
1749 /* check to see if port is enabled */
1750
1751 if (port->pm_level != 0)
1752 return 0;
1753
1754 /* try and work out if the baudrate is changing, we can detect
1755 * a change in rate, but we do not have support for detecting
1756 * a disturbance in the clock-rate over the change.
1757 */
1758
Kyoungil Kim25f04ad2012-05-20 17:49:31 +09001759 if (IS_ERR(port->baudclk))
Ben Dooks30555472008-10-21 14:06:36 +01001760 goto exit;
1761
Kyoungil Kim25f04ad2012-05-20 17:49:31 +09001762 if (port->baudclk_rate == clk_get_rate(port->baudclk))
Ben Dooks30555472008-10-21 14:06:36 +01001763 goto exit;
1764
1765 if (val == CPUFREQ_PRECHANGE) {
1766 /* we should really shut the port down whilst the
1767 * frequency change is in progress. */
1768
1769 } else if (val == CPUFREQ_POSTCHANGE) {
1770 struct ktermios *termios;
1771 struct tty_struct *tty;
1772
Alan Coxebd2c8f2009-09-19 13:13:28 -07001773 if (uport->state == NULL)
Ben Dooks30555472008-10-21 14:06:36 +01001774 goto exit;
Ben Dooks30555472008-10-21 14:06:36 +01001775
Alan Coxebd2c8f2009-09-19 13:13:28 -07001776 tty = uport->state->port.tty;
Ben Dooks30555472008-10-21 14:06:36 +01001777
Ben Dooks7de40c22008-12-14 23:11:02 +00001778 if (tty == NULL)
Ben Dooks30555472008-10-21 14:06:36 +01001779 goto exit;
Ben Dooks30555472008-10-21 14:06:36 +01001780
Alan Coxadc8d742012-07-14 15:31:47 +01001781 termios = &tty->termios;
Ben Dooks30555472008-10-21 14:06:36 +01001782
1783 if (termios == NULL) {
Sachin Kamatd20925e2012-09-05 10:30:10 +05301784 dev_warn(uport->dev, "%s: no termios?\n", __func__);
Ben Dooks30555472008-10-21 14:06:36 +01001785 goto exit;
1786 }
1787
1788 s3c24xx_serial_set_termios(uport, termios, NULL);
1789 }
1790
Robert Baldygaef4aca72014-11-24 07:56:22 +01001791exit:
Ben Dooks30555472008-10-21 14:06:36 +01001792 return 0;
1793}
1794
Robert Baldygaef4aca72014-11-24 07:56:22 +01001795static inline int
1796s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
Ben Dooks30555472008-10-21 14:06:36 +01001797{
1798 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1799
1800 return cpufreq_register_notifier(&port->freq_transition,
1801 CPUFREQ_TRANSITION_NOTIFIER);
1802}
1803
Robert Baldygaef4aca72014-11-24 07:56:22 +01001804static inline void
1805s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
Ben Dooks30555472008-10-21 14:06:36 +01001806{
1807 cpufreq_unregister_notifier(&port->freq_transition,
1808 CPUFREQ_TRANSITION_NOTIFIER);
1809}
1810
1811#else
Robert Baldygaef4aca72014-11-24 07:56:22 +01001812static inline int
1813s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
Ben Dooks30555472008-10-21 14:06:36 +01001814{
1815 return 0;
1816}
1817
Robert Baldygaef4aca72014-11-24 07:56:22 +01001818static inline void
1819s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
Ben Dooks30555472008-10-21 14:06:36 +01001820{
1821}
1822#endif
1823
Stuart Menefy5086e0a2019-02-12 21:40:22 +00001824static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1825{
1826 struct device *dev = ourport->port.dev;
1827 struct s3c24xx_uart_info *info = ourport->info;
1828 char clk_name[MAX_CLK_NAME_LENGTH];
1829 unsigned int clk_sel;
1830 struct clk *clk;
1831 int clk_num;
1832 int ret;
1833
1834 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1835 for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1836 if (!(clk_sel & (1 << clk_num)))
1837 continue;
1838
1839 sprintf(clk_name, "clk_uart_baud%d", clk_num);
1840 clk = clk_get(dev, clk_name);
1841 if (IS_ERR(clk))
1842 continue;
1843
1844 ret = clk_prepare_enable(clk);
1845 if (ret) {
1846 clk_put(clk);
1847 continue;
1848 }
1849
1850 ourport->baudclk = clk;
1851 ourport->baudclk_rate = clk_get_rate(clk);
1852 s3c24xx_serial_setsource(&ourport->port, clk_num);
1853
1854 return 0;
1855 }
1856
1857 return -EINVAL;
1858}
1859
Ben Dooksb4975492008-07-03 12:32:51 +01001860/* s3c24xx_serial_init_port
1861 *
1862 * initialise a single serial port from the platform device given
1863 */
1864
1865static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
Ben Dooksb4975492008-07-03 12:32:51 +01001866 struct platform_device *platdev)
1867{
1868 struct uart_port *port = &ourport->port;
Thomas Abrahamda121502011-11-02 19:23:25 +09001869 struct s3c2410_uartcfg *cfg = ourport->cfg;
Ben Dooksb4975492008-07-03 12:32:51 +01001870 struct resource *res;
1871 int ret;
1872
1873 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1874
1875 if (platdev == NULL)
1876 return -ENODEV;
1877
Ben Dooksb4975492008-07-03 12:32:51 +01001878 if (port->mapbase != 0)
Krzysztof Kozlowskie51e4d82016-06-16 08:27:35 +02001879 return -EINVAL;
Ben Dooksb4975492008-07-03 12:32:51 +01001880
Ben Dooksb4975492008-07-03 12:32:51 +01001881 /* setup info for port */
1882 port->dev = &platdev->dev;
Ben Dooksb4975492008-07-03 12:32:51 +01001883
Thomas Abraham88bb4ea2011-08-10 15:51:19 +05301884 /* Startup sequence is different for s3c64xx and higher SoC's */
1885 if (s3c24xx_serial_has_interrupt_mask(port))
1886 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1887
Ben Dooksb4975492008-07-03 12:32:51 +01001888 port->uartclk = 1;
1889
1890 if (cfg->uart_flags & UPF_CONS_FLOW) {
1891 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1892 port->flags |= UPF_CONS_FLOW;
1893 }
1894
1895 /* sort our the physical and virtual addresses for each UART */
1896
1897 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1898 if (res == NULL) {
Sachin Kamatd20925e2012-09-05 10:30:10 +05301899 dev_err(port->dev, "failed to find memory resource for uart\n");
Ben Dooksb4975492008-07-03 12:32:51 +01001900 return -EINVAL;
1901 }
1902
Joe Perchese4ac92d2014-05-20 14:05:50 -07001903 dbg("resource %pR)\n", res);
Ben Dooksb4975492008-07-03 12:32:51 +01001904
Thomas Abraham41147bf2013-01-01 00:21:55 -08001905 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1906 if (!port->membase) {
1907 dev_err(port->dev, "failed to remap controller address\n");
1908 return -EBUSY;
1909 }
1910
Ben Dooksb690ace2008-10-21 14:07:03 +01001911 port->mapbase = res->start;
Ben Dooksb4975492008-07-03 12:32:51 +01001912 ret = platform_get_irq(platdev, 0);
1913 if (ret < 0)
1914 port->irq = 0;
Ben Dooksb73c289c2008-10-21 14:07:04 +01001915 else {
Ben Dooksb4975492008-07-03 12:32:51 +01001916 port->irq = ret;
Ben Dooksb73c289c2008-10-21 14:07:04 +01001917 ourport->rx_irq = ret;
1918 ourport->tx_irq = ret + 1;
1919 }
Sachin Kamat9303ac12012-09-05 10:30:11 +05301920
Ben Dooksb73c289c2008-10-21 14:07:04 +01001921 ret = platform_get_irq(platdev, 1);
1922 if (ret > 0)
1923 ourport->tx_irq = ret;
Robert Baldyga658c9d2b72014-12-10 12:49:23 +01001924 /*
1925 * DMA is currently supported only on DT platforms, if DMA properties
1926 * are specified.
1927 */
1928 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1929 "dmas", NULL)) {
1930 ourport->dma = devm_kzalloc(port->dev,
1931 sizeof(*ourport->dma),
1932 GFP_KERNEL);
Krzysztof Kozlowskie51e4d82016-06-16 08:27:35 +02001933 if (!ourport->dma) {
1934 ret = -ENOMEM;
1935 goto err;
1936 }
Robert Baldyga658c9d2b72014-12-10 12:49:23 +01001937 }
Ben Dooksb4975492008-07-03 12:32:51 +01001938
1939 ourport->clk = clk_get(&platdev->dev, "uart");
Chander Kashyap60e93572013-05-28 18:32:07 +05301940 if (IS_ERR(ourport->clk)) {
1941 pr_err("%s: Controller clock not found\n",
1942 dev_name(&platdev->dev));
Krzysztof Kozlowskie51e4d82016-06-16 08:27:35 +02001943 ret = PTR_ERR(ourport->clk);
1944 goto err;
Chander Kashyap60e93572013-05-28 18:32:07 +05301945 }
1946
1947 ret = clk_prepare_enable(ourport->clk);
1948 if (ret) {
1949 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1950 clk_put(ourport->clk);
Krzysztof Kozlowskie51e4d82016-06-16 08:27:35 +02001951 goto err;
Chander Kashyap60e93572013-05-28 18:32:07 +05301952 }
Ben Dooksb4975492008-07-03 12:32:51 +01001953
Stuart Menefy5086e0a2019-02-12 21:40:22 +00001954 ret = s3c24xx_serial_enable_baudclk(ourport);
1955 if (ret)
1956 pr_warn("uart: failed to enable baudclk\n");
1957
Thomas Abraham88bb4ea2011-08-10 15:51:19 +05301958 /* Keep all interrupts masked and cleared */
1959 if (s3c24xx_serial_has_interrupt_mask(port)) {
1960 wr_regl(port, S3C64XX_UINTM, 0xf);
1961 wr_regl(port, S3C64XX_UINTP, 0xf);
1962 wr_regl(port, S3C64XX_UINTSP, 0xf);
1963 }
1964
Fabio Estevam1ff5b642014-06-04 20:06:41 -03001965 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1966 &port->mapbase, port->membase, port->irq,
Ben Dooksb73c289c2008-10-21 14:07:04 +01001967 ourport->rx_irq, ourport->tx_irq, port->uartclk);
Ben Dooksb4975492008-07-03 12:32:51 +01001968
1969 /* reset the fifos (and setup the uart) */
1970 s3c24xx_serial_resetport(port, cfg);
Krzysztof Kozlowskie51e4d82016-06-16 08:27:35 +02001971
Ben Dooksb4975492008-07-03 12:32:51 +01001972 return 0;
Krzysztof Kozlowskie51e4d82016-06-16 08:27:35 +02001973
1974err:
1975 port->mapbase = 0;
1976 return ret;
Ben Dooksb4975492008-07-03 12:32:51 +01001977}
1978
Ben Dooksb4975492008-07-03 12:32:51 +01001979/* Device driver serial port probe */
1980
Greg Kroah-Hartman06674e52019-12-10 15:36:58 +01001981#ifdef CONFIG_OF
Thomas Abraham26c919e2011-11-06 22:10:44 +05301982static const struct of_device_id s3c24xx_uart_dt_match[];
Greg Kroah-Hartman06674e52019-12-10 15:36:58 +01001983#endif
1984
Ben Dooksb4975492008-07-03 12:32:51 +01001985static int probe_index;
1986
Thomas Abraham26c919e2011-11-06 22:10:44 +05301987static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1988 struct platform_device *pdev)
1989{
1990#ifdef CONFIG_OF
1991 if (pdev->dev.of_node) {
1992 const struct of_device_id *match;
1993 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1994 return (struct s3c24xx_serial_drv_data *)match->data;
1995 }
1996#endif
1997 return (struct s3c24xx_serial_drv_data *)
1998 platform_get_device_id(pdev)->driver_data;
1999}
2000
Thomas Abrahamda121502011-11-02 19:23:25 +09002001static int s3c24xx_serial_probe(struct platform_device *pdev)
Ben Dooksb4975492008-07-03 12:32:51 +01002002{
Naveen Krishna Chatradhi4622eb62014-07-14 17:07:18 +05302003 struct device_node *np = pdev->dev.of_node;
Ben Dooksb4975492008-07-03 12:32:51 +01002004 struct s3c24xx_uart_port *ourport;
Tomasz Figa13a9f6c62014-06-26 13:24:34 +02002005 int index = probe_index;
Ben Dooksb4975492008-07-03 12:32:51 +01002006 int ret;
2007
Naveen Krishna Chatradhi4622eb62014-07-14 17:07:18 +05302008 if (np) {
2009 ret = of_alias_get_id(np, "serial");
Tomasz Figa13a9f6c62014-06-26 13:24:34 +02002010 if (ret >= 0)
2011 index = ret;
2012 }
Ben Dooksb4975492008-07-03 12:32:51 +01002013
Tomasz Figa13a9f6c62014-06-26 13:24:34 +02002014 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
2015
Geert Uytterhoeven49ee23b2018-02-23 14:38:34 +01002016 if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
2017 dev_err(&pdev->dev, "serial%d out of range\n", index);
2018 return -EINVAL;
2019 }
Tomasz Figa13a9f6c62014-06-26 13:24:34 +02002020 ourport = &s3c24xx_serial_ports[index];
Thomas Abrahamda121502011-11-02 19:23:25 +09002021
Thomas Abraham26c919e2011-11-06 22:10:44 +05302022 ourport->drv_data = s3c24xx_get_driver_data(pdev);
2023 if (!ourport->drv_data) {
2024 dev_err(&pdev->dev, "could not find driver data\n");
2025 return -ENODEV;
2026 }
Thomas Abrahamda121502011-11-02 19:23:25 +09002027
Kyoungil Kim7cd88832012-05-20 17:45:54 +09002028 ourport->baudclk = ERR_PTR(-EINVAL);
Thomas Abrahamda121502011-11-02 19:23:25 +09002029 ourport->info = ourport->drv_data->info;
Jingoo Han574de552013-07-30 17:06:57 +09002030 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
Jingoo Hand4aab202013-09-09 14:10:30 +09002031 dev_get_platdata(&pdev->dev) :
Thomas Abrahamda121502011-11-02 19:23:25 +09002032 ourport->drv_data->def_cfg;
2033
Naveen Krishna Chatradhi4622eb62014-07-14 17:07:18 +05302034 if (np)
2035 of_property_read_u32(np,
Naveen Krishna Chatradhi135f07c2014-07-14 17:07:16 +05302036 "samsung,uart-fifosize", &ourport->port.fifosize);
2037
Robert Baldyga2f1ba722014-11-24 07:56:23 +01002038 if (ourport->drv_data->fifosize[index])
2039 ourport->port.fifosize = ourport->drv_data->fifosize[index];
2040 else if (ourport->info->fifosize)
2041 ourport->port.fifosize = ourport->info->fifosize;
Thomas Abrahamda121502011-11-02 19:23:25 +09002042
Marek Szyprowski81ccb2a2015-07-31 10:58:27 +02002043 /*
2044 * DMA transfers must be aligned at least to cache line size,
2045 * so find minimal transfer size suitable for DMA mode
2046 */
2047 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2048 dma_get_cache_alignment());
2049
Ben Dooksb4975492008-07-03 12:32:51 +01002050 dbg("%s: initialising port %p...\n", __func__, ourport);
2051
Thomas Abrahamda121502011-11-02 19:23:25 +09002052 ret = s3c24xx_serial_init_port(ourport, pdev);
Ben Dooksb4975492008-07-03 12:32:51 +01002053 if (ret < 0)
Tushar Behera8ad711a2014-06-23 11:32:14 +05302054 return ret;
Ben Dooksb4975492008-07-03 12:32:51 +01002055
Tushar Behera6f134c3c2014-01-20 14:32:34 +05302056 if (!s3c24xx_uart_drv.state) {
2057 ret = uart_register_driver(&s3c24xx_uart_drv);
2058 if (ret < 0) {
2059 pr_err("Failed to register Samsung UART driver\n");
2060 return ret;
2061 }
2062 }
2063
Ben Dooksb4975492008-07-03 12:32:51 +01002064 dbg("%s: adding port\n", __func__);
2065 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
Thomas Abrahamda121502011-11-02 19:23:25 +09002066 platform_set_drvdata(pdev, &ourport->port);
Ben Dooksb4975492008-07-03 12:32:51 +01002067
Heiko Stübner0da33362013-12-05 00:54:38 +01002068 /*
2069 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2070 * so that a potential re-enablement through the pm-callback overlaps
2071 * and keeps the clock enabled in this case.
2072 */
2073 clk_disable_unprepare(ourport->clk);
Stuart Menefy5086e0a2019-02-12 21:40:22 +00002074 if (!IS_ERR(ourport->baudclk))
2075 clk_disable_unprepare(ourport->baudclk);
Heiko Stübner0da33362013-12-05 00:54:38 +01002076
Ben Dooks30555472008-10-21 14:06:36 +01002077 ret = s3c24xx_serial_cpufreq_register(ourport);
2078 if (ret < 0)
Thomas Abrahamda121502011-11-02 19:23:25 +09002079 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
Ben Dooks30555472008-10-21 14:06:36 +01002080
Krzysztof Kozlowski926b7b52016-06-16 08:27:36 +02002081 probe_index++;
2082
Ben Dooksb4975492008-07-03 12:32:51 +01002083 return 0;
Ben Dooksb4975492008-07-03 12:32:51 +01002084}
2085
Bill Pembertonae8d8a12012-11-19 13:26:18 -05002086static int s3c24xx_serial_remove(struct platform_device *dev)
Ben Dooksb4975492008-07-03 12:32:51 +01002087{
2088 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2089
2090 if (port) {
Ben Dooks30555472008-10-21 14:06:36 +01002091 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
Ben Dooksb4975492008-07-03 12:32:51 +01002092 uart_remove_one_port(&s3c24xx_uart_drv, port);
2093 }
2094
Tushar Behera6f134c3c2014-01-20 14:32:34 +05302095 uart_unregister_driver(&s3c24xx_uart_drv);
2096
Ben Dooksb4975492008-07-03 12:32:51 +01002097 return 0;
2098}
2099
Ben Dooksb4975492008-07-03 12:32:51 +01002100/* UART power management code */
MyungJoo Hamaef7fe52011-06-29 15:28:24 +09002101#ifdef CONFIG_PM_SLEEP
2102static int s3c24xx_serial_suspend(struct device *dev)
Ben Dooksb4975492008-07-03 12:32:51 +01002103{
MyungJoo Hamaef7fe52011-06-29 15:28:24 +09002104 struct uart_port *port = s3c24xx_dev_to_port(dev);
Ben Dooksb4975492008-07-03 12:32:51 +01002105
2106 if (port)
2107 uart_suspend_port(&s3c24xx_uart_drv, port);
2108
2109 return 0;
2110}
2111
MyungJoo Hamaef7fe52011-06-29 15:28:24 +09002112static int s3c24xx_serial_resume(struct device *dev)
Ben Dooksb4975492008-07-03 12:32:51 +01002113{
MyungJoo Hamaef7fe52011-06-29 15:28:24 +09002114 struct uart_port *port = s3c24xx_dev_to_port(dev);
Ben Dooksb4975492008-07-03 12:32:51 +01002115 struct s3c24xx_uart_port *ourport = to_ourport(port);
2116
2117 if (port) {
Thomas Abraham9484b002012-10-03 07:40:04 +09002118 clk_prepare_enable(ourport->clk);
Marek Szyprowski1ff36522018-09-13 10:21:25 +02002119 if (!IS_ERR(ourport->baudclk))
2120 clk_prepare_enable(ourport->baudclk);
Ben Dooksb4975492008-07-03 12:32:51 +01002121 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
Marek Szyprowski1ff36522018-09-13 10:21:25 +02002122 if (!IS_ERR(ourport->baudclk))
2123 clk_disable_unprepare(ourport->baudclk);
Thomas Abraham9484b002012-10-03 07:40:04 +09002124 clk_disable_unprepare(ourport->clk);
Ben Dooksb4975492008-07-03 12:32:51 +01002125
2126 uart_resume_port(&s3c24xx_uart_drv, port);
2127 }
2128
2129 return 0;
2130}
MyungJoo Hamaef7fe52011-06-29 15:28:24 +09002131
Michael Spangd09a7302013-03-27 19:34:24 -04002132static int s3c24xx_serial_resume_noirq(struct device *dev)
2133{
2134 struct uart_port *port = s3c24xx_dev_to_port(dev);
남영민a8a17812017-02-01 19:25:46 +09002135 struct s3c24xx_uart_port *ourport = to_ourport(port);
Michael Spangd09a7302013-03-27 19:34:24 -04002136
2137 if (port) {
2138 /* restore IRQ mask */
2139 if (s3c24xx_serial_has_interrupt_mask(port)) {
2140 unsigned int uintm = 0xf;
2141 if (tx_enabled(port))
2142 uintm &= ~S3C64XX_UINTM_TXD_MSK;
2143 if (rx_enabled(port))
2144 uintm &= ~S3C64XX_UINTM_RXD_MSK;
남영민a8a17812017-02-01 19:25:46 +09002145 clk_prepare_enable(ourport->clk);
Marek Szyprowski1ff36522018-09-13 10:21:25 +02002146 if (!IS_ERR(ourport->baudclk))
2147 clk_prepare_enable(ourport->baudclk);
Michael Spangd09a7302013-03-27 19:34:24 -04002148 wr_regl(port, S3C64XX_UINTM, uintm);
Marek Szyprowski1ff36522018-09-13 10:21:25 +02002149 if (!IS_ERR(ourport->baudclk))
2150 clk_disable_unprepare(ourport->baudclk);
남영민a8a17812017-02-01 19:25:46 +09002151 clk_disable_unprepare(ourport->clk);
Michael Spangd09a7302013-03-27 19:34:24 -04002152 }
2153 }
2154
2155 return 0;
2156}
2157
MyungJoo Hamaef7fe52011-06-29 15:28:24 +09002158static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2159 .suspend = s3c24xx_serial_suspend,
2160 .resume = s3c24xx_serial_resume,
Michael Spangd09a7302013-03-27 19:34:24 -04002161 .resume_noirq = s3c24xx_serial_resume_noirq,
MyungJoo Hamaef7fe52011-06-29 15:28:24 +09002162};
Kukjin Kimb882fc12011-07-28 08:50:38 +09002163#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
2164
MyungJoo Hamaef7fe52011-06-29 15:28:24 +09002165#else /* !CONFIG_PM_SLEEP */
Kukjin Kimb882fc12011-07-28 08:50:38 +09002166
2167#define SERIAL_SAMSUNG_PM_OPS NULL
MyungJoo Hamaef7fe52011-06-29 15:28:24 +09002168#endif /* CONFIG_PM_SLEEP */
Ben Dooksb4975492008-07-03 12:32:51 +01002169
Ben Dooksb4975492008-07-03 12:32:51 +01002170/* Console code */
2171
2172#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2173
2174static struct uart_port *cons_uart;
2175
2176static int
2177s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2178{
2179 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2180 unsigned long ufstat, utrstat;
2181
2182 if (ufcon & S3C2410_UFCON_FIFOMODE) {
Uwe Kleine-König9ddc5b62010-01-20 17:02:24 +01002183 /* fifo mode - check amount of data in fifo registers... */
Ben Dooksb4975492008-07-03 12:32:51 +01002184
2185 ufstat = rd_regl(port, S3C2410_UFSTAT);
2186 return (ufstat & info->tx_fifofull) ? 0 : 1;
2187 }
2188
2189 /* in non-fifo mode, we go and use the tx buffer empty */
2190
2191 utrstat = rd_regl(port, S3C2410_UTRSTAT);
2192 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2193}
2194
Michael Spang38adbc52013-03-27 19:34:25 -04002195static bool
2196s3c24xx_port_configured(unsigned int ucon)
2197{
2198 /* consider the serial port configured if the tx/rx mode set */
2199 return (ucon & 0xf) != 0;
2200}
2201
Julien Pichon93b5c032012-09-21 23:22:31 -07002202#ifdef CONFIG_CONSOLE_POLL
2203/*
2204 * Console polling routines for writing and reading from the uart while
2205 * in an interrupt or debug context.
2206 */
2207
2208static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2209{
2210 struct s3c24xx_uart_port *ourport = to_ourport(port);
2211 unsigned int ufstat;
2212
2213 ufstat = rd_regl(port, S3C2410_UFSTAT);
2214 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2215 return NO_POLL_CHAR;
2216
2217 return rd_regb(port, S3C2410_URXH);
2218}
2219
2220static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2221 unsigned char c)
2222{
Doug Andersonbb7f09b2014-04-21 09:40:34 -07002223 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2224 unsigned int ucon = rd_regl(port, S3C2410_UCON);
Michael Spang38adbc52013-03-27 19:34:25 -04002225
2226 /* not possible to xmit on unconfigured port */
2227 if (!s3c24xx_port_configured(ucon))
2228 return;
Julien Pichon93b5c032012-09-21 23:22:31 -07002229
2230 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2231 cpu_relax();
Doug Andersonbb7f09b2014-04-21 09:40:34 -07002232 wr_regb(port, S3C2410_UTXH, c);
Julien Pichon93b5c032012-09-21 23:22:31 -07002233}
2234
2235#endif /* CONFIG_CONSOLE_POLL */
2236
Ben Dooksb4975492008-07-03 12:32:51 +01002237static void
2238s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2239{
Doug Andersonbb7f09b2014-04-21 09:40:34 -07002240 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
Michael Spang38adbc52013-03-27 19:34:25 -04002241
Ben Dooksb4975492008-07-03 12:32:51 +01002242 while (!s3c24xx_serial_console_txrdy(port, ufcon))
Doug Andersonf94b0572014-04-21 09:40:36 -07002243 cpu_relax();
Doug Andersonbb7f09b2014-04-21 09:40:34 -07002244 wr_regb(port, S3C2410_UTXH, ch);
Ben Dooksb4975492008-07-03 12:32:51 +01002245}
2246
2247static void
2248s3c24xx_serial_console_write(struct console *co, const char *s,
2249 unsigned int count)
2250{
Doug Andersonab88c8d2014-04-21 09:40:35 -07002251 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2252
2253 /* not possible to xmit on unconfigured port */
2254 if (!s3c24xx_port_configured(ucon))
2255 return;
2256
Ben Dooksb4975492008-07-03 12:32:51 +01002257 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2258}
2259
2260static void __init
2261s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2262 int *parity, int *bits)
2263{
Ben Dooksb4975492008-07-03 12:32:51 +01002264 struct clk *clk;
2265 unsigned int ulcon;
2266 unsigned int ucon;
2267 unsigned int ubrdiv;
2268 unsigned long rate;
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02002269 unsigned int clk_sel;
2270 char clk_name[MAX_CLK_NAME_LENGTH];
Ben Dooksb4975492008-07-03 12:32:51 +01002271
2272 ulcon = rd_regl(port, S3C2410_ULCON);
2273 ucon = rd_regl(port, S3C2410_UCON);
2274 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2275
2276 dbg("s3c24xx_serial_get_options: port=%p\n"
2277 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2278 port, ulcon, ucon, ubrdiv);
2279
Michael Spang38adbc52013-03-27 19:34:25 -04002280 if (s3c24xx_port_configured(ucon)) {
Ben Dooksb4975492008-07-03 12:32:51 +01002281 switch (ulcon & S3C2410_LCON_CSMASK) {
2282 case S3C2410_LCON_CS5:
2283 *bits = 5;
2284 break;
2285 case S3C2410_LCON_CS6:
2286 *bits = 6;
2287 break;
2288 case S3C2410_LCON_CS7:
2289 *bits = 7;
2290 break;
Ben Dooksb4975492008-07-03 12:32:51 +01002291 case S3C2410_LCON_CS8:
Naveen Krishna Chatradhi3bcce592014-07-14 17:07:17 +05302292 default:
Ben Dooksb4975492008-07-03 12:32:51 +01002293 *bits = 8;
2294 break;
2295 }
2296
2297 switch (ulcon & S3C2410_LCON_PMASK) {
2298 case S3C2410_LCON_PEVEN:
2299 *parity = 'e';
2300 break;
2301
2302 case S3C2410_LCON_PODD:
2303 *parity = 'o';
2304 break;
2305
2306 case S3C2410_LCON_PNONE:
2307 default:
2308 *parity = 'n';
2309 }
2310
2311 /* now calculate the baud rate */
2312
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02002313 clk_sel = s3c24xx_serial_getsource(port);
2314 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
Ben Dooksb4975492008-07-03 12:32:51 +01002315
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02002316 clk = clk_get(port->dev, clk_name);
Kyoungil Kim7cd88832012-05-20 17:45:54 +09002317 if (!IS_ERR(clk))
Thomas Abraham5f5a7a52011-10-24 11:47:46 +02002318 rate = clk_get_rate(clk);
Ben Dooksb4975492008-07-03 12:32:51 +01002319 else
2320 rate = 1;
2321
Ben Dooksb4975492008-07-03 12:32:51 +01002322 *baud = rate / (16 * (ubrdiv + 1));
2323 dbg("calculated baud %d\n", *baud);
2324 }
2325
2326}
2327
Ben Dooksb4975492008-07-03 12:32:51 +01002328static int __init
2329s3c24xx_serial_console_setup(struct console *co, char *options)
2330{
2331 struct uart_port *port;
2332 int baud = 9600;
2333 int bits = 8;
2334 int parity = 'n';
2335 int flow = 'n';
2336
2337 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2338 co, co->index, options);
2339
2340 /* is this a valid port */
2341
Ben Dooks03d5e772008-11-03 09:21:23 +00002342 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
Ben Dooksb4975492008-07-03 12:32:51 +01002343 co->index = 0;
2344
2345 port = &s3c24xx_serial_ports[co->index].port;
2346
2347 /* is the port configured? */
2348
Thomas Abrahamee430f12011-06-14 19:12:26 +09002349 if (port->mapbase == 0x0)
2350 return -ENODEV;
Ben Dooksb4975492008-07-03 12:32:51 +01002351
2352 cons_uart = port;
2353
2354 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2355
2356 /*
2357 * Check whether an invalid uart number has been specified, and
2358 * if so, search for the first available port that does have
2359 * console support.
2360 */
2361 if (options)
2362 uart_parse_options(options, &baud, &parity, &bits, &flow);
2363 else
2364 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2365
2366 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2367
2368 return uart_set_options(port, co, baud, parity, bits, flow);
2369}
2370
Ben Dooksb4975492008-07-03 12:32:51 +01002371static struct console s3c24xx_serial_console = {
2372 .name = S3C24XX_SERIAL_NAME,
2373 .device = uart_console_device,
2374 .flags = CON_PRINTBUFFER,
2375 .index = -1,
2376 .write = s3c24xx_serial_console_write,
Thomas Abraham5822a5d2011-06-14 19:12:26 +09002377 .setup = s3c24xx_serial_console_setup,
2378 .data = &s3c24xx_uart_drv,
Ben Dooksb4975492008-07-03 12:32:51 +01002379};
Ben Dooksb4975492008-07-03 12:32:51 +01002380#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2381
Thomas Abrahamda121502011-11-02 19:23:25 +09002382#ifdef CONFIG_CPU_S3C2410
2383static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2384 .info = &(struct s3c24xx_uart_info) {
2385 .name = "Samsung S3C2410 UART",
2386 .type = PORT_S3C2410,
2387 .fifosize = 16,
2388 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2389 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2390 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2391 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2392 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2393 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2394 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2395 .num_clks = 2,
2396 .clksel_mask = S3C2410_UCON_CLKMASK,
2397 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2398 },
2399 .def_cfg = &(struct s3c2410_uartcfg) {
2400 .ucon = S3C2410_UCON_DEFAULT,
2401 .ufcon = S3C2410_UFCON_DEFAULT,
2402 },
2403};
2404#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2405#else
2406#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2407#endif
2408
2409#ifdef CONFIG_CPU_S3C2412
2410static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2411 .info = &(struct s3c24xx_uart_info) {
2412 .name = "Samsung S3C2412 UART",
2413 .type = PORT_S3C2412,
2414 .fifosize = 64,
2415 .has_divslot = 1,
2416 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2417 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2418 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2419 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2420 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2421 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2422 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2423 .num_clks = 4,
2424 .clksel_mask = S3C2412_UCON_CLKMASK,
2425 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2426 },
2427 .def_cfg = &(struct s3c2410_uartcfg) {
2428 .ucon = S3C2410_UCON_DEFAULT,
2429 .ufcon = S3C2410_UFCON_DEFAULT,
2430 },
2431};
2432#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2433#else
2434#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2435#endif
2436
2437#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
Denis 'GNUtoo' Cariklib26469a2012-02-23 08:23:52 +01002438 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
Thomas Abrahamda121502011-11-02 19:23:25 +09002439static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2440 .info = &(struct s3c24xx_uart_info) {
2441 .name = "Samsung S3C2440 UART",
2442 .type = PORT_S3C2440,
2443 .fifosize = 64,
2444 .has_divslot = 1,
2445 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2446 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2447 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2448 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2449 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2450 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2451 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2452 .num_clks = 4,
2453 .clksel_mask = S3C2412_UCON_CLKMASK,
2454 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2455 },
2456 .def_cfg = &(struct s3c2410_uartcfg) {
2457 .ucon = S3C2410_UCON_DEFAULT,
2458 .ufcon = S3C2410_UFCON_DEFAULT,
2459 },
2460};
2461#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2462#else
2463#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2464#endif
2465
Kukjin Kim953b53a2014-07-01 06:32:22 +09002466#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
Thomas Abrahamda121502011-11-02 19:23:25 +09002467static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2468 .info = &(struct s3c24xx_uart_info) {
2469 .name = "Samsung S3C6400 UART",
2470 .type = PORT_S3C6400,
2471 .fifosize = 64,
2472 .has_divslot = 1,
2473 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2474 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2475 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2476 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2477 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2478 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2479 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2480 .num_clks = 4,
2481 .clksel_mask = S3C6400_UCON_CLKMASK,
2482 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2483 },
2484 .def_cfg = &(struct s3c2410_uartcfg) {
2485 .ucon = S3C2410_UCON_DEFAULT,
2486 .ufcon = S3C2410_UFCON_DEFAULT,
2487 },
2488};
2489#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2490#else
2491#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2492#endif
2493
2494#ifdef CONFIG_CPU_S5PV210
2495static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2496 .info = &(struct s3c24xx_uart_info) {
2497 .name = "Samsung S5PV210 UART",
2498 .type = PORT_S3C6400,
2499 .has_divslot = 1,
2500 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2501 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2502 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2503 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2504 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2505 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2506 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2507 .num_clks = 2,
2508 .clksel_mask = S5PV210_UCON_CLKMASK,
2509 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2510 },
2511 .def_cfg = &(struct s3c2410_uartcfg) {
2512 .ucon = S5PV210_UCON_DEFAULT,
2513 .ufcon = S5PV210_UFCON_DEFAULT,
2514 },
2515 .fifosize = { 256, 64, 16, 16 },
2516};
2517#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2518#else
2519#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2520#endif
2521
Chander Kashyap33f88132013-06-19 00:29:34 +09002522#if defined(CONFIG_ARCH_EXYNOS)
Chanwoo Choi31ec77a2014-12-02 17:49:54 +09002523#define EXYNOS_COMMON_SERIAL_DRV_DATA \
2524 .info = &(struct s3c24xx_uart_info) { \
2525 .name = "Samsung Exynos UART", \
2526 .type = PORT_S3C6400, \
2527 .has_divslot = 1, \
2528 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2529 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2530 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2531 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2532 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2533 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2534 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2535 .num_clks = 1, \
2536 .clksel_mask = 0, \
2537 .clksel_shift = 0, \
2538 }, \
2539 .def_cfg = &(struct s3c2410_uartcfg) { \
2540 .ucon = S5PV210_UCON_DEFAULT, \
2541 .ufcon = S5PV210_UFCON_DEFAULT, \
2542 .has_fracval = 1, \
2543 } \
2544
Thomas Abrahamda121502011-11-02 19:23:25 +09002545static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
Chanwoo Choi31ec77a2014-12-02 17:49:54 +09002546 EXYNOS_COMMON_SERIAL_DRV_DATA,
Thomas Abrahamda121502011-11-02 19:23:25 +09002547 .fifosize = { 256, 64, 16, 16 },
2548};
Chanwoo Choi31ec77a2014-12-02 17:49:54 +09002549
2550static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2551 EXYNOS_COMMON_SERIAL_DRV_DATA,
2552 .fifosize = { 64, 256, 16, 256 },
2553};
2554
Thomas Abrahamda121502011-11-02 19:23:25 +09002555#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
Chanwoo Choi31ec77a2014-12-02 17:49:54 +09002556#define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
Thomas Abrahamda121502011-11-02 19:23:25 +09002557#else
2558#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
Chanwoo Choi31ec77a2014-12-02 17:49:54 +09002559#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
Thomas Abrahamda121502011-11-02 19:23:25 +09002560#endif
2561
Krzysztof Kozlowski24ee4df2015-05-02 00:40:05 +09002562static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
Thomas Abrahamda121502011-11-02 19:23:25 +09002563 {
2564 .name = "s3c2410-uart",
2565 .driver_data = S3C2410_SERIAL_DRV_DATA,
2566 }, {
2567 .name = "s3c2412-uart",
2568 .driver_data = S3C2412_SERIAL_DRV_DATA,
2569 }, {
2570 .name = "s3c2440-uart",
2571 .driver_data = S3C2440_SERIAL_DRV_DATA,
2572 }, {
2573 .name = "s3c6400-uart",
2574 .driver_data = S3C6400_SERIAL_DRV_DATA,
2575 }, {
2576 .name = "s5pv210-uart",
2577 .driver_data = S5PV210_SERIAL_DRV_DATA,
2578 }, {
2579 .name = "exynos4210-uart",
2580 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
Chanwoo Choi31ec77a2014-12-02 17:49:54 +09002581 }, {
2582 .name = "exynos5433-uart",
2583 .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
Thomas Abrahamda121502011-11-02 19:23:25 +09002584 },
2585 { },
2586};
2587MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2588
Thomas Abraham26c919e2011-11-06 22:10:44 +05302589#ifdef CONFIG_OF
2590static const struct of_device_id s3c24xx_uart_dt_match[] = {
Heiko Stübner666ca0b2012-11-22 11:37:44 +01002591 { .compatible = "samsung,s3c2410-uart",
2592 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2593 { .compatible = "samsung,s3c2412-uart",
2594 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2595 { .compatible = "samsung,s3c2440-uart",
2596 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2597 { .compatible = "samsung,s3c6400-uart",
2598 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2599 { .compatible = "samsung,s5pv210-uart",
2600 .data = (void *)S5PV210_SERIAL_DRV_DATA },
Thomas Abraham26c919e2011-11-06 22:10:44 +05302601 { .compatible = "samsung,exynos4210-uart",
Mark Browna169a882011-11-08 17:00:14 +09002602 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
Chanwoo Choi31ec77a2014-12-02 17:49:54 +09002603 { .compatible = "samsung,exynos5433-uart",
2604 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
Thomas Abraham26c919e2011-11-06 22:10:44 +05302605 {},
2606};
2607MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
Thomas Abraham26c919e2011-11-06 22:10:44 +05302608#endif
2609
Thomas Abrahamda121502011-11-02 19:23:25 +09002610static struct platform_driver samsung_serial_driver = {
2611 .probe = s3c24xx_serial_probe,
Bill Pemberton2d47b712012-11-19 13:21:34 -05002612 .remove = s3c24xx_serial_remove,
Thomas Abrahamda121502011-11-02 19:23:25 +09002613 .id_table = s3c24xx_serial_driver_ids,
2614 .driver = {
2615 .name = "samsung-uart",
Thomas Abrahamda121502011-11-02 19:23:25 +09002616 .pm = SERIAL_SAMSUNG_PM_OPS,
Sachin Kamat905f4ba2013-01-07 09:50:42 +05302617 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
Thomas Abrahamda121502011-11-02 19:23:25 +09002618 },
2619};
2620
Tushar Behera6f134c3c2014-01-20 14:32:34 +05302621module_platform_driver(samsung_serial_driver);
Thomas Abrahamda121502011-11-02 19:23:25 +09002622
Marek Szyprowskic3bda292015-02-02 10:47:35 +01002623#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
Tomasz Figab94ba032015-01-23 14:47:41 +01002624/*
2625 * Early console.
2626 */
2627
2628struct samsung_early_console_data {
2629 u32 txfull_mask;
2630};
2631
2632static void samsung_early_busyuart(struct uart_port *port)
2633{
2634 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2635 ;
2636}
2637
2638static void samsung_early_busyuart_fifo(struct uart_port *port)
2639{
2640 struct samsung_early_console_data *data = port->private_data;
2641
2642 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2643 ;
2644}
2645
2646static void samsung_early_putc(struct uart_port *port, int c)
2647{
2648 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2649 samsung_early_busyuart_fifo(port);
2650 else
2651 samsung_early_busyuart(port);
2652
2653 writeb(c, port->membase + S3C2410_UTXH);
2654}
2655
2656static void samsung_early_write(struct console *con, const char *s, unsigned n)
2657{
2658 struct earlycon_device *dev = con->data;
2659
2660 uart_console_write(&dev->port, s, n, samsung_early_putc);
2661}
2662
2663static int __init samsung_early_console_setup(struct earlycon_device *device,
2664 const char *opt)
2665{
2666 if (!device->port.membase)
2667 return -ENODEV;
2668
2669 device->con->write = samsung_early_write;
2670 return 0;
2671}
2672
2673/* S3C2410 */
2674static struct samsung_early_console_data s3c2410_early_console_data = {
2675 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2676};
2677
2678static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2679 const char *opt)
2680{
2681 device->port.private_data = &s3c2410_early_console_data;
2682 return samsung_early_console_setup(device, opt);
2683}
2684OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2685 s3c2410_early_console_setup);
Tomasz Figab94ba032015-01-23 14:47:41 +01002686
2687/* S3C2412, S3C2440, S3C64xx */
2688static struct samsung_early_console_data s3c2440_early_console_data = {
2689 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2690};
2691
2692static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2693 const char *opt)
2694{
2695 device->port.private_data = &s3c2440_early_console_data;
2696 return samsung_early_console_setup(device, opt);
2697}
2698OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2699 s3c2440_early_console_setup);
2700OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2701 s3c2440_early_console_setup);
2702OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2703 s3c2440_early_console_setup);
Tomasz Figab94ba032015-01-23 14:47:41 +01002704
2705/* S5PV210, EXYNOS */
2706static struct samsung_early_console_data s5pv210_early_console_data = {
2707 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2708};
2709
2710static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2711 const char *opt)
2712{
2713 device->port.private_data = &s5pv210_early_console_data;
2714 return samsung_early_console_setup(device, opt);
2715}
2716OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2717 s5pv210_early_console_setup);
2718OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2719 s5pv210_early_console_setup);
Marek Szyprowskic3bda292015-02-02 10:47:35 +01002720#endif
Tomasz Figab94ba032015-01-23 14:47:41 +01002721
Thomas Abrahamda121502011-11-02 19:23:25 +09002722MODULE_ALIAS("platform:samsung-uart");
Ben Dooksb4975492008-07-03 12:32:51 +01002723MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2724MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2725MODULE_LICENSE("GPL v2");