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Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -07001/*
2 * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "am33xx.dtsi"
11
12/ {
13 model = "Toby Churchill SL50 Series";
14 compatible = "tcl,am335x-sl50", "ti,am33xx";
15
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&dcdc2_reg>;
19 };
20 };
21
Javier Martinez Canillas278cb792016-08-31 12:35:30 +020022 memory@80000000 {
Javier Martinez Canillas35852c62016-08-31 12:35:15 +020023 device_type = "memory";
24 reg = <0x80000000 0x20000000>; /* 512 MB */
25 };
26
Enric Balletbo i Serra01c37be42016-01-16 11:51:12 +010027 chosen {
28 stdout-path = &uart0;
29 };
30
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -070031 leds {
32 compatible = "gpio-leds";
33 pinctrl-names = "default";
34 pinctrl-0 = <&led_pins>;
35
Javier Martinez Canillasc731abd2016-08-01 12:47:03 -040036 led0 {
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -070037 label = "sl50:green:usr0";
38 gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
39 default-state = "off";
40 };
41
Javier Martinez Canillasc731abd2016-08-01 12:47:03 -040042 led1 {
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -070043 label = "sl50:red:usr1";
44 gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
45 default-state = "off";
46 };
47
Javier Martinez Canillasc731abd2016-08-01 12:47:03 -040048 led2 {
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -070049 label = "sl50:green:usr2";
50 gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
51 default-state = "off";
52 };
53
Javier Martinez Canillasc731abd2016-08-01 12:47:03 -040054 led3 {
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -070055 label = "sl50:red:usr3";
56 gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
57 default-state = "off";
58 };
59 };
60
61 backlight0: disp0 {
62 compatible = "pwm-backlight";
63 pwms = <&ehrpwm1 0 500000 0>;
64 brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
65 default-brightness-level = <6>;
66 };
67
68 backlight1: disp1 {
69 compatible = "pwm-backlight";
70 pwms = <&ehrpwm1 1 500000 0>;
71 brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
72 default-brightness-level = <6>;
73 };
74
Enric Balletbo i Serrab328d9b2016-01-16 11:51:13 +010075 clocks {
76 compatible = "simple-bus";
77 #address-cells = <1>;
78 #size-cells = <0>;
79
80 /* audio external oscillator */
81 tlv320aic3x_mclk: oscillator@0 {
82 compatible = "fixed-clock";
83 #clock-cells = <0>;
84 clock-frequency = <24576000>; /* 24.576MHz */
85 };
86 };
87
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -070088 sound {
89 compatible = "ti,da830-evm-audio";
90 ti,model = "AM335x-SL50";
91 ti,audio-codec = <&audio_codec>;
92 ti,mcasp-controller = <&mcasp0>;
Enric Balletbo i Serrab328d9b2016-01-16 11:51:13 +010093
94 clocks = <&tlv320aic3x_mclk>;
95 clock-names = "mclk";
96
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -070097 ti,audio-routing =
98 "Headphone Jack", "HPLOUT",
99 "Headphone Jack", "HPROUT",
100 "LINE1R", "Line In",
101 "LINE1L", "Line In";
102 };
103
104 emmc_pwrseq: pwrseq@0 {
105 compatible = "mmc-pwrseq-emmc";
106 pinctrl-names = "default";
107 pinctrl-0 = <&emmc_pwrseq_pins>;
108 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
109 };
110
Javier Martinez Canillas4c049a52016-08-01 12:46:58 -0400111 vmmcsd_fixed: fixedregulator0 {
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700112 compatible = "regulator-fixed";
113 regulator-name = "vmmcsd_fixed";
114 regulator-min-microvolt = <3300000>;
115 regulator-max-microvolt = <3300000>;
116 };
117};
118
119&am33xx_pinmux {
120 pinctrl-names = "default";
121 pinctrl-0 = <&lwb_pins>;
122
123 led_pins: pinmux_led_pins {
124 pinctrl-single,pins = <
125 AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */
126 AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* gpmc_a6.gpio1_22 */
127 AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* gpmc_a7.gpio1_23 */
128 AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* gpmc_a8.gpio1_24 */
129 >;
130 };
131
132 uart0_pins: pinmux_uart0_pins {
133 pinctrl-single,pins = <
134 AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
135 AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
136 >;
137 };
138
Enric Balletbo i Serrae9c7beb2017-01-16 17:57:32 +0100139 uart1_pins: pinmux_uart1_pins {
140 pinctrl-single,pins = <
141 AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
142 AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
143 >;
144 };
145
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700146 uart4_pins: pinmux_uart4_pins {
147 pinctrl-single,pins = <
148 AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* gpmc_wait0.uart4_rxd */
149 AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpmc_wpn.uart4_txd */
150 >;
151 };
152
153 i2c0_pins: pinmux_i2c0_pins {
154 pinctrl-single,pins = <
155 AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
156 AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
157 >;
158 };
159
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700160 i2c2_pins: pinmux_i2c2_pins {
161 pinctrl-single,pins = <
162 AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */
163 AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */
164 >;
165 };
166
167 cpsw_default: cpsw_default {
168 pinctrl-single,pins = <
169 /* Slave 1 */
170 AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
171 AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
172 AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
173 AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
174 AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
175 AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
176 AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
177 AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
178 AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
179 AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
180 AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
181 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
182 AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
183 >;
184 };
185
186 cpsw_sleep: cpsw_sleep {
187 pinctrl-single,pins = <
188 /* Slave 1 reset value */
189 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
190 AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
191 AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
192 AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
193 AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
194 AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
195 AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
196 AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
197 AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
198 AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
199 AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
200 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
201 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
202 >;
203 };
204
205 davinci_mdio_default: davinci_mdio_default {
206 pinctrl-single,pins = <
207 /* MDIO */
208 AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
209 AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
210 >;
211 };
212
213 davinci_mdio_sleep: davinci_mdio_sleep {
214 pinctrl-single,pins = <
215 /* MDIO reset value */
216 AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
217 AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
218 >;
219 };
220
221 mmc1_pins: pinmux_mmc1_pins {
222 pinctrl-single,pins = <
223 AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
224 >;
225 };
226
227 emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins {
228 pinctrl-single,pins = <
229 AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a4.gpio1_20 */
230 >;
231 };
232
233 emmc_pins: pinmux_emmc_pins {
234 pinctrl-single,pins = <
235 AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
236 AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
237 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
238 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
239 AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
240 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
241 AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
242 AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
243 AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
244 AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
245 >;
246 };
247
248 audio_pins: pinmux_audio_pins {
249 pinctrl-single,pins = <
250 AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
251 AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */
252 AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */
253 AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */
Enric Balletbo i Serrab328d9b2016-01-16 11:51:13 +0100254 AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2 */
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700255 >;
256 };
257
258 ehrpwm1_pins: pinmux_ehrpwm1a_pins {
259 pinctrl-single,pins = <
260 AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE6) /* gpmc_a2.ehrpwm1a */
261 AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.ehrpwm1b */
262 >;
263 };
264
Enric Balletbo i Serraf37f9112017-01-16 17:57:33 +0100265 spi0_pins: pinmux_spi0_pins {
266 pinctrl-single,pins = <
267 AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_MOSI - spi0_d0.spi0_d0 */
268 AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_MISO - spi0_d1.spi0_d1 */
269 AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_CLK - spi0_clk.spi0_clk */
270 AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_CS0 (NBATTSS) - spi0_cs0.spi0_cs0 */
271 AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_CS1 (FPGA_FLASH_NCS) - spi0_cs1.spi0_cs1 */
272 >;
273 };
274
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700275 lwb_pins: pinmux_lwb_pins {
276 pinctrl-single,pins = <
277 AM33XX_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) /* SoundPA_en - mcasp0_fsr.gpio3_19 */
278 AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* nKbdOnC - gpmc_ad10.gpio0_26 */
279 AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */
280 AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */
281 AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7) /* nDispReset - gpmc_ad14.gpio1_14 */
282 AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */
283 /* AVR Programming - SPI Bus (bit bang) - Screen and Keyboard */
284 AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE7) /* Kbd/Disp/BattMOSI spi0_d0.gpio0_3 */
285 AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE7) /* Kbd/Disp/BattMISO spi0_d1.gpio0_4 */
286 AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE7) /* Kbd/Disp/BattSCLK spi0_clk.gpio0_2 */
287 /* PDI Bus - Battery system */
288 AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */
289 AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */
290 >;
291 };
292};
293
294&i2c0 {
295 status = "okay";
296 pinctrl-names = "default";
297 pinctrl-0 = <&i2c0_pins>;
298
299 clock-frequency = <400000>;
300
301 tps: tps@24 {
302 reg = <0x24>;
303 };
304
Enric Balletbo i Serra1d669a72017-01-16 17:57:34 +0100305 bq32000: rtc@68 {
306 compatible = "ti,bq32000";
307 trickle-resistor-ohms = <1120>;
308 reg = <0x68>;
309 };
310
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700311 eeprom: eeprom@50 {
312 compatible = "at,24c256";
313 reg = <0x50>;
314 };
Enric Balletbo i Serra1d669a72017-01-16 17:57:34 +0100315
Enric Balletbo i Serra4340f9d2017-01-16 17:57:35 +0100316 gpio_exp: mcp23017@20 {
317 compatible = "microchip,mcp23017";
318 reg = <0x20>;
319 };
Enric Balletbo i Serra1d669a72017-01-16 17:57:34 +0100320
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700321};
322
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700323&i2c2 {
324 status = "okay";
325 pinctrl-names = "default";
326 pinctrl-0 = <&i2c2_pins>;
327
328 clock-frequency = <400000>;
329
330 audio_codec: tlv320aic3106@1b {
331 status = "okay";
332 compatible = "ti,tlv320aic3106";
333 reg = <0x1b>;
334
335 AVDD-supply = <&ldo4_reg>;
336 IOVDD-supply = <&ldo4_reg>;
337 DRVDD-supply = <&ldo4_reg>;
338 DVDD-supply = <&ldo3_reg>;
339 };
340};
341
Enric Balletbo i Serra1d669a72017-01-16 17:57:34 +0100342&rtc {
343 status = "disabled";
344};
345
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700346&usb {
347 status = "okay";
348};
349
350&usb_ctrl_mod {
351 status = "okay";
352};
353
354&usb0_phy {
355 status = "okay";
356};
357
358&usb1_phy {
359 status = "okay";
360};
361
362&usb0 {
363 status = "okay";
364 dr_mode = "peripheral";
365};
366
367&usb1 {
368 status = "okay";
369 dr_mode = "host";
370};
371
372&cppi41dma {
373 status = "okay";
374};
375
376&mmc1 {
377 status = "okay";
378 pinctrl-names = "default";
379 pinctrl-0 = <&mmc1_pins>;
380 bus-width = <4>;
381 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
382 vmmc-supply = <&vmmcsd_fixed>;
383};
384
385&mmc2 {
386 status = "okay";
387 pinctrl-names = "default";
388 pinctrl-0 = <&emmc_pins>;
389 bus-width = <8>;
390 vmmc-supply = <&vmmcsd_fixed>;
391 mmc-pwrseq = <&emmc_pwrseq>;
392};
393
394&mcasp0 {
395 status = "okay";
396 pinctrl-names = "default";
397 pinctrl-0 = <&audio_pins>;
398
399 op-mode = <0>; /* MCASP_ISS_MODE */
400 tdm-slots = <2>;
401 serial-dir = <
402 2 0 1 0
403 0 0 0 0
404 0 0 0 0
405 0 0 0 0
406 >;
407 tx-num-evt = <1>;
408 rx-num-evt = <1>;
409};
410
411&uart0 {
412 status = "okay";
413 pinctrl-names = "default";
414 pinctrl-0 = <&uart0_pins>;
415};
416
Enric Balletbo i Serrae9c7beb2017-01-16 17:57:32 +0100417&uart1 {
418 status = "okay";
419 pinctrl-names = "default";
420 pinctrl-0 = <&uart1_pins>;
421};
422
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700423&uart4 {
424 status = "okay";
425 pinctrl-names = "default";
426 pinctrl-0 = <&uart4_pins>;
427};
428
Enric Balletbo i Serraf37f9112017-01-16 17:57:33 +0100429&spi0 {
430 status = "okay";
431 pinctrl-names = "default";
432 pinctrl-0 = <&spi0_pins>;
433
434 flash: n25q032@1 {
435 #address-cells = <1>;
436 #size-cells = <1>;
437 compatible = "micron,n25q032";
438 reg = <1>;
439 spi-max-frequency = <5000000>;
440 };
441};
442
Peter Ujfalusie327b3f2016-02-19 16:12:19 +0200443#include "tps65217.dtsi"
444
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700445&tps {
446 ti,pmic-shutdown-controller;
447
448 interrupt-parent = <&intc>;
449 interrupts = <7>; /* NNMI */
450
451 regulators {
452 dcdc1_reg: regulator@0 {
453 /* VDDS_DDR */
454 regulator-min-microvolt = <1500000>;
455 regulator-max-microvolt = <1500000>;
456 regulator-always-on;
457 };
458
459 dcdc2_reg: regulator@1 {
460 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
461 regulator-name = "vdd_mpu";
462 regulator-min-microvolt = <925000>;
463 regulator-max-microvolt = <1325000>;
464 regulator-boot-on;
465 regulator-always-on;
466 };
467
468 dcdc3_reg: regulator@2 {
469 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
470 regulator-name = "vdd_core";
471 regulator-min-microvolt = <925000>;
472 regulator-max-microvolt = <1150000>;
473 regulator-boot-on;
474 regulator-always-on;
475 };
476
477 ldo1_reg: regulator@3 {
478 /* VRTC / VIO / VDDS*/
479 regulator-always-on;
480 regulator-min-microvolt = <1800000>;
481 regulator-max-microvolt = <1800000>;
482 };
483
484 ldo2_reg: regulator@4 {
485 /* VDD_3V3AUX */
486 regulator-always-on;
487 regulator-min-microvolt = <3300000>;
488 regulator-max-microvolt = <3300000>;
489 };
490
491 ldo3_reg: regulator@5 {
492 /* VDD_1V8 */
493 regulator-min-microvolt = <1800000>;
494 regulator-max-microvolt = <1800000>;
495 regulator-always-on;
496 };
497
498 ldo4_reg: regulator@6 {
Enric Balletbo i Serra8584d4f2015-05-28 09:49:50 -0700499 /* VDD_3V3A */
500 regulator-min-microvolt = <3300000>;
501 regulator-max-microvolt = <3300000>;
502 regulator-always-on;
503 };
504 };
505};
506
507&cpsw_emac0 {
508 phy_id = <&davinci_mdio>, <0>;
509 phy-mode = "mii";
510};
511
512&cpsw_emac1 {
513 phy_id = <&davinci_mdio>, <1>;
514 phy-mode = "mii";
515};
516
517&mac {
518 status = "okay";
519 pinctrl-names = "default", "sleep";
520 pinctrl-0 = <&cpsw_default>;
521 pinctrl-1 = <&cpsw_sleep>;
522};
523
524&davinci_mdio {
525 status = "okay";
526 pinctrl-names = "default", "sleep";
527 pinctrl-0 = <&davinci_mdio_default>;
528 pinctrl-1 = <&davinci_mdio_sleep>;
529};
530
531&sham {
532 status = "okay";
533};
534
535&aes {
536 status = "okay";
537};
538
539&epwmss1 {
540 status = "okay";
541};
542
543&ehrpwm1 {
544 status = "okay";
545 pinctrl-names = "default";
546 pinctrl-0 = <&ehrpwm1_pins>;
547};