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Shawn Guo117ccd552013-05-03 11:28:42 +08001/*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
Anson Huang4291b642014-01-14 17:30:28 +080011#include <dt-bindings/input/input.h>
Shawn Guo117ccd552013-05-03 11:28:42 +080012#include "imx6sl.dtsi"
13
14/ {
15 model = "Freescale i.MX6 SoloLite EVK Board";
16 compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
17
18 memory {
19 reg = <0x80000000 0x40000000>;
20 };
Peter Chen60222322013-09-10 10:23:16 +080021
22 regulators {
23 compatible = "simple-bus";
Shawn Guo56160e32014-02-07 23:22:50 +080024 #address-cells = <1>;
25 #size-cells = <0>;
Peter Chen60222322013-09-10 10:23:16 +080026
Shawn Guo56160e32014-02-07 23:22:50 +080027 reg_usb_otg1_vbus: regulator@0 {
Peter Chen60222322013-09-10 10:23:16 +080028 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080029 reg = <0>;
Peter Chen60222322013-09-10 10:23:16 +080030 regulator-name = "usb_otg1_vbus";
31 regulator-min-microvolt = <5000000>;
32 regulator-max-microvolt = <5000000>;
33 gpio = <&gpio4 0 0>;
34 enable-active-high;
35 };
36
Shawn Guo56160e32014-02-07 23:22:50 +080037 reg_usb_otg2_vbus: regulator@1 {
Peter Chen60222322013-09-10 10:23:16 +080038 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080039 reg = <1>;
Peter Chen60222322013-09-10 10:23:16 +080040 regulator-name = "usb_otg2_vbus";
41 regulator-min-microvolt = <5000000>;
42 regulator-max-microvolt = <5000000>;
43 gpio = <&gpio4 2 0>;
44 enable-active-high;
45 };
46 };
Shawn Guo117ccd552013-05-03 11:28:42 +080047};
48
Huang Shijied1b53972013-10-18 10:32:53 +080049&ecspi1 {
50 fsl,spi-num-chipselects = <1>;
51 cs-gpios = <&gpio4 11 0>;
52 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +080053 pinctrl-0 = <&pinctrl_ecspi1>;
Huang Shijied1b53972013-10-18 10:32:53 +080054 status = "okay";
55
56 flash: m25p80@0 {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 compatible = "st,m25p32";
60 spi-max-frequency = <20000000>;
61 reg = <0>;
62 };
63};
64
Shawn Guo117ccd552013-05-03 11:28:42 +080065&fec {
66 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +080067 pinctrl-0 = <&pinctrl_fec>;
Shawn Guo117ccd552013-05-03 11:28:42 +080068 phy-mode = "rmii";
69 status = "okay";
70};
71
72&iomuxc {
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_hog>;
75
Shawn Guofffaa652013-11-04 10:49:04 +080076 imx6sl-evk {
Shawn Guo117ccd552013-05-03 11:28:42 +080077 pinctrl_hog: hoggrp {
78 fsl,pins = <
79 MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
80 MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059
81 MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059
82 MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059
83 MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
Peter Chen60222322013-09-10 10:23:16 +080084 MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
85 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
Shawn Guo117ccd552013-05-03 11:28:42 +080086 >;
87 };
Shawn Guofffaa652013-11-04 10:49:04 +080088
89 pinctrl_ecspi1: ecspi1grp {
90 fsl,pins = <
91 MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
92 MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
93 MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
94 >;
95 };
96
97 pinctrl_fec: fecgrp {
98 fsl,pins = <
99 MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
100 MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
101 MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
102 MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
103 MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
104 MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
105 MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
106 MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
107 MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
108 >;
109 };
110
Anson Huang4291b642014-01-14 17:30:28 +0800111 pinctrl_kpp: kppgrp {
112 fsl,pins = <
113 MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
114 MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010
115 MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0
116 MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0
117 MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0
118 MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0
119 >;
120 };
121
Shawn Guofffaa652013-11-04 10:49:04 +0800122 pinctrl_uart1: uart1grp {
123 fsl,pins = <
124 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
125 MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
126 >;
127 };
128
129 pinctrl_usbotg1: usbotg1grp {
130 fsl,pins = <
131 MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
132 >;
133 };
134
135 pinctrl_usdhc1: usdhc1grp {
136 fsl,pins = <
137 MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
138 MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
139 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
140 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
141 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
142 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
143 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
144 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
145 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
146 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
147 >;
148 };
149
150 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
151 fsl,pins = <
152 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
153 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
154 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
155 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
156 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
157 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
158 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
159 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
160 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
161 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
162 >;
163 };
164
165 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
166 fsl,pins = <
167 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
168 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
169 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
170 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
171 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
172 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
173 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
174 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
175 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
176 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
177 >;
178 };
179
180 pinctrl_usdhc2: usdhc2grp {
181 fsl,pins = <
182 MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
183 MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
184 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
185 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
186 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
187 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
188 >;
189 };
190
191 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
192 fsl,pins = <
193 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
194 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
195 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
196 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
197 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
198 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
199 >;
200 };
201
202 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
203 fsl,pins = <
204 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
205 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
206 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
207 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
208 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
209 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
210 >;
211 };
212
213 pinctrl_usdhc3: usdhc3grp {
214 fsl,pins = <
215 MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
216 MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
217 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
218 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
219 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
220 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
221 >;
222 };
223
224 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
225 fsl,pins = <
226 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
227 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
228 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
229 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
230 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
231 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
232 >;
233 };
234
235 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
236 fsl,pins = <
237 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
238 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
239 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
240 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
241 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
242 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
243 >;
244 };
Shawn Guo117ccd552013-05-03 11:28:42 +0800245 };
246};
247
Anson Huang4291b642014-01-14 17:30:28 +0800248&kpp {
249 pinctrl-names = "default";
250 pinctrl-0 = <&pinctrl_kpp>;
251 linux,keymap = <
252 MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */
253 MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */
254 MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */
255 MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */
256 MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */
257 MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */
258 MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */
259 MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */
260 >;
261 status = "okay";
262};
263
Shawn Guo117ccd552013-05-03 11:28:42 +0800264&uart1 {
265 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +0800266 pinctrl-0 = <&pinctrl_uart1>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800267 status = "okay";
268};
269
Peter Chen60222322013-09-10 10:23:16 +0800270&usbotg1 {
271 vbus-supply = <&reg_usb_otg1_vbus>;
272 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +0800273 pinctrl-0 = <&pinctrl_usbotg1>;
Peter Chen60222322013-09-10 10:23:16 +0800274 disable-over-current;
275 status = "okay";
276};
277
278&usbotg2 {
279 vbus-supply = <&reg_usb_otg2_vbus>;
280 dr_mode = "host";
281 disable-over-current;
282 status = "okay";
283};
284
Shawn Guo117ccd552013-05-03 11:28:42 +0800285&usdhc1 {
Dong Aishengfa87dfd2013-10-09 19:20:07 +0800286 pinctrl-names = "default", "state_100mhz", "state_200mhz";
Shawn Guofffaa652013-11-04 10:49:04 +0800287 pinctrl-0 = <&pinctrl_usdhc1>;
288 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
289 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800290 bus-width = <8>;
291 cd-gpios = <&gpio4 7 0>;
292 wp-gpios = <&gpio4 6 0>;
293 status = "okay";
294};
295
296&usdhc2 {
Dong Aishengfa87dfd2013-10-09 19:20:07 +0800297 pinctrl-names = "default", "state_100mhz", "state_200mhz";
Shawn Guofffaa652013-11-04 10:49:04 +0800298 pinctrl-0 = <&pinctrl_usdhc2>;
299 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
300 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800301 cd-gpios = <&gpio5 0 0>;
302 wp-gpios = <&gpio4 29 0>;
303 status = "okay";
304};
305
306&usdhc3 {
Dong Aishengfa87dfd2013-10-09 19:20:07 +0800307 pinctrl-names = "default", "state_100mhz", "state_200mhz";
Shawn Guofffaa652013-11-04 10:49:04 +0800308 pinctrl-0 = <&pinctrl_usdhc3>;
309 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
310 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800311 cd-gpios = <&gpio3 22 0>;
312 status = "okay";
313};