blob: ece8b37e51ddde167b44069e80bdfb5c3105fa19 [file] [log] [blame]
Wolfram Sang80872e22010-10-15 12:21:03 +02001/*
2 * Freescale eSDHC controller driver generics for OF and pltfm.
3 *
4 * Copyright (c) 2007 Freescale Semiconductor, Inc.
5 * Copyright (c) 2009 MontaVista Software, Inc.
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <w.sang@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 */
13
14#ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
15#define _DRIVERS_MMC_SDHCI_ESDHC_H
16
17/*
18 * Ops and quirks for the Freescale eSDHC controller.
19 */
20
21#define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
Wolfram Sang80872e22010-10-15 12:21:03 +020022 SDHCI_QUIRK_NO_BUSY_IRQ | \
Wolfram Sang80872e22010-10-15 12:21:03 +020023 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
Yangbo Lu67b589a2015-07-10 11:42:37 +080024 SDHCI_QUIRK_PIO_NEEDS_DELAY | \
25 SDHCI_QUIRK_NO_HISPD_BIT)
Wolfram Sang80872e22010-10-15 12:21:03 +020026
Wolfram Sang80872e22010-10-15 12:21:03 +020027/* pltfm-specific */
28#define ESDHC_HOST_CONTROL_LE 0x20
29
Oded Gabbay66b50a02013-06-27 12:00:05 -040030/*
yangbo lua6b44882016-12-26 17:46:29 +080031 * eSDHC register definition
Oded Gabbay66b50a02013-06-27 12:00:05 -040032 */
Oded Gabbay66b50a02013-06-27 12:00:05 -040033
yangbo lue87d2db2016-12-26 17:46:30 +080034/* Present State Register */
35#define ESDHC_PRSSTAT 0x24
36#define ESDHC_CLOCK_STABLE 0x00000008
37
yangbo lua6b44882016-12-26 17:46:29 +080038/* Protocol Control Register */
39#define ESDHC_PROCTL 0x28
40#define ESDHC_CTRL_4BITBUS (0x1 << 1)
41#define ESDHC_CTRL_8BITBUS (0x2 << 1)
42#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
43#define ESDHC_HOST_CONTROL_RES 0x01
Wolfram Sang80872e22010-10-15 12:21:03 +020044
yangbo lua6b44882016-12-26 17:46:29 +080045/* System Control Register */
46#define ESDHC_SYSTEM_CONTROL 0x2c
47#define ESDHC_CLOCK_MASK 0x0000fff0
48#define ESDHC_PREDIV_SHIFT 8
49#define ESDHC_DIVIDER_SHIFT 4
yangbo lue87d2db2016-12-26 17:46:30 +080050#define ESDHC_CLOCK_SDCLKEN 0x00000008
yangbo lua6b44882016-12-26 17:46:29 +080051#define ESDHC_CLOCK_PEREN 0x00000004
52#define ESDHC_CLOCK_HCKEN 0x00000002
53#define ESDHC_CLOCK_IPGEN 0x00000001
54
55/* Control Register for DMA transfer */
56#define ESDHC_DMA_SYSCTL 0x40c
57#define ESDHC_DMA_SNOOP 0x00000040
Wolfram Sang80872e22010-10-15 12:21:03 +020058
Wolfram Sang80872e22010-10-15 12:21:03 +020059#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */