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Andrew Lunn406a4362019-04-27 19:32:56 +02001// SPDX-License-Identifier: GPL-2.0+
Lennert Buytenhek2e16a772008-10-07 13:46:22 +00002/*
3 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
Lennert Buytenheke84665c2009-03-20 09:52:09 +00004 * Copyright (c) 2008-2009 Marvell Semiconductor
Lennert Buytenhek2e16a772008-10-07 13:46:22 +00005 */
6
Barry Grussling19b2f972013-01-08 16:05:54 +00007#include <linux/delay.h>
Vivien Didelot56c3ff92017-10-13 14:18:07 -04008#include <linux/etherdevice.h>
Barry Grussling19b2f972013-01-08 16:05:54 +00009#include <linux/jiffies.h>
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000010#include <linux/list.h>
Paul Gortmaker2bbba272012-01-24 10:41:40 +000011#include <linux/module.h>
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000012#include <linux/netdevice.h>
13#include <linux/phy.h>
Ben Hutchingsc8f0b862011-11-27 17:06:08 +000014#include <net/dsa.h>
Neil Armstrong6a4b2982015-11-10 16:51:36 +010015#include "mv88e6060.h"
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000016
17static int reg_read(struct dsa_switch *ds, int addr, int reg)
18{
Vivien Didelot04bed142016-08-31 18:06:13 -040019 struct mv88e6060_priv *priv = ds->priv;
Guenter Roeckb184e492014-10-17 12:30:58 -070020
Andrew Lunna77d43f2016-04-13 02:40:42 +020021 return mdiobus_read_nested(priv->bus, priv->sw_addr + addr, reg);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000022}
23
24#define REG_READ(addr, reg) \
25 ({ \
26 int __ret; \
27 \
28 __ret = reg_read(ds, addr, reg); \
29 if (__ret < 0) \
30 return __ret; \
31 __ret; \
32 })
33
34
35static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
36{
Vivien Didelot04bed142016-08-31 18:06:13 -040037 struct mv88e6060_priv *priv = ds->priv;
Guenter Roeckb184e492014-10-17 12:30:58 -070038
Andrew Lunna77d43f2016-04-13 02:40:42 +020039 return mdiobus_write_nested(priv->bus, priv->sw_addr + addr, reg, val);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000040}
41
42#define REG_WRITE(addr, reg, val) \
43 ({ \
44 int __ret; \
45 \
46 __ret = reg_write(ds, addr, reg, val); \
47 if (__ret < 0) \
48 return __ret; \
49 })
50
Vivien Didelot0209d142016-04-17 13:23:55 -040051static const char *mv88e6060_get_name(struct mii_bus *bus, int sw_addr)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000052{
53 int ret;
54
Neil Armstrong6a4b2982015-11-10 16:51:36 +010055 ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000056 if (ret >= 0) {
Neil Armstrong6a4b2982015-11-10 16:51:36 +010057 if (ret == PORT_SWITCH_ID_6060)
Guenter Roeck3de6aa4c2014-10-29 10:44:54 -070058 return "Marvell 88E6060 (A0)";
Neil Armstrong6a4b2982015-11-10 16:51:36 +010059 if (ret == PORT_SWITCH_ID_6060_R1 ||
60 ret == PORT_SWITCH_ID_6060_R2)
Guenter Roeck3de6aa4c2014-10-29 10:44:54 -070061 return "Marvell 88E6060 (B0)";
Neil Armstrong6a4b2982015-11-10 16:51:36 +010062 if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000063 return "Marvell 88E6060";
64 }
65
66 return NULL;
67}
68
Florian Fainelli5ed4e3e2017-11-10 15:22:52 -080069static enum dsa_tag_protocol mv88e6060_get_tag_protocol(struct dsa_switch *ds,
70 int port)
Andrew Lunn7b314362016-08-22 16:01:01 +020071{
72 return DSA_TAG_PROTO_TRAILER;
73}
74
Vivien Didelot0209d142016-04-17 13:23:55 -040075static const char *mv88e6060_drv_probe(struct device *dsa_dev,
76 struct device *host_dev, int sw_addr,
77 void **_priv)
Andrew Lunna77d43f2016-04-13 02:40:42 +020078{
79 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
80 struct mv88e6060_priv *priv;
Vivien Didelot0209d142016-04-17 13:23:55 -040081 const char *name;
Andrew Lunna77d43f2016-04-13 02:40:42 +020082
83 name = mv88e6060_get_name(bus, sw_addr);
84 if (name) {
85 priv = devm_kzalloc(dsa_dev, sizeof(*priv), GFP_KERNEL);
86 if (!priv)
87 return NULL;
88 *_priv = priv;
89 priv->bus = bus;
90 priv->sw_addr = sw_addr;
91 }
92
93 return name;
94}
95
Lennert Buytenhek2e16a772008-10-07 13:46:22 +000096static int mv88e6060_switch_reset(struct dsa_switch *ds)
97{
98 int i;
99 int ret;
Barry Grussling19b2f972013-01-08 16:05:54 +0000100 unsigned long timeout;
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000101
Barry Grussling3675c8d2013-01-08 16:05:53 +0000102 /* Set all ports to the disabled state. */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100103 for (i = 0; i < MV88E6060_PORTS; i++) {
104 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
105 REG_WRITE(REG_PORT(i), PORT_CONTROL,
106 ret & ~PORT_CONTROL_STATE_MASK);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000107 }
108
Barry Grussling3675c8d2013-01-08 16:05:53 +0000109 /* Wait for transmit queues to drain. */
Barry Grussling19b2f972013-01-08 16:05:54 +0000110 usleep_range(2000, 4000);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000111
Barry Grussling3675c8d2013-01-08 16:05:53 +0000112 /* Reset the switch. */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100113 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
114 GLOBAL_ATU_CONTROL_SWRESET |
Anderson Luiz Alvesa7451562018-11-30 21:58:36 -0200115 GLOBAL_ATU_CONTROL_LEARNDIS);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000116
Barry Grussling3675c8d2013-01-08 16:05:53 +0000117 /* Wait up to one second for reset to complete. */
Barry Grussling19b2f972013-01-08 16:05:54 +0000118 timeout = jiffies + 1 * HZ;
119 while (time_before(jiffies, timeout)) {
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100120 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
121 if (ret & GLOBAL_STATUS_INIT_READY)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000122 break;
123
Barry Grussling19b2f972013-01-08 16:05:54 +0000124 usleep_range(1000, 2000);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000125 }
Barry Grussling19b2f972013-01-08 16:05:54 +0000126 if (time_after(jiffies, timeout))
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000127 return -ETIMEDOUT;
128
129 return 0;
130}
131
132static int mv88e6060_setup_global(struct dsa_switch *ds)
133{
Barry Grussling3675c8d2013-01-08 16:05:53 +0000134 /* Disable discarding of frames with excessive collisions,
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000135 * set the maximum frame size to 1536 bytes, and mask all
136 * interrupt sources.
137 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100138 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000139
Anderson Luiz Alvesa7451562018-11-30 21:58:36 -0200140 /* Disable automatic address learning.
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000141 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100142 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
Anderson Luiz Alvesa7451562018-11-30 21:58:36 -0200143 GLOBAL_ATU_CONTROL_LEARNDIS);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000144
145 return 0;
146}
147
148static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
149{
150 int addr = REG_PORT(p);
151
Barry Grussling3675c8d2013-01-08 16:05:53 +0000152 /* Do not force flow control, disable Ingress and Egress
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000153 * Header tagging, disable VLAN tunneling, and set the port
154 * state to Forwarding. Additionally, if this is the CPU
155 * port, enable Ingress and Egress Trailer tagging mode.
156 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100157 REG_WRITE(addr, PORT_CONTROL,
158 dsa_is_cpu_port(ds, p) ?
159 PORT_CONTROL_TRAILER |
160 PORT_CONTROL_INGRESS_MODE |
161 PORT_CONTROL_STATE_FORWARDING :
162 PORT_CONTROL_STATE_FORWARDING);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000163
Barry Grussling3675c8d2013-01-08 16:05:53 +0000164 /* Port based VLAN map: give each port its own address
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000165 * database, allow the CPU port to talk to each of the 'real'
166 * ports, and allow each of the 'real' ports to only talk to
167 * the CPU port.
168 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100169 REG_WRITE(addr, PORT_VLAN_MAP,
170 ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
Vivien Didelot02bc6e52017-10-26 11:22:56 -0400171 (dsa_is_cpu_port(ds, p) ? dsa_user_ports(ds) :
172 BIT(dsa_to_port(ds, p)->cpu_dp->index)));
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000173
Barry Grussling3675c8d2013-01-08 16:05:53 +0000174 /* Port Association Vector: when learning source addresses
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000175 * of packets, add the address to the address database using
176 * a port bitmap that has only the bit for this port set and
177 * the other bits clear.
178 */
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100179 REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p));
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000180
181 return 0;
182}
183
Vivien Didelot56c3ff92017-10-13 14:18:07 -0400184static int mv88e6060_setup_addr(struct dsa_switch *ds)
185{
186 u8 addr[ETH_ALEN];
187 u16 val;
188
189 eth_random_addr(addr);
190
191 val = addr[0] << 8 | addr[1];
192
193 /* The multicast bit is always transmitted as a zero, so the switch uses
194 * bit 8 for "DiffAddr", where 0 means all ports transmit the same SA.
195 */
196 val &= 0xfeff;
197
198 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, val);
199 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
200 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
201
202 return 0;
203}
204
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000205static int mv88e6060_setup(struct dsa_switch *ds)
206{
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000207 int ret;
Andrew Lunna77d43f2016-04-13 02:40:42 +0200208 int i;
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000209
210 ret = mv88e6060_switch_reset(ds);
211 if (ret < 0)
212 return ret;
213
214 /* @@@ initialise atu */
215
216 ret = mv88e6060_setup_global(ds);
217 if (ret < 0)
218 return ret;
219
Vivien Didelot56c3ff92017-10-13 14:18:07 -0400220 ret = mv88e6060_setup_addr(ds);
221 if (ret < 0)
222 return ret;
223
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100224 for (i = 0; i < MV88E6060_PORTS; i++) {
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000225 ret = mv88e6060_setup_port(ds, i);
226 if (ret < 0)
227 return ret;
228 }
229
230 return 0;
231}
232
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000233static int mv88e6060_port_to_phy_addr(int port)
234{
Neil Armstrong6a4b2982015-11-10 16:51:36 +0100235 if (port >= 0 && port < MV88E6060_PORTS)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000236 return port;
237 return -1;
238}
239
240static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
241{
242 int addr;
243
244 addr = mv88e6060_port_to_phy_addr(port);
245 if (addr == -1)
246 return 0xffff;
247
248 return reg_read(ds, addr, regnum);
249}
250
251static int
252mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
253{
254 int addr;
255
256 addr = mv88e6060_port_to_phy_addr(port);
257 if (addr == -1)
258 return 0xffff;
259
260 return reg_write(ds, addr, regnum, val);
261}
262
Florian Fainellia82f67a2017-01-08 14:52:08 -0800263static const struct dsa_switch_ops mv88e6060_switch_ops = {
Andrew Lunn7b314362016-08-22 16:01:01 +0200264 .get_tag_protocol = mv88e6060_get_tag_protocol,
Andrew Lunne49bad32016-04-13 02:40:43 +0200265 .probe = mv88e6060_drv_probe,
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000266 .setup = mv88e6060_setup,
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000267 .phy_read = mv88e6060_phy_read,
268 .phy_write = mv88e6060_phy_write,
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000269};
270
Florian Fainelliab3d4082017-01-08 14:52:07 -0800271static struct dsa_switch_driver mv88e6060_switch_drv = {
272 .ops = &mv88e6060_switch_ops,
273};
274
Roel Kluin5eaa65b2008-12-10 15:18:31 -0800275static int __init mv88e6060_init(void)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000276{
Florian Fainelliab3d4082017-01-08 14:52:07 -0800277 register_switch_driver(&mv88e6060_switch_drv);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000278 return 0;
279}
280module_init(mv88e6060_init);
281
Roel Kluin5eaa65b2008-12-10 15:18:31 -0800282static void __exit mv88e6060_cleanup(void)
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000283{
Florian Fainelliab3d4082017-01-08 14:52:07 -0800284 unregister_switch_driver(&mv88e6060_switch_drv);
Lennert Buytenhek2e16a772008-10-07 13:46:22 +0000285}
286module_exit(mv88e6060_cleanup);
Ben Hutchings3d825ed2011-11-25 14:37:16 +0000287
288MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
289MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
290MODULE_LICENSE("GPL");
291MODULE_ALIAS("platform:mv88e6060");