Thomas Gleixner | 2874c5f | 2019-05-27 08:55:01 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 2 | /* |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 3 | * Copyright (C) 2002 Paul Mackerras, IBM Corp. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 4 | */ |
| 5 | #include <asm/processor.h> |
| 6 | #include <asm/ppc_asm.h> |
Al Viro | 9445aa1 | 2016-01-13 23:33:46 -0500 | [diff] [blame] | 7 | #include <asm/export.h> |
Christophe Leroy | ec0c464 | 2018-07-05 16:24:57 +0000 | [diff] [blame] | 8 | #include <asm/asm-compat.h> |
Christophe Leroy | 2c86cd1 | 2018-07-05 16:25:01 +0000 | [diff] [blame] | 9 | #include <asm/feature-fixups.h> |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 10 | |
Paul Mackerras | 98c45f5 | 2018-08-03 20:13:04 +1000 | [diff] [blame] | 11 | #ifndef SELFTEST_CASE |
| 12 | /* 0 == most CPUs, 1 == POWER6, 2 == Cell */ |
| 13 | #define SELFTEST_CASE 0 |
| 14 | #endif |
| 15 | |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 16 | #ifdef __BIG_ENDIAN__ |
| 17 | #define sLd sld /* Shift towards low-numbered address. */ |
| 18 | #define sHd srd /* Shift towards high-numbered address. */ |
| 19 | #else |
| 20 | #define sLd srd /* Shift towards low-numbered address. */ |
| 21 | #define sHd sld /* Shift towards high-numbered address. */ |
| 22 | #endif |
| 23 | |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 24 | /* |
| 25 | * These macros are used to generate exception table entries. |
| 26 | * The exception handlers below use the original arguments |
| 27 | * (stored on the stack) and the point where we're up to in |
| 28 | * the destination buffer, i.e. the address of the first |
| 29 | * unmodified byte. Generally r3 points into the destination |
| 30 | * buffer, but the first unmodified byte is at a variable |
| 31 | * offset from r3. In the code below, the symbol r3_offset |
| 32 | * is set to indicate the current offset at each point in |
| 33 | * the code. This offset is then used as a negative offset |
| 34 | * from the exception handler code, and those instructions |
| 35 | * before the exception handlers are addi instructions that |
| 36 | * adjust r3 to point to the correct place. |
| 37 | */ |
| 38 | .macro lex /* exception handler for load */ |
| 39 | 100: EX_TABLE(100b, .Lld_exc - r3_offset) |
| 40 | .endm |
| 41 | |
| 42 | .macro stex /* exception handler for store */ |
| 43 | 100: EX_TABLE(100b, .Lst_exc - r3_offset) |
| 44 | .endm |
| 45 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 46 | .align 7 |
Anton Blanchard | 169c7ce | 2014-04-03 16:01:11 +1100 | [diff] [blame] | 47 | _GLOBAL_TOC(__copy_tofrom_user) |
Nicholas Piggin | 15a3204 | 2018-02-21 05:08:26 +1000 | [diff] [blame] | 48 | #ifdef CONFIG_PPC_BOOK3S_64 |
Anton Blanchard | a66086b | 2011-12-07 20:11:45 +0000 | [diff] [blame] | 49 | BEGIN_FTR_SECTION |
| 50 | nop |
| 51 | FTR_SECTION_ELSE |
| 52 | b __copy_tofrom_user_power7 |
| 53 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY) |
Nicholas Piggin | 15a3204 | 2018-02-21 05:08:26 +1000 | [diff] [blame] | 54 | #endif |
Anton Blanchard | a66086b | 2011-12-07 20:11:45 +0000 | [diff] [blame] | 55 | _GLOBAL(__copy_tofrom_user_base) |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 56 | /* first check for a 4kB copy on a 4kB boundary */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 57 | cmpldi cr1,r5,16 |
| 58 | cmpdi cr6,r5,4096 |
| 59 | or r0,r3,r4 |
| 60 | neg r6,r3 /* LS 3 bits = # bytes to 8-byte dest bdry */ |
| 61 | andi. r0,r0,4095 |
| 62 | std r3,-24(r1) |
| 63 | crand cr0*4+2,cr0*4+2,cr6*4+2 |
| 64 | std r4,-16(r1) |
| 65 | std r5,-8(r1) |
| 66 | dcbt 0,r4 |
Benjamin Herrenschmidt | 3c726f8 | 2005-11-07 11:06:55 +1100 | [diff] [blame] | 67 | beq .Lcopy_page_4K |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 68 | andi. r6,r6,7 |
Anton Blanchard | 694caf0 | 2012-04-18 02:21:52 +0000 | [diff] [blame] | 69 | PPC_MTOCRF(0x01,r5) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 70 | blt cr1,.Lshort_copy |
Mark Nelson | a4e22f0 | 2008-11-11 00:53:34 +0000 | [diff] [blame] | 71 | /* Below we want to nop out the bne if we're on a CPU that has the |
| 72 | * CPU_FTR_UNALIGNED_LD_STD bit set and the CPU_FTR_CP_USE_DCBTZ bit |
| 73 | * cleared. |
| 74 | * At the time of writing the only CPU that has this combination of bits |
| 75 | * set is Power6. |
| 76 | */ |
Paul Mackerras | 98c45f5 | 2018-08-03 20:13:04 +1000 | [diff] [blame] | 77 | test_feature = (SELFTEST_CASE == 1) |
Mark Nelson | a4e22f0 | 2008-11-11 00:53:34 +0000 | [diff] [blame] | 78 | BEGIN_FTR_SECTION |
| 79 | nop |
| 80 | FTR_SECTION_ELSE |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 81 | bne .Ldst_unaligned |
Mark Nelson | a4e22f0 | 2008-11-11 00:53:34 +0000 | [diff] [blame] | 82 | ALT_FTR_SECTION_END(CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_CP_USE_DCBTZ, \ |
| 83 | CPU_FTR_UNALIGNED_LD_STD) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 84 | .Ldst_aligned: |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 85 | addi r3,r3,-16 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 86 | r3_offset = 16 |
Paul Mackerras | 98c45f5 | 2018-08-03 20:13:04 +1000 | [diff] [blame] | 87 | test_feature = (SELFTEST_CASE == 0) |
Mark Nelson | a4e22f0 | 2008-11-11 00:53:34 +0000 | [diff] [blame] | 88 | BEGIN_FTR_SECTION |
| 89 | andi. r0,r4,7 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 90 | bne .Lsrc_unaligned |
Mark Nelson | a4e22f0 | 2008-11-11 00:53:34 +0000 | [diff] [blame] | 91 | END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD) |
Anton Blanchard | 789c299 | 2010-02-10 14:56:26 +0000 | [diff] [blame] | 92 | blt cr1,.Ldo_tail /* if < 16 bytes to copy */ |
| 93 | srdi r0,r5,5 |
| 94 | cmpdi cr1,r0,0 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 95 | lex; ld r7,0(r4) |
| 96 | lex; ld r6,8(r4) |
Anton Blanchard | 789c299 | 2010-02-10 14:56:26 +0000 | [diff] [blame] | 97 | addi r4,r4,16 |
| 98 | mtctr r0 |
| 99 | andi. r0,r5,0x10 |
| 100 | beq 22f |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 101 | addi r3,r3,16 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 102 | r3_offset = 0 |
Anton Blanchard | 789c299 | 2010-02-10 14:56:26 +0000 | [diff] [blame] | 103 | addi r4,r4,-16 |
| 104 | mr r9,r7 |
| 105 | mr r8,r6 |
| 106 | beq cr1,72f |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 107 | 21: |
| 108 | lex; ld r7,16(r4) |
| 109 | lex; ld r6,24(r4) |
Anton Blanchard | 789c299 | 2010-02-10 14:56:26 +0000 | [diff] [blame] | 110 | addi r4,r4,32 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 111 | stex; std r9,0(r3) |
| 112 | r3_offset = 8 |
| 113 | stex; std r8,8(r3) |
| 114 | r3_offset = 16 |
| 115 | 22: |
| 116 | lex; ld r9,0(r4) |
| 117 | lex; ld r8,8(r4) |
| 118 | stex; std r7,16(r3) |
| 119 | r3_offset = 24 |
| 120 | stex; std r6,24(r3) |
Anton Blanchard | 789c299 | 2010-02-10 14:56:26 +0000 | [diff] [blame] | 121 | addi r3,r3,32 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 122 | r3_offset = 0 |
Anton Blanchard | 789c299 | 2010-02-10 14:56:26 +0000 | [diff] [blame] | 123 | bdnz 21b |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 124 | 72: |
| 125 | stex; std r9,0(r3) |
| 126 | r3_offset = 8 |
| 127 | stex; std r8,8(r3) |
| 128 | r3_offset = 16 |
Anton Blanchard | 789c299 | 2010-02-10 14:56:26 +0000 | [diff] [blame] | 129 | andi. r5,r5,0xf |
| 130 | beq+ 3f |
| 131 | addi r4,r4,16 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 132 | .Ldo_tail: |
Anton Blanchard | 789c299 | 2010-02-10 14:56:26 +0000 | [diff] [blame] | 133 | addi r3,r3,16 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 134 | r3_offset = 0 |
Anton Blanchard | 789c299 | 2010-02-10 14:56:26 +0000 | [diff] [blame] | 135 | bf cr7*4+0,246f |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 136 | lex; ld r9,0(r4) |
Anton Blanchard | 789c299 | 2010-02-10 14:56:26 +0000 | [diff] [blame] | 137 | addi r4,r4,8 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 138 | stex; std r9,0(r3) |
Anton Blanchard | 789c299 | 2010-02-10 14:56:26 +0000 | [diff] [blame] | 139 | addi r3,r3,8 |
| 140 | 246: bf cr7*4+1,1f |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 141 | lex; lwz r9,0(r4) |
Mark Nelson | f72b728 | 2009-02-25 13:46:24 +0000 | [diff] [blame] | 142 | addi r4,r4,4 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 143 | stex; stw r9,0(r3) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 144 | addi r3,r3,4 |
| 145 | 1: bf cr7*4+2,2f |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 146 | lex; lhz r9,0(r4) |
Mark Nelson | f72b728 | 2009-02-25 13:46:24 +0000 | [diff] [blame] | 147 | addi r4,r4,2 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 148 | stex; sth r9,0(r3) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 149 | addi r3,r3,2 |
| 150 | 2: bf cr7*4+3,3f |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 151 | lex; lbz r9,0(r4) |
| 152 | stex; stb r9,0(r3) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 153 | 3: li r3,0 |
| 154 | blr |
| 155 | |
| 156 | .Lsrc_unaligned: |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 157 | r3_offset = 16 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 158 | srdi r6,r5,3 |
| 159 | addi r5,r5,-16 |
| 160 | subf r4,r0,r4 |
| 161 | srdi r7,r5,4 |
| 162 | sldi r10,r0,3 |
| 163 | cmpldi cr6,r6,3 |
| 164 | andi. r5,r5,7 |
| 165 | mtctr r7 |
| 166 | subfic r11,r10,64 |
| 167 | add r5,r5,r0 |
| 168 | bt cr7*4+0,28f |
| 169 | |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 170 | lex; ld r9,0(r4) /* 3+2n loads, 2+2n stores */ |
| 171 | lex; ld r0,8(r4) |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 172 | sLd r6,r9,r10 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 173 | lex; ldu r9,16(r4) |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 174 | sHd r7,r0,r11 |
| 175 | sLd r8,r0,r10 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 176 | or r7,r7,r6 |
| 177 | blt cr6,79f |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 178 | lex; ld r0,8(r4) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 179 | b 2f |
| 180 | |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 181 | 28: |
| 182 | lex; ld r0,0(r4) /* 4+2n loads, 3+2n stores */ |
| 183 | lex; ldu r9,8(r4) |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 184 | sLd r8,r0,r10 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 185 | addi r3,r3,-8 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 186 | r3_offset = 24 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 187 | blt cr6,5f |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 188 | lex; ld r0,8(r4) |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 189 | sHd r12,r9,r11 |
| 190 | sLd r6,r9,r10 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 191 | lex; ldu r9,16(r4) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 192 | or r12,r8,r12 |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 193 | sHd r7,r0,r11 |
| 194 | sLd r8,r0,r10 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 195 | addi r3,r3,16 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 196 | r3_offset = 8 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 197 | beq cr6,78f |
| 198 | |
| 199 | 1: or r7,r7,r6 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 200 | lex; ld r0,8(r4) |
| 201 | stex; std r12,8(r3) |
| 202 | r3_offset = 16 |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 203 | 2: sHd r12,r9,r11 |
| 204 | sLd r6,r9,r10 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 205 | lex; ldu r9,16(r4) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 206 | or r12,r8,r12 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 207 | stex; stdu r7,16(r3) |
| 208 | r3_offset = 8 |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 209 | sHd r7,r0,r11 |
| 210 | sLd r8,r0,r10 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 211 | bdnz 1b |
| 212 | |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 213 | 78: |
| 214 | stex; std r12,8(r3) |
| 215 | r3_offset = 16 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 216 | or r7,r7,r6 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 217 | 79: |
| 218 | stex; std r7,16(r3) |
| 219 | r3_offset = 24 |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 220 | 5: sHd r12,r9,r11 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 221 | or r12,r8,r12 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 222 | stex; std r12,24(r3) |
| 223 | r3_offset = 32 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 224 | bne 6f |
| 225 | li r3,0 |
| 226 | blr |
| 227 | 6: cmpwi cr1,r5,8 |
| 228 | addi r3,r3,32 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 229 | r3_offset = 0 |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 230 | sLd r9,r9,r10 |
Mark Nelson | f72b728 | 2009-02-25 13:46:24 +0000 | [diff] [blame] | 231 | ble cr1,7f |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 232 | lex; ld r0,8(r4) |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 233 | sHd r7,r0,r11 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 234 | or r9,r7,r9 |
Mark Nelson | f72b728 | 2009-02-25 13:46:24 +0000 | [diff] [blame] | 235 | 7: |
| 236 | bf cr7*4+1,1f |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 237 | #ifdef __BIG_ENDIAN__ |
Mark Nelson | f72b728 | 2009-02-25 13:46:24 +0000 | [diff] [blame] | 238 | rotldi r9,r9,32 |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 239 | #endif |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 240 | stex; stw r9,0(r3) |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 241 | #ifdef __LITTLE_ENDIAN__ |
| 242 | rotrdi r9,r9,32 |
| 243 | #endif |
Mark Nelson | f72b728 | 2009-02-25 13:46:24 +0000 | [diff] [blame] | 244 | addi r3,r3,4 |
| 245 | 1: bf cr7*4+2,2f |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 246 | #ifdef __BIG_ENDIAN__ |
Mark Nelson | f72b728 | 2009-02-25 13:46:24 +0000 | [diff] [blame] | 247 | rotldi r9,r9,16 |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 248 | #endif |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 249 | stex; sth r9,0(r3) |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 250 | #ifdef __LITTLE_ENDIAN__ |
| 251 | rotrdi r9,r9,16 |
| 252 | #endif |
Mark Nelson | f72b728 | 2009-02-25 13:46:24 +0000 | [diff] [blame] | 253 | addi r3,r3,2 |
| 254 | 2: bf cr7*4+3,3f |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 255 | #ifdef __BIG_ENDIAN__ |
Mark Nelson | f72b728 | 2009-02-25 13:46:24 +0000 | [diff] [blame] | 256 | rotldi r9,r9,8 |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 257 | #endif |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 258 | stex; stb r9,0(r3) |
Paul E. McKenney | 2015116 | 2013-12-18 09:29:57 +1100 | [diff] [blame] | 259 | #ifdef __LITTLE_ENDIAN__ |
| 260 | rotrdi r9,r9,8 |
| 261 | #endif |
Mark Nelson | f72b728 | 2009-02-25 13:46:24 +0000 | [diff] [blame] | 262 | 3: li r3,0 |
| 263 | blr |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 264 | |
| 265 | .Ldst_unaligned: |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 266 | r3_offset = 0 |
Anton Blanchard | 694caf0 | 2012-04-18 02:21:52 +0000 | [diff] [blame] | 267 | PPC_MTOCRF(0x01,r6) /* put #bytes to 8B bdry into cr7 */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 268 | subf r5,r6,r5 |
| 269 | li r7,0 |
Mark Nelson | a4e22f0 | 2008-11-11 00:53:34 +0000 | [diff] [blame] | 270 | cmpldi cr1,r5,16 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 271 | bf cr7*4+3,1f |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 272 | 100: EX_TABLE(100b, .Lld_exc_r7) |
| 273 | lbz r0,0(r4) |
| 274 | 100: EX_TABLE(100b, .Lst_exc_r7) |
| 275 | stb r0,0(r3) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 276 | addi r7,r7,1 |
| 277 | 1: bf cr7*4+2,2f |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 278 | 100: EX_TABLE(100b, .Lld_exc_r7) |
| 279 | lhzx r0,r7,r4 |
| 280 | 100: EX_TABLE(100b, .Lst_exc_r7) |
| 281 | sthx r0,r7,r3 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 282 | addi r7,r7,2 |
| 283 | 2: bf cr7*4+1,3f |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 284 | 100: EX_TABLE(100b, .Lld_exc_r7) |
| 285 | lwzx r0,r7,r4 |
| 286 | 100: EX_TABLE(100b, .Lst_exc_r7) |
| 287 | stwx r0,r7,r3 |
Anton Blanchard | 694caf0 | 2012-04-18 02:21:52 +0000 | [diff] [blame] | 288 | 3: PPC_MTOCRF(0x01,r5) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 289 | add r4,r6,r4 |
| 290 | add r3,r6,r3 |
| 291 | b .Ldst_aligned |
| 292 | |
| 293 | .Lshort_copy: |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 294 | r3_offset = 0 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 295 | bf cr7*4+0,1f |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 296 | lex; lwz r0,0(r4) |
| 297 | lex; lwz r9,4(r4) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 298 | addi r4,r4,8 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 299 | stex; stw r0,0(r3) |
| 300 | stex; stw r9,4(r3) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 301 | addi r3,r3,8 |
| 302 | 1: bf cr7*4+1,2f |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 303 | lex; lwz r0,0(r4) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 304 | addi r4,r4,4 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 305 | stex; stw r0,0(r3) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 306 | addi r3,r3,4 |
| 307 | 2: bf cr7*4+2,3f |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 308 | lex; lhz r0,0(r4) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 309 | addi r4,r4,2 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 310 | stex; sth r0,0(r3) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 311 | addi r3,r3,2 |
| 312 | 3: bf cr7*4+3,4f |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 313 | lex; lbz r0,0(r4) |
| 314 | stex; stb r0,0(r3) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 315 | 4: li r3,0 |
| 316 | blr |
| 317 | |
| 318 | /* |
| 319 | * exception handlers follow |
| 320 | * we have to return the number of bytes not copied |
| 321 | * for an exception on a load, we set the rest of the destination to 0 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 322 | * Note that the number of bytes of instructions for adjusting r3 needs |
| 323 | * to equal the amount of the adjustment, due to the trick of using |
| 324 | * .Lld_exc - r3_offset as the handler address. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 325 | */ |
| 326 | |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 327 | .Lld_exc_r7: |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 328 | add r3,r3,r7 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 329 | b .Lld_exc |
| 330 | |
| 331 | /* adjust by 24 */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 332 | addi r3,r3,8 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 333 | nop |
| 334 | /* adjust by 16 */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 335 | addi r3,r3,8 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 336 | nop |
| 337 | /* adjust by 8 */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 338 | addi r3,r3,8 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 339 | nop |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 340 | |
| 341 | /* |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 342 | * Here we have had a fault on a load and r3 points to the first |
| 343 | * unmodified byte of the destination. We use the original arguments |
| 344 | * and r3 to work out how much wasn't copied. Since we load some |
| 345 | * distance ahead of the stores, we continue copying byte-by-byte until |
| 346 | * we hit the load fault again in order to copy as much as possible. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 347 | */ |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 348 | .Lld_exc: |
| 349 | ld r6,-24(r1) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 350 | ld r4,-16(r1) |
| 351 | ld r5,-8(r1) |
| 352 | subf r6,r6,r3 |
| 353 | add r4,r4,r6 |
| 354 | subf r5,r6,r5 /* #bytes left to go */ |
| 355 | |
| 356 | /* |
| 357 | * first see if we can copy any more bytes before hitting another exception |
| 358 | */ |
| 359 | mtctr r5 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 360 | r3_offset = 0 |
| 361 | 100: EX_TABLE(100b, .Ldone) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 362 | 43: lbz r0,0(r4) |
| 363 | addi r4,r4,1 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 364 | stex; stb r0,0(r3) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 365 | addi r3,r3,1 |
| 366 | bdnz 43b |
| 367 | li r3,0 /* huh? all copied successfully this time? */ |
| 368 | blr |
| 369 | |
| 370 | /* |
Al Viro | 3448890 | 2017-03-21 16:35:08 -0400 | [diff] [blame] | 371 | * here we have trapped again, amount remaining is in ctr. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 372 | */ |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 373 | .Ldone: |
| 374 | mfctr r3 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 375 | blr |
| 376 | |
| 377 | /* |
Paul Mackerras | f8db200 | 2018-08-03 20:13:06 +1000 | [diff] [blame] | 378 | * exception handlers for stores: we need to work out how many bytes |
| 379 | * weren't copied, and we may need to copy some more. |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 380 | * Note that the number of bytes of instructions for adjusting r3 needs |
| 381 | * to equal the amount of the adjustment, due to the trick of using |
| 382 | * .Lst_exc - r3_offset as the handler address. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 383 | */ |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 384 | .Lst_exc_r7: |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 385 | add r3,r3,r7 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 386 | b .Lst_exc |
| 387 | |
| 388 | /* adjust by 24 */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 389 | addi r3,r3,8 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 390 | nop |
| 391 | /* adjust by 16 */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 392 | addi r3,r3,8 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 393 | nop |
| 394 | /* adjust by 8 */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 395 | addi r3,r3,4 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 396 | /* adjust by 4 */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 397 | addi r3,r3,4 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 398 | .Lst_exc: |
Paul Mackerras | f8db200 | 2018-08-03 20:13:06 +1000 | [diff] [blame] | 399 | ld r6,-24(r1) /* original destination pointer */ |
| 400 | ld r4,-16(r1) /* original source pointer */ |
| 401 | ld r5,-8(r1) /* original number of bytes */ |
| 402 | add r7,r6,r5 |
| 403 | /* |
| 404 | * If the destination pointer isn't 8-byte aligned, |
| 405 | * we may have got the exception as a result of a |
| 406 | * store that overlapped a page boundary, so we may be |
| 407 | * able to copy a few more bytes. |
| 408 | */ |
| 409 | 17: andi. r0,r3,7 |
| 410 | beq 19f |
| 411 | subf r8,r6,r3 /* #bytes copied */ |
| 412 | 100: EX_TABLE(100b,19f) |
| 413 | lbzx r0,r8,r4 |
| 414 | 100: EX_TABLE(100b,19f) |
| 415 | stb r0,0(r3) |
| 416 | addi r3,r3,1 |
| 417 | cmpld r3,r7 |
| 418 | blt 17b |
| 419 | 19: subf r3,r3,r7 /* #bytes not copied in r3 */ |
Al Viro | 3448890 | 2017-03-21 16:35:08 -0400 | [diff] [blame] | 420 | blr |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 421 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 422 | /* |
| 423 | * Routine to copy a whole page of data, optimized for POWER4. |
| 424 | * On POWER4 it is more than 50% faster than the simple loop |
Michael Ellerman | 0f36910 | 2014-07-10 12:29:24 +1000 | [diff] [blame] | 425 | * above (following the .Ldst_aligned label). |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 426 | */ |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 427 | .macro exc |
| 428 | 100: EX_TABLE(100b, .Labort) |
| 429 | .endm |
Benjamin Herrenschmidt | 3c726f8 | 2005-11-07 11:06:55 +1100 | [diff] [blame] | 430 | .Lcopy_page_4K: |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 431 | std r31,-32(1) |
| 432 | std r30,-40(1) |
| 433 | std r29,-48(1) |
| 434 | std r28,-56(1) |
| 435 | std r27,-64(1) |
| 436 | std r26,-72(1) |
| 437 | std r25,-80(1) |
| 438 | std r24,-88(1) |
| 439 | std r23,-96(1) |
| 440 | std r22,-104(1) |
| 441 | std r21,-112(1) |
| 442 | std r20,-120(1) |
| 443 | li r5,4096/32 - 1 |
| 444 | addi r3,r3,-8 |
| 445 | li r0,5 |
| 446 | 0: addi r5,r5,-24 |
| 447 | mtctr r0 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 448 | exc; ld r22,640(4) |
| 449 | exc; ld r21,512(4) |
| 450 | exc; ld r20,384(4) |
| 451 | exc; ld r11,256(4) |
| 452 | exc; ld r9,128(4) |
| 453 | exc; ld r7,0(4) |
| 454 | exc; ld r25,648(4) |
| 455 | exc; ld r24,520(4) |
| 456 | exc; ld r23,392(4) |
| 457 | exc; ld r10,264(4) |
| 458 | exc; ld r8,136(4) |
| 459 | exc; ldu r6,8(4) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 460 | cmpwi r5,24 |
| 461 | 1: |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 462 | exc; std r22,648(3) |
| 463 | exc; std r21,520(3) |
| 464 | exc; std r20,392(3) |
| 465 | exc; std r11,264(3) |
| 466 | exc; std r9,136(3) |
| 467 | exc; std r7,8(3) |
| 468 | exc; ld r28,648(4) |
| 469 | exc; ld r27,520(4) |
| 470 | exc; ld r26,392(4) |
| 471 | exc; ld r31,264(4) |
| 472 | exc; ld r30,136(4) |
| 473 | exc; ld r29,8(4) |
| 474 | exc; std r25,656(3) |
| 475 | exc; std r24,528(3) |
| 476 | exc; std r23,400(3) |
| 477 | exc; std r10,272(3) |
| 478 | exc; std r8,144(3) |
| 479 | exc; std r6,16(3) |
| 480 | exc; ld r22,656(4) |
| 481 | exc; ld r21,528(4) |
| 482 | exc; ld r20,400(4) |
| 483 | exc; ld r11,272(4) |
| 484 | exc; ld r9,144(4) |
| 485 | exc; ld r7,16(4) |
| 486 | exc; std r28,664(3) |
| 487 | exc; std r27,536(3) |
| 488 | exc; std r26,408(3) |
| 489 | exc; std r31,280(3) |
| 490 | exc; std r30,152(3) |
| 491 | exc; stdu r29,24(3) |
| 492 | exc; ld r25,664(4) |
| 493 | exc; ld r24,536(4) |
| 494 | exc; ld r23,408(4) |
| 495 | exc; ld r10,280(4) |
| 496 | exc; ld r8,152(4) |
| 497 | exc; ldu r6,24(4) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 498 | bdnz 1b |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 499 | exc; std r22,648(3) |
| 500 | exc; std r21,520(3) |
| 501 | exc; std r20,392(3) |
| 502 | exc; std r11,264(3) |
| 503 | exc; std r9,136(3) |
| 504 | exc; std r7,8(3) |
| 505 | addi r4,r4,640 |
| 506 | addi r3,r3,648 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 507 | bge 0b |
| 508 | mtctr r5 |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 509 | exc; ld r7,0(4) |
| 510 | exc; ld r8,8(4) |
| 511 | exc; ldu r9,16(4) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 512 | 3: |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 513 | exc; ld r10,8(4) |
| 514 | exc; std r7,8(3) |
| 515 | exc; ld r7,16(4) |
| 516 | exc; std r8,16(3) |
| 517 | exc; ld r8,24(4) |
| 518 | exc; std r9,24(3) |
| 519 | exc; ldu r9,32(4) |
| 520 | exc; stdu r10,32(3) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 521 | bdnz 3b |
| 522 | 4: |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 523 | exc; ld r10,8(4) |
| 524 | exc; std r7,8(3) |
| 525 | exc; std r8,16(3) |
| 526 | exc; std r9,24(3) |
| 527 | exc; std r10,32(3) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 528 | 9: ld r20,-120(1) |
| 529 | ld r21,-112(1) |
| 530 | ld r22,-104(1) |
| 531 | ld r23,-96(1) |
| 532 | ld r24,-88(1) |
| 533 | ld r25,-80(1) |
| 534 | ld r26,-72(1) |
| 535 | ld r27,-64(1) |
| 536 | ld r28,-56(1) |
| 537 | ld r29,-48(1) |
| 538 | ld r30,-40(1) |
| 539 | ld r31,-32(1) |
| 540 | li r3,0 |
| 541 | blr |
| 542 | |
| 543 | /* |
| 544 | * on an exception, reset to the beginning and jump back into the |
| 545 | * standard __copy_tofrom_user |
| 546 | */ |
Paul Mackerras | a7c81ce | 2018-08-03 20:13:03 +1000 | [diff] [blame] | 547 | .Labort: |
| 548 | ld r20,-120(1) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 549 | ld r21,-112(1) |
| 550 | ld r22,-104(1) |
| 551 | ld r23,-96(1) |
| 552 | ld r24,-88(1) |
| 553 | ld r25,-80(1) |
| 554 | ld r26,-72(1) |
| 555 | ld r27,-64(1) |
| 556 | ld r28,-56(1) |
| 557 | ld r29,-48(1) |
| 558 | ld r30,-40(1) |
| 559 | ld r31,-32(1) |
| 560 | ld r3,-24(r1) |
| 561 | ld r4,-16(r1) |
| 562 | li r5,4096 |
| 563 | b .Ldst_aligned |
Al Viro | 9445aa1 | 2016-01-13 23:33:46 -0500 | [diff] [blame] | 564 | EXPORT_SYMBOL(__copy_tofrom_user) |