blob: 4711fa4457f3537a2d551673b34f9f6a12ae2474 [file] [log] [blame]
Avi Kivity6aa8b732006-12-10 02:21:36 -08001#ifndef __SVM_H
2#define __SVM_H
3
David Howellsaf170c52012-12-14 22:37:13 +00004#include <uapi/asm/svm.h>
Xiao Guangrong26bf2642012-09-17 16:31:13 +08005
Xiao Guangrong26bf2642012-09-17 16:31:13 +08006
Avi Kivity6aa8b732006-12-10 02:21:36 -08007enum {
8 INTERCEPT_INTR,
9 INTERCEPT_NMI,
10 INTERCEPT_SMI,
11 INTERCEPT_INIT,
12 INTERCEPT_VINTR,
13 INTERCEPT_SELECTIVE_CR0,
14 INTERCEPT_STORE_IDTR,
15 INTERCEPT_STORE_GDTR,
16 INTERCEPT_STORE_LDTR,
17 INTERCEPT_STORE_TR,
18 INTERCEPT_LOAD_IDTR,
19 INTERCEPT_LOAD_GDTR,
20 INTERCEPT_LOAD_LDTR,
21 INTERCEPT_LOAD_TR,
22 INTERCEPT_RDTSC,
23 INTERCEPT_RDPMC,
24 INTERCEPT_PUSHF,
25 INTERCEPT_POPF,
26 INTERCEPT_CPUID,
27 INTERCEPT_RSM,
28 INTERCEPT_IRET,
29 INTERCEPT_INTn,
30 INTERCEPT_INVD,
31 INTERCEPT_PAUSE,
32 INTERCEPT_HLT,
33 INTERCEPT_INVLPG,
34 INTERCEPT_INVLPGA,
35 INTERCEPT_IOIO_PROT,
36 INTERCEPT_MSR_PROT,
37 INTERCEPT_TASK_SWITCH,
38 INTERCEPT_FERR_FREEZE,
39 INTERCEPT_SHUTDOWN,
40 INTERCEPT_VMRUN,
41 INTERCEPT_VMMCALL,
42 INTERCEPT_VMLOAD,
43 INTERCEPT_VMSAVE,
44 INTERCEPT_STGI,
45 INTERCEPT_CLGI,
46 INTERCEPT_SKINIT,
47 INTERCEPT_RDTSCP,
48 INTERCEPT_ICEBP,
49 INTERCEPT_WBINVD,
Joerg Roedel916ce232007-03-21 19:47:00 +010050 INTERCEPT_MONITOR,
51 INTERCEPT_MWAIT,
52 INTERCEPT_MWAIT_COND,
Joerg Roedel81dd35d2010-12-07 17:15:06 +010053 INTERCEPT_XSETBV,
Avi Kivity6aa8b732006-12-10 02:21:36 -080054};
55
56
57struct __attribute__ ((__packed__)) vmcb_control_area {
Roedel, Joerg4ee546b2010-12-03 10:50:51 +010058 u32 intercept_cr;
Joerg Roedel3aed0412010-11-30 18:03:58 +010059 u32 intercept_dr;
Avi Kivity6aa8b732006-12-10 02:21:36 -080060 u32 intercept_exceptions;
61 u64 intercept;
Mark Langsdorf565d0992009-10-06 14:25:02 -050062 u8 reserved_1[42];
63 u16 pause_filter_count;
Avi Kivity6aa8b732006-12-10 02:21:36 -080064 u64 iopm_base_pa;
65 u64 msrpm_base_pa;
66 u64 tsc_offset;
67 u32 asid;
68 u8 tlb_ctl;
69 u8 reserved_2[3];
70 u32 int_ctl;
71 u32 int_vector;
72 u32 int_state;
73 u8 reserved_3[4];
74 u32 exit_code;
75 u32 exit_code_hi;
76 u64 exit_info_1;
77 u64 exit_info_2;
78 u32 exit_int_info;
79 u32 exit_int_info_err;
80 u64 nested_ctl;
Suravee Suthikulpanit3d5615e2016-05-04 14:09:45 -050081 u64 avic_vapic_bar;
82 u8 reserved_4[8];
Avi Kivity6aa8b732006-12-10 02:21:36 -080083 u32 event_inj;
84 u32 event_inj_err;
85 u64 nested_cr3;
86 u64 lbr_ctl;
Roedel, Joerg8d28fec2010-12-03 13:15:21 +010087 u32 clean;
88 u32 reserved_5;
Andre Przywara6bc31bd2010-04-11 23:07:28 +020089 u64 next_rip;
Andre Przywaradc25e892010-12-21 11:12:07 +010090 u8 insn_len;
91 u8 insn_bytes[15];
Suravee Suthikulpanit3d5615e2016-05-04 14:09:45 -050092 u64 avic_backing_page; /* Offset 0xe0 */
93 u8 reserved_6[8]; /* Offset 0xe8 */
94 u64 avic_logical_id; /* Offset 0xf0 */
95 u64 avic_physical_id; /* Offset 0xf8 */
96 u8 reserved_7[768];
Avi Kivity6aa8b732006-12-10 02:21:36 -080097};
98
99
100#define TLB_CONTROL_DO_NOTHING 0
101#define TLB_CONTROL_FLUSH_ALL_ASID 1
Joerg Roedel38e5e922010-12-03 15:25:16 +0100102#define TLB_CONTROL_FLUSH_ASID 3
103#define TLB_CONTROL_FLUSH_ASID_LOCAL 7
Avi Kivity6aa8b732006-12-10 02:21:36 -0800104
105#define V_TPR_MASK 0x0f
106
107#define V_IRQ_SHIFT 8
108#define V_IRQ_MASK (1 << V_IRQ_SHIFT)
109
110#define V_INTR_PRIO_SHIFT 16
111#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
112
113#define V_IGN_TPR_SHIFT 20
114#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
115
116#define V_INTR_MASKING_SHIFT 24
117#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
118
119#define SVM_INTERRUPT_SHADOW_MASK 1
120
121#define SVM_IOIO_STR_SHIFT 2
122#define SVM_IOIO_REP_SHIFT 3
123#define SVM_IOIO_SIZE_SHIFT 4
124#define SVM_IOIO_ASIZE_SHIFT 7
125
126#define SVM_IOIO_TYPE_MASK 1
127#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
128#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
129#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
130#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
131
Joerg Roedel4a810182010-02-24 18:59:15 +0100132#define SVM_VM_CR_VALID_MASK 0x001fULL
133#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
134#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
135
Avi Kivity6aa8b732006-12-10 02:21:36 -0800136struct __attribute__ ((__packed__)) vmcb_seg {
137 u16 selector;
138 u16 attrib;
139 u32 limit;
140 u64 base;
141};
142
143struct __attribute__ ((__packed__)) vmcb_save_area {
144 struct vmcb_seg es;
145 struct vmcb_seg cs;
146 struct vmcb_seg ss;
147 struct vmcb_seg ds;
148 struct vmcb_seg fs;
149 struct vmcb_seg gs;
150 struct vmcb_seg gdtr;
151 struct vmcb_seg ldtr;
152 struct vmcb_seg idtr;
153 struct vmcb_seg tr;
154 u8 reserved_1[43];
155 u8 cpl;
156 u8 reserved_2[4];
157 u64 efer;
158 u8 reserved_3[112];
159 u64 cr4;
160 u64 cr3;
161 u64 cr0;
162 u64 dr7;
163 u64 dr6;
164 u64 rflags;
165 u64 rip;
166 u8 reserved_4[88];
167 u64 rsp;
168 u8 reserved_5[24];
169 u64 rax;
170 u64 star;
171 u64 lstar;
172 u64 cstar;
173 u64 sfmask;
174 u64 kernel_gs_base;
175 u64 sysenter_cs;
176 u64 sysenter_esp;
177 u64 sysenter_eip;
178 u64 cr2;
179 u8 reserved_6[32];
180 u64 g_pat;
181 u64 dbgctl;
182 u64 br_from;
183 u64 br_to;
184 u64 last_excp_from;
185 u64 last_excp_to;
186};
187
188struct __attribute__ ((__packed__)) vmcb {
189 struct vmcb_control_area control;
190 struct vmcb_save_area save;
191};
192
193#define SVM_CPUID_FEATURE_SHIFT 2
194#define SVM_CPUID_FUNC 0x8000000a
195
Joerg Roedel6031a612007-06-22 12:29:50 +0300196#define SVM_VM_CR_SVM_DISABLE 4
197
Avi Kivity6aa8b732006-12-10 02:21:36 -0800198#define SVM_SELECTOR_S_SHIFT 4
199#define SVM_SELECTOR_DPL_SHIFT 5
200#define SVM_SELECTOR_P_SHIFT 7
201#define SVM_SELECTOR_AVL_SHIFT 8
202#define SVM_SELECTOR_L_SHIFT 9
203#define SVM_SELECTOR_DB_SHIFT 10
204#define SVM_SELECTOR_G_SHIFT 11
205
206#define SVM_SELECTOR_TYPE_MASK (0xf)
207#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
208#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
209#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
210#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
211#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
212#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
213#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
214
215#define SVM_SELECTOR_WRITE_MASK (1 << 1)
216#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
217#define SVM_SELECTOR_CODE_MASK (1 << 3)
218
Roedel, Joerg4ee546b2010-12-03 10:50:51 +0100219#define INTERCEPT_CR0_READ 0
220#define INTERCEPT_CR3_READ 3
221#define INTERCEPT_CR4_READ 4
222#define INTERCEPT_CR8_READ 8
223#define INTERCEPT_CR0_WRITE (16 + 0)
224#define INTERCEPT_CR3_WRITE (16 + 3)
225#define INTERCEPT_CR4_WRITE (16 + 4)
226#define INTERCEPT_CR8_WRITE (16 + 8)
Avi Kivity6aa8b732006-12-10 02:21:36 -0800227
Joerg Roedel3aed0412010-11-30 18:03:58 +0100228#define INTERCEPT_DR0_READ 0
229#define INTERCEPT_DR1_READ 1
230#define INTERCEPT_DR2_READ 2
231#define INTERCEPT_DR3_READ 3
232#define INTERCEPT_DR4_READ 4
233#define INTERCEPT_DR5_READ 5
234#define INTERCEPT_DR6_READ 6
235#define INTERCEPT_DR7_READ 7
236#define INTERCEPT_DR0_WRITE (16 + 0)
237#define INTERCEPT_DR1_WRITE (16 + 1)
238#define INTERCEPT_DR2_WRITE (16 + 2)
239#define INTERCEPT_DR3_WRITE (16 + 3)
240#define INTERCEPT_DR4_WRITE (16 + 4)
241#define INTERCEPT_DR5_WRITE (16 + 5)
242#define INTERCEPT_DR6_WRITE (16 + 6)
243#define INTERCEPT_DR7_WRITE (16 + 7)
Avi Kivity6aa8b732006-12-10 02:21:36 -0800244
245#define SVM_EVTINJ_VEC_MASK 0xff
246
247#define SVM_EVTINJ_TYPE_SHIFT 8
248#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
249
250#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
251#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
252#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
253#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
254
255#define SVM_EVTINJ_VALID (1 << 31)
256#define SVM_EVTINJ_VALID_ERR (1 << 11)
257
258#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
Gleb Natapov64a7ec02009-03-30 16:03:29 +0300259#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
Avi Kivity6aa8b732006-12-10 02:21:36 -0800260
261#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
262#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
263#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
264#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
265
266#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
267#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
268
Izik Eidus37817f22008-03-24 23:14:53 +0200269#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
270#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
Jan Kiszkae269fb22010-04-14 15:51:09 +0200271#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
Izik Eidus37817f22008-03-24 23:14:53 +0200272
Andre Przywara7ff76d52010-12-21 11:12:04 +0100273#define SVM_EXITINFO_REG_MASK 0x0F
274
Avi Kivitydc772702010-01-06 13:13:01 +0200275#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
Avi Kivity6aa8b732006-12-10 02:21:36 -0800276
277#define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
278#define SVM_VMRUN ".byte 0x0f, 0x01, 0xd8"
279#define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb"
280#define SVM_CLGI ".byte 0x0f, 0x01, 0xdd"
281#define SVM_STGI ".byte 0x0f, 0x01, 0xdc"
282#define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"
283
284#endif