Nikola Milosavljevic | b405066 | 2021-12-12 00:13:49 +0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /dts-v1/; |
| 3 | |
| 4 | #include <dt-bindings/input/atmel-maxtouch.h> |
| 5 | #include <dt-bindings/input/gpio-keys.h> |
| 6 | #include <dt-bindings/input/input.h> |
| 7 | #include <dt-bindings/thermal/thermal.h> |
| 8 | |
| 9 | #include "tegra20.dtsi" |
| 10 | #include "tegra20-cpu-opp.dtsi" |
| 11 | #include "tegra20-cpu-opp-microvolt.dtsi" |
| 12 | |
| 13 | / { |
| 14 | model = "ASUS EeePad Transformer TF101"; |
| 15 | compatible = "asus,tf101", "nvidia,tegra20"; |
| 16 | chassis-type = "convertible"; |
| 17 | |
| 18 | aliases { |
| 19 | mmc0 = &sdmmc4; /* eMMC */ |
| 20 | mmc1 = &sdmmc3; /* MicroSD */ |
| 21 | mmc2 = &sdmmc1; /* WiFi */ |
| 22 | |
| 23 | rtc0 = &pmic; |
| 24 | rtc1 = "/rtc@7000e000"; |
| 25 | |
| 26 | serial0 = &uartd; |
| 27 | serial1 = &uartc; /* Bluetooth */ |
| 28 | serial2 = &uartb; /* GPS */ |
| 29 | }; |
| 30 | |
| 31 | /* |
| 32 | * The decompressor and also some bootloaders rely on a |
| 33 | * pre-existing /chosen node to be available to insert the |
| 34 | * command line and merge other ATAGS info. |
| 35 | */ |
| 36 | chosen {}; |
| 37 | |
| 38 | memory@0 { |
| 39 | reg = <0x00000000 0x40000000>; |
| 40 | }; |
| 41 | |
| 42 | reserved-memory { |
| 43 | #address-cells = <1>; |
| 44 | #size-cells = <1>; |
| 45 | ranges; |
| 46 | |
| 47 | ramoops@2ffe0000 { |
| 48 | compatible = "ramoops"; |
| 49 | reg = <0x2ffe0000 0x10000>; /* 64kB */ |
| 50 | console-size = <0x8000>; /* 32kB */ |
| 51 | record-size = <0x400>; /* 1kB */ |
| 52 | ecc-size = <16>; |
| 53 | }; |
| 54 | |
| 55 | linux,cma@30000000 { |
| 56 | compatible = "shared-dma-pool"; |
| 57 | alloc-ranges = <0x30000000 0x10000000>; |
| 58 | size = <0x10000000>; /* 256MiB */ |
| 59 | linux,cma-default; |
| 60 | reusable; |
| 61 | }; |
| 62 | }; |
| 63 | |
| 64 | host1x@50000000 { |
| 65 | dc@54200000 { |
| 66 | rgb { |
| 67 | status = "okay"; |
| 68 | |
| 69 | port@0 { |
| 70 | lcd_output: endpoint { |
| 71 | remote-endpoint = <&lvds_encoder_input>; |
| 72 | bus-width = <18>; |
| 73 | }; |
| 74 | }; |
| 75 | }; |
| 76 | }; |
| 77 | |
| 78 | hdmi@54280000 { |
| 79 | status = "okay"; |
| 80 | |
| 81 | vdd-supply = <&hdmi_vdd_reg>; |
| 82 | pll-supply = <&hdmi_pll_reg>; |
| 83 | hdmi-supply = <&vdd_hdmi_en>; |
| 84 | |
| 85 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
| 86 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
| 87 | GPIO_ACTIVE_HIGH>; |
| 88 | }; |
| 89 | }; |
| 90 | |
| 91 | gpio@6000d000 { |
| 92 | charging-enable-hog { |
| 93 | gpio-hog; |
| 94 | gpios = <TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; |
| 95 | output-low; |
| 96 | }; |
| 97 | }; |
| 98 | |
| 99 | pinmux@70000014 { |
| 100 | pinctrl-names = "default"; |
| 101 | pinctrl-0 = <&state_default>; |
| 102 | |
| 103 | state_default: pinmux { |
| 104 | ata { |
| 105 | nvidia,pins = "ata"; |
| 106 | nvidia,function = "ide"; |
| 107 | }; |
| 108 | |
| 109 | atb { |
| 110 | nvidia,pins = "atb", "gma", "gme"; |
| 111 | nvidia,function = "sdio4"; |
| 112 | }; |
| 113 | |
| 114 | atc { |
| 115 | nvidia,pins = "atc"; |
| 116 | nvidia,function = "nand"; |
| 117 | }; |
| 118 | |
| 119 | atd { |
| 120 | nvidia,pins = "atd", "ate", "gmb", "spia", |
| 121 | "spib", "spic"; |
| 122 | nvidia,function = "gmi"; |
| 123 | }; |
| 124 | |
| 125 | cdev1 { |
| 126 | nvidia,pins = "cdev1"; |
| 127 | nvidia,function = "plla_out"; |
| 128 | }; |
| 129 | |
| 130 | cdev2 { |
| 131 | nvidia,pins = "cdev2"; |
| 132 | nvidia,function = "pllp_out4"; |
| 133 | }; |
| 134 | |
| 135 | crtp { |
| 136 | nvidia,pins = "crtp"; |
| 137 | nvidia,function = "crt"; |
| 138 | }; |
| 139 | |
| 140 | lm1 { |
| 141 | nvidia,pins = "lm1"; |
| 142 | nvidia,function = "rsvd3"; |
| 143 | }; |
| 144 | |
| 145 | csus { |
| 146 | nvidia,pins = "csus"; |
| 147 | nvidia,function = "vi_sensor_clk"; |
| 148 | }; |
| 149 | |
| 150 | dap1 { |
| 151 | nvidia,pins = "dap1"; |
| 152 | nvidia,function = "dap1"; |
| 153 | }; |
| 154 | |
| 155 | dap2 { |
| 156 | nvidia,pins = "dap2"; |
| 157 | nvidia,function = "dap2"; |
| 158 | }; |
| 159 | |
| 160 | dap3 { |
| 161 | nvidia,pins = "dap3"; |
| 162 | nvidia,function = "dap3"; |
| 163 | }; |
| 164 | |
| 165 | dap4 { |
| 166 | nvidia,pins = "dap4"; |
| 167 | nvidia,function = "dap4"; |
| 168 | }; |
| 169 | |
| 170 | dta { |
| 171 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; |
| 172 | nvidia,function = "vi"; |
| 173 | }; |
| 174 | |
| 175 | dtf { |
| 176 | nvidia,pins = "dtf"; |
| 177 | nvidia,function = "i2c3"; |
| 178 | }; |
| 179 | |
| 180 | gmc { |
| 181 | nvidia,pins = "gmc"; |
| 182 | nvidia,function = "uartd"; |
| 183 | }; |
| 184 | |
| 185 | gmd { |
| 186 | nvidia,pins = "gmd"; |
| 187 | nvidia,function = "sflash"; |
| 188 | }; |
| 189 | |
| 190 | gpu { |
| 191 | nvidia,pins = "gpu"; |
| 192 | nvidia,function = "pwm"; |
| 193 | }; |
| 194 | |
| 195 | gpu7 { |
| 196 | nvidia,pins = "gpu7"; |
| 197 | nvidia,function = "rtck"; |
| 198 | }; |
| 199 | |
| 200 | gpv { |
| 201 | nvidia,pins = "gpv", "slxa"; |
| 202 | nvidia,function = "pcie"; |
| 203 | }; |
| 204 | |
| 205 | hdint { |
| 206 | nvidia,pins = "hdint"; |
| 207 | nvidia,function = "hdmi"; |
| 208 | }; |
| 209 | |
| 210 | i2cp { |
| 211 | nvidia,pins = "i2cp"; |
| 212 | nvidia,function = "i2cp"; |
| 213 | }; |
| 214 | |
| 215 | irrx { |
| 216 | nvidia,pins = "irrx", "irtx"; |
| 217 | nvidia,function = "uartb"; |
| 218 | }; |
| 219 | |
| 220 | kbca { |
| 221 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", |
| 222 | "kbce", "kbcf"; |
| 223 | nvidia,function = "kbc"; |
| 224 | }; |
| 225 | |
| 226 | lcsn { |
| 227 | nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", |
| 228 | "lsdi", "lvp0"; |
| 229 | nvidia,function = "rsvd4"; |
| 230 | }; |
| 231 | |
| 232 | ld0 { |
| 233 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", |
| 234 | "ld5", "ld6", "ld7", "ld8", "ld9", |
| 235 | "ld10", "ld11", "ld12", "ld13", "ld14", |
| 236 | "ld15", "ld16", "ld17", "ldi", "lhp0", |
| 237 | "lhp1", "lhp2", "lhs", "lpp", "lpw0", |
| 238 | "lpw2", "lsc0", "lsc1", "lsck", "lsda", |
| 239 | "lspi", "lvp1", "lvs"; |
| 240 | nvidia,function = "displaya"; |
| 241 | }; |
| 242 | |
| 243 | owc { |
| 244 | nvidia,pins = "owc", "spdi", "spdo", "uac"; |
| 245 | nvidia,function = "rsvd2"; |
| 246 | }; |
| 247 | |
| 248 | pmc { |
| 249 | nvidia,pins = "pmc"; |
| 250 | nvidia,function = "pwr_on"; |
| 251 | }; |
| 252 | |
| 253 | rm { |
| 254 | nvidia,pins = "rm"; |
| 255 | nvidia,function = "i2c1"; |
| 256 | }; |
| 257 | |
| 258 | sdb { |
| 259 | nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; |
| 260 | nvidia,function = "sdio3"; |
| 261 | }; |
| 262 | |
| 263 | sdio1 { |
| 264 | nvidia,pins = "sdio1"; |
| 265 | nvidia,function = "sdio1"; |
| 266 | }; |
| 267 | |
| 268 | slxd { |
| 269 | nvidia,pins = "slxd"; |
| 270 | nvidia,function = "spdif"; |
| 271 | }; |
| 272 | |
| 273 | spid { |
| 274 | nvidia,pins = "spid", "spie", "spif"; |
| 275 | nvidia,function = "spi1"; |
| 276 | }; |
| 277 | |
| 278 | spig { |
| 279 | nvidia,pins = "spig", "spih"; |
| 280 | nvidia,function = "spi2_alt"; |
| 281 | }; |
| 282 | |
| 283 | uaa { |
| 284 | nvidia,pins = "uaa", "uab", "uda"; |
| 285 | nvidia,function = "ulpi"; |
| 286 | }; |
| 287 | |
| 288 | uad { |
| 289 | nvidia,pins = "uad"; |
| 290 | nvidia,function = "irda"; |
| 291 | }; |
| 292 | |
| 293 | uca { |
| 294 | nvidia,pins = "uca", "ucb"; |
| 295 | nvidia,function = "uartc"; |
| 296 | }; |
| 297 | |
| 298 | conf_ata { |
| 299 | nvidia,pins = "ata", "atb", "atc", "atd", |
| 300 | "cdev1", "cdev2", "dap1", "dap4", |
| 301 | "dte", "ddc", "dtf", "gma", "gmc", |
| 302 | "gme", "gpu", "gpu7", "gpv", "i2cp", |
| 303 | "irrx", "irtx", "pta", "rm", "sdc", |
| 304 | "sdd", "slxc", "slxd", "slxk", "spdi", |
| 305 | "spdo", "uac", "uad", |
| 306 | "uda", "csus"; |
| 307 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 308 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 309 | }; |
| 310 | |
| 311 | conf_ate { |
| 312 | nvidia,pins = "ate", "dap2", "dap3", "gmb", "gmd", |
| 313 | "owc", "spia", "spib", "spic", |
| 314 | "spid", "spie", "spig", "slxa"; |
| 315 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 316 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 317 | }; |
| 318 | |
| 319 | conf_ck32 { |
| 320 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", |
| 321 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; |
| 322 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 323 | }; |
| 324 | |
| 325 | conf_crtp { |
| 326 | nvidia,pins = "crtp", "spih"; |
| 327 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 328 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 329 | }; |
| 330 | |
| 331 | conf_dta { |
| 332 | nvidia,pins = "dta", "dtb", "dtc", "dtd"; |
| 333 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 334 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 335 | }; |
| 336 | |
| 337 | conf_spif { |
| 338 | nvidia,pins = "spif"; |
| 339 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 340 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 341 | }; |
| 342 | |
| 343 | conf_hdint { |
| 344 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", |
| 345 | "lpw1", "lsck", "lsda", "lsdi", "lvp0"; |
| 346 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 347 | }; |
| 348 | |
| 349 | conf_kbca { |
| 350 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", |
| 351 | "kbce", "kbcf", "sdio1", "uaa", "uab", |
| 352 | "uca", "ucb"; |
| 353 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 354 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 355 | }; |
| 356 | |
| 357 | conf_lc { |
| 358 | nvidia,pins = "lc", "ls"; |
| 359 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 360 | }; |
| 361 | |
| 362 | conf_ld0 { |
| 363 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", |
| 364 | "ld5", "ld6", "ld7", "ld8", "ld9", |
| 365 | "ld10", "ld11", "ld12", "ld13", "ld14", |
| 366 | "ld15", "ld16", "ld17", "ldi", "lhp0", |
| 367 | "lhp1", "lhp2", "lhs", "lm0", "lpp", |
| 368 | "lpw0", "lpw2", "lsc0", "lsc1", "lspi", |
| 369 | "lvp1", "lvs", "pmc", "sdb"; |
| 370 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 371 | }; |
| 372 | |
| 373 | conf_ld17_0 { |
| 374 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", |
| 375 | "ld23_22"; |
| 376 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 377 | }; |
| 378 | |
| 379 | drive_sdio1 { |
| 380 | nvidia,pins = "drive_sdio1", "drive_ddc", "drive_vi1"; |
| 381 | nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; |
| 382 | nvidia,schmitt = <TEGRA_PIN_ENABLE>; |
| 383 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; |
| 384 | nvidia,pull-down-strength = <31>; |
| 385 | nvidia,pull-up-strength = <31>; |
| 386 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
| 387 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
| 388 | }; |
| 389 | |
| 390 | drive_csus { |
| 391 | nvidia,pins = "drive_csus"; |
| 392 | nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; |
| 393 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| 394 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; |
| 395 | nvidia,pull-down-strength = <31>; |
| 396 | nvidia,pull-up-strength = <31>; |
| 397 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
| 398 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
| 399 | }; |
| 400 | }; |
| 401 | |
| 402 | state_i2cmux_ddc: pinmux_i2cmux_ddc { |
| 403 | ddc { |
| 404 | nvidia,pins = "ddc"; |
| 405 | nvidia,function = "i2c2"; |
| 406 | }; |
| 407 | |
| 408 | pta { |
| 409 | nvidia,pins = "pta"; |
| 410 | nvidia,function = "rsvd4"; |
| 411 | }; |
| 412 | }; |
| 413 | |
| 414 | state_i2cmux_pta: pinmux_i2cmux_pta { |
| 415 | ddc { |
| 416 | nvidia,pins = "ddc"; |
| 417 | nvidia,function = "rsvd4"; |
| 418 | }; |
| 419 | |
| 420 | pta { |
| 421 | nvidia,pins = "pta"; |
| 422 | nvidia,function = "i2c2"; |
| 423 | }; |
| 424 | }; |
| 425 | |
| 426 | state_i2cmux_idle: pinmux_i2cmux_idle { |
| 427 | ddc { |
| 428 | nvidia,pins = "ddc"; |
| 429 | nvidia,function = "rsvd4"; |
| 430 | }; |
| 431 | |
| 432 | pta { |
| 433 | nvidia,pins = "pta"; |
| 434 | nvidia,function = "rsvd4"; |
| 435 | }; |
| 436 | }; |
| 437 | }; |
| 438 | |
| 439 | i2s@70002800 { |
| 440 | status = "okay"; |
| 441 | }; |
| 442 | |
| 443 | serial@70006040 { |
| 444 | compatible = "nvidia,tegra20-hsuart"; |
| 445 | /* GPS BCM4751 */ |
| 446 | }; |
| 447 | |
| 448 | serial@70006200 { |
| 449 | compatible = "nvidia,tegra20-hsuart"; |
| 450 | status = "okay"; |
| 451 | |
| 452 | /* Azurewave AW-NH615 BCM4329B1 */ |
| 453 | bluetooth { |
| 454 | compatible = "brcm,bcm4329-bt"; |
| 455 | |
| 456 | interrupt-parent = <&gpio>; |
| 457 | interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>; |
| 458 | interrupt-names = "host-wakeup"; |
| 459 | |
| 460 | /* PLLP 216MHz / 16 / 4 */ |
| 461 | max-speed = <3375000>; |
| 462 | |
| 463 | clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; |
| 464 | clock-names = "txco"; |
| 465 | |
| 466 | vbat-supply = <&vdd_3v3_sys>; |
| 467 | vddio-supply = <&vdd_1v8_sys>; |
| 468 | |
| 469 | device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; |
| 470 | shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; |
| 471 | }; |
| 472 | }; |
| 473 | |
| 474 | serial@70006300 { |
| 475 | status = "okay"; |
| 476 | }; |
| 477 | |
| 478 | pwm@7000a000 { |
| 479 | status = "okay"; |
| 480 | }; |
| 481 | |
| 482 | i2c@7000c000 { |
| 483 | status = "okay"; |
| 484 | clock-frequency = <400000>; |
| 485 | |
| 486 | /* Aichi AMI306 digital compass */ |
| 487 | magnetometer@e { |
| 488 | compatible = "asahi-kasei,ak8974"; |
| 489 | reg = <0xe>; |
| 490 | |
| 491 | avdd-supply = <&vdd_3v3_sys>; |
| 492 | dvdd-supply = <&vdd_1v8_sys>; |
| 493 | |
| 494 | mount-matrix = "-1", "0", "0", |
| 495 | "0", "1", "0", |
| 496 | "0", "0", "-1"; |
| 497 | }; |
| 498 | |
| 499 | wm8903: audio-codec@1a { |
| 500 | compatible = "wlf,wm8903"; |
| 501 | reg = <0x1a>; |
| 502 | |
| 503 | interrupt-parent = <&gpio>; |
| 504 | interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_BOTH>; |
| 505 | |
| 506 | gpio-controller; |
| 507 | #gpio-cells = <2>; |
| 508 | |
| 509 | micdet-cfg = <0x83>; |
| 510 | micdet-delay = <100>; |
| 511 | |
| 512 | gpio-cfg = < |
| 513 | 0xffffffff /* don't touch */ |
| 514 | 0xffffffff /* don't touch */ |
| 515 | 0x00000000 /* Speaker-enable GPIO, output, low */ |
| 516 | 0x00000400 /* Mic bias current detect */ |
| 517 | 0xffffffff /* don't touch */ |
| 518 | >; |
| 519 | |
| 520 | AVDD-supply = <&vdd_1v8_sys>; |
| 521 | CPVDD-supply = <&vdd_1v8_sys>; |
| 522 | DBVDD-supply = <&vdd_1v8_sys>; |
| 523 | DCVDD-supply = <&vdd_1v8_sys>; |
| 524 | }; |
| 525 | |
| 526 | /* Atmel MXT1386 Touchscreen */ |
| 527 | touchscreen@5b { |
| 528 | compatible = "atmel,maxtouch"; |
| 529 | reg = <0x5b>; |
| 530 | |
| 531 | interrupt-parent = <&gpio>; |
| 532 | interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>; |
| 533 | |
| 534 | reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>; |
| 535 | |
| 536 | vdda-supply = <&vdd_3v3_sys>; |
| 537 | vdd-supply = <&vdd_3v3_sys>; |
| 538 | |
| 539 | atmel,wakeup-method = <ATMEL_MXT_WAKEUP_I2C_SCL>; |
| 540 | }; |
| 541 | |
| 542 | gyroscope@68 { |
| 543 | compatible = "invensense,mpu3050"; |
| 544 | reg = <0x68>; |
| 545 | |
| 546 | interrupt-parent = <&gpio>; |
| 547 | interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>; |
| 548 | |
| 549 | vdd-supply = <&vdd_3v3_sys>; |
| 550 | vlogic-supply = <&vdd_1v8_sys>; |
| 551 | |
| 552 | mount-matrix = "0", "1", "0", |
| 553 | "-1", "0", "0", |
| 554 | "0", "0", "1"; |
| 555 | |
| 556 | i2c-gate { |
| 557 | #address-cells = <1>; |
| 558 | #size-cells = <0>; |
| 559 | |
| 560 | accelerometer@f { |
| 561 | compatible = "kionix,kxtf9"; |
| 562 | reg = <0xf>; |
| 563 | |
| 564 | interrupt-parent = <&gpio>; |
| 565 | interrupts = <TEGRA_GPIO(N, 4) IRQ_TYPE_EDGE_RISING>; |
| 566 | |
| 567 | vdd-supply = <&vdd_1v8_sys>; |
| 568 | vddio-supply = <&vdd_1v8_sys>; |
| 569 | |
| 570 | mount-matrix = "1", "0", "0", |
| 571 | "0", "1", "0", |
| 572 | "0", "0", "1"; |
| 573 | }; |
| 574 | }; |
| 575 | }; |
| 576 | }; |
| 577 | |
| 578 | i2c2: i2c@7000c400 { |
| 579 | status = "okay"; |
| 580 | clock-frequency = <100000>; |
| 581 | }; |
| 582 | |
| 583 | i2c@7000c500 { |
| 584 | status = "okay"; |
| 585 | clock-frequency = <400000>; |
| 586 | }; |
| 587 | |
| 588 | i2c@7000d000 { |
| 589 | status = "okay"; |
| 590 | clock-frequency = <400000>; |
| 591 | |
| 592 | pmic: pmic@34 { |
| 593 | compatible = "ti,tps6586x"; |
| 594 | reg = <0x34>; |
| 595 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 596 | |
| 597 | ti,system-power-controller; |
| 598 | |
| 599 | #gpio-cells = <2>; |
| 600 | gpio-controller; |
| 601 | |
| 602 | sys-supply = <&vdd_5v0_sys>; |
| 603 | vin-sm0-supply = <&sys_reg>; |
| 604 | vin-sm1-supply = <&sys_reg>; |
| 605 | vin-sm2-supply = <&sys_reg>; |
| 606 | vinldo01-supply = <&sm2_reg>; |
| 607 | vinldo23-supply = <&sm2_reg>; |
| 608 | vinldo4-supply = <&sm2_reg>; |
| 609 | vinldo678-supply = <&sm2_reg>; |
| 610 | vinldo9-supply = <&sm2_reg>; |
| 611 | |
| 612 | regulators { |
| 613 | sys_reg: sys { |
| 614 | regulator-name = "vdd_sys"; |
| 615 | regulator-always-on; |
| 616 | }; |
| 617 | |
| 618 | vdd_core: sm0 { |
| 619 | regulator-name = "vdd_sm0,vdd_core"; |
| 620 | regulator-min-microvolt = <950000>; |
| 621 | regulator-max-microvolt = <1300000>; |
| 622 | regulator-coupled-with = <&rtc_vdd &vdd_cpu>; |
| 623 | regulator-coupled-max-spread = <170000 550000>; |
| 624 | regulator-always-on; |
| 625 | regulator-boot-on; |
| 626 | |
| 627 | nvidia,tegra-core-regulator; |
| 628 | }; |
| 629 | |
| 630 | vdd_cpu: sm1 { |
| 631 | regulator-name = "vdd_sm1,vdd_cpu"; |
| 632 | regulator-min-microvolt = <750000>; |
| 633 | regulator-max-microvolt = <1125000>; |
| 634 | regulator-coupled-with = <&vdd_core &rtc_vdd>; |
| 635 | regulator-coupled-max-spread = <550000 550000>; |
| 636 | regulator-always-on; |
| 637 | regulator-boot-on; |
| 638 | |
| 639 | nvidia,tegra-cpu-regulator; |
| 640 | }; |
| 641 | |
| 642 | sm2_reg: sm2 { |
| 643 | regulator-name = "vdd_sm2,vin_ldo*"; |
| 644 | regulator-min-microvolt = <3700000>; |
| 645 | regulator-max-microvolt = <3700000>; |
| 646 | regulator-always-on; |
| 647 | }; |
| 648 | |
| 649 | /* LDO0 is not connected to anything */ |
| 650 | |
| 651 | ldo1 { |
| 652 | regulator-name = "vdd_ldo1,avdd_pll*"; |
| 653 | regulator-min-microvolt = <1100000>; |
| 654 | regulator-max-microvolt = <1100000>; |
| 655 | regulator-always-on; |
| 656 | }; |
| 657 | |
| 658 | rtc_vdd: ldo2 { |
| 659 | regulator-name = "vdd_ldo2,vdd_rtc"; |
| 660 | regulator-min-microvolt = <950000>; |
| 661 | regulator-max-microvolt = <1300000>; |
| 662 | regulator-coupled-with = <&vdd_core &vdd_cpu>; |
| 663 | regulator-coupled-max-spread = <170000 550000>; |
| 664 | regulator-always-on; |
| 665 | regulator-boot-on; |
| 666 | |
| 667 | nvidia,tegra-rtc-regulator; |
| 668 | }; |
| 669 | |
| 670 | ldo3 { |
| 671 | regulator-name = "vdd_ldo3,avdd_usb*"; |
| 672 | regulator-min-microvolt = <3300000>; |
| 673 | regulator-max-microvolt = <3300000>; |
| 674 | regulator-always-on; |
| 675 | }; |
| 676 | |
| 677 | ldo4 { |
| 678 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; |
| 679 | regulator-min-microvolt = <1800000>; |
| 680 | regulator-max-microvolt = <1800000>; |
| 681 | regulator-always-on; |
| 682 | }; |
| 683 | |
| 684 | vcore_emmc: ldo5 { |
| 685 | regulator-name = "vdd_ldo5,vcore_mmc"; |
| 686 | regulator-min-microvolt = <2850000>; |
| 687 | regulator-max-microvolt = <2850000>; |
| 688 | regulator-always-on; |
| 689 | }; |
| 690 | |
| 691 | ldo6 { |
| 692 | regulator-name = "vdd_ldo6,avdd_vdac"; |
| 693 | regulator-min-microvolt = <1800000>; |
| 694 | regulator-max-microvolt = <1800000>; |
| 695 | }; |
| 696 | |
| 697 | hdmi_vdd_reg: ldo7 { |
| 698 | regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; |
| 699 | regulator-min-microvolt = <3300000>; |
| 700 | regulator-max-microvolt = <3300000>; |
| 701 | }; |
| 702 | |
| 703 | hdmi_pll_reg: ldo8 { |
| 704 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; |
| 705 | regulator-min-microvolt = <1800000>; |
| 706 | regulator-max-microvolt = <1800000>; |
| 707 | }; |
| 708 | |
| 709 | ldo9 { |
| 710 | regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; |
| 711 | regulator-min-microvolt = <2850000>; |
| 712 | regulator-max-microvolt = <2850000>; |
| 713 | regulator-always-on; |
| 714 | }; |
| 715 | |
| 716 | ldo_rtc { |
| 717 | regulator-name = "vdd_rtc_out,vdd_cell"; |
| 718 | regulator-min-microvolt = <3300000>; |
| 719 | regulator-max-microvolt = <3300000>; |
| 720 | regulator-always-on; |
| 721 | }; |
| 722 | }; |
| 723 | }; |
| 724 | |
| 725 | nct1008: temperature-sensor@4c { |
| 726 | compatible = "onnn,nct1008"; |
| 727 | reg = <0x4c>; |
| 728 | vcc-supply = <&vdd_3v3_sys>; |
| 729 | |
| 730 | interrupt-parent = <&gpio>; |
| 731 | interrupts = <TEGRA_GPIO(N, 6) IRQ_TYPE_EDGE_FALLING>; |
| 732 | |
| 733 | #thermal-sensor-cells = <1>; |
| 734 | }; |
| 735 | }; |
| 736 | |
| 737 | pmc@7000e400 { |
| 738 | nvidia,invert-interrupt; |
| 739 | nvidia,suspend-mode = <1>; |
| 740 | nvidia,cpu-pwr-good-time = <2000>; |
| 741 | nvidia,cpu-pwr-off-time = <100>; |
| 742 | nvidia,core-pwr-good-time = <3845 3845>; |
| 743 | nvidia,core-pwr-off-time = <458>; |
| 744 | nvidia,sys-clock-req-active-high; |
| 745 | core-supply = <&vdd_core>; |
| 746 | }; |
| 747 | |
| 748 | memory-controller@7000f400 { |
| 749 | nvidia,use-ram-code; |
| 750 | |
| 751 | emc-tables@3 { |
| 752 | reg = <0x3>; |
| 753 | |
| 754 | #address-cells = <1>; |
| 755 | #size-cells = <0>; |
| 756 | |
| 757 | lpddr2 { |
| 758 | compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; |
| 759 | revision-id1 = <1>; |
| 760 | density = <2048>; |
| 761 | io-width = <16>; |
| 762 | }; |
| 763 | |
| 764 | emc-table@25000 { |
| 765 | reg = <25000>; |
| 766 | compatible = "nvidia,tegra20-emc-table"; |
| 767 | clock-frequency = <25000>; |
| 768 | nvidia,emc-registers = <0x00000002 0x00000006 |
| 769 | 0x00000003 0x00000003 0x00000006 0x00000004 |
| 770 | 0x00000002 0x00000009 0x00000003 0x00000003 |
| 771 | 0x00000002 0x00000002 0x00000002 0x00000004 |
| 772 | 0x00000003 0x00000008 0x0000000b 0x0000004d |
| 773 | 0x00000000 0x00000003 0x00000003 0x00000003 |
| 774 | 0x00000008 0x00000001 0x0000000a 0x00000004 |
| 775 | 0x00000003 0x00000008 0x00000004 0x00000006 |
| 776 | 0x00000002 0x00000068 0x00000000 0x00000003 |
| 777 | 0x00000000 0x00000000 0x00000282 0xa0ae04ae |
| 778 | 0x00070000 0x00000000 0x00000000 0x00000003 |
| 779 | 0x00000000 0x00000000 0x00000000 0x00000000>; |
| 780 | }; |
| 781 | |
| 782 | emc-table@50000 { |
| 783 | reg = <50000>; |
| 784 | compatible = "nvidia,tegra20-emc-table"; |
| 785 | clock-frequency = <50000>; |
| 786 | nvidia,emc-registers = <0x00000003 0x00000007 |
| 787 | 0x00000003 0x00000003 0x00000006 0x00000004 |
| 788 | 0x00000002 0x00000009 0x00000003 0x00000003 |
| 789 | 0x00000002 0x00000002 0x00000002 0x00000005 |
| 790 | 0x00000003 0x00000008 0x0000000b 0x0000009f |
| 791 | 0x00000000 0x00000003 0x00000003 0x00000003 |
| 792 | 0x00000008 0x00000001 0x0000000a 0x00000007 |
| 793 | 0x00000003 0x00000008 0x00000004 0x00000006 |
| 794 | 0x00000002 0x000000d0 0x00000000 0x00000000 |
| 795 | 0x00000000 0x00000000 0x00000282 0xa0ae04ae |
| 796 | 0x00070000 0x00000000 0x00000000 0x00000005 |
| 797 | 0x00000000 0x00000000 0x00000000 0x00000000>; |
| 798 | }; |
| 799 | |
| 800 | emc-table@75000 { |
| 801 | reg = <75000>; |
| 802 | compatible = "nvidia,tegra20-emc-table"; |
| 803 | clock-frequency = <75000>; |
| 804 | nvidia,emc-registers = <0x00000005 0x0000000a |
| 805 | 0x00000004 0x00000003 0x00000006 0x00000004 |
| 806 | 0x00000002 0x00000009 0x00000003 0x00000003 |
| 807 | 0x00000002 0x00000002 0x00000002 0x00000005 |
| 808 | 0x00000003 0x00000008 0x0000000b 0x000000ff |
| 809 | 0x00000000 0x00000003 0x00000003 0x00000003 |
| 810 | 0x00000008 0x00000001 0x0000000a 0x0000000b |
| 811 | 0x00000003 0x00000008 0x00000004 0x00000006 |
| 812 | 0x00000002 0x00000138 0x00000000 0x00000000 |
| 813 | 0x00000000 0x00000000 0x00000282 0xa0ae04ae |
| 814 | 0x00070000 0x00000000 0x00000000 0x00000007 |
| 815 | 0x00000000 0x00000000 0x00000000 0x00000000>; |
| 816 | }; |
| 817 | |
| 818 | emc-table@150000 { |
| 819 | reg = <150000>; |
| 820 | compatible = "nvidia,tegra20-emc-table"; |
| 821 | clock-frequency = <150000>; |
| 822 | nvidia,emc-registers = <0x00000009 0x00000014 |
| 823 | 0x00000007 0x00000003 0x00000006 0x00000004 |
| 824 | 0x00000002 0x00000009 0x00000003 0x00000003 |
| 825 | 0x00000002 0x00000002 0x00000002 0x00000005 |
| 826 | 0x00000003 0x00000008 0x0000000b 0x0000021f |
| 827 | 0x00000000 0x00000003 0x00000003 0x00000003 |
| 828 | 0x00000008 0x00000001 0x0000000a 0x00000015 |
| 829 | 0x00000003 0x00000008 0x00000004 0x00000006 |
| 830 | 0x00000002 0x00000270 0x00000000 0x00000001 |
| 831 | 0x00000000 0x00000000 0x00000282 0xa07c04ae |
| 832 | 0x007dc010 0x00000000 0x00000000 0x0000000e |
| 833 | 0x00000000 0x00000000 0x00000000 0x00000000>; |
| 834 | }; |
| 835 | |
| 836 | emc-table@300000 { |
| 837 | reg = <300000>; |
| 838 | compatible = "nvidia,tegra20-emc-table"; |
| 839 | clock-frequency = <300000>; |
| 840 | nvidia,emc-registers = <0x00000012 0x00000027 |
| 841 | 0x0000000d 0x00000006 0x00000007 0x00000005 |
| 842 | 0x00000003 0x00000009 0x00000006 0x00000006 |
| 843 | 0x00000003 0x00000003 0x00000002 0x00000006 |
| 844 | 0x00000003 0x00000009 0x0000000c 0x0000045f |
| 845 | 0x00000000 0x00000004 0x00000004 0x00000006 |
| 846 | 0x00000008 0x00000001 0x0000000e 0x0000002a |
| 847 | 0x00000003 0x0000000f 0x00000007 0x00000005 |
| 848 | 0x00000002 0x000004e0 0x00000005 0x00000002 |
| 849 | 0x00000000 0x00000000 0x00000282 0xe059048b |
| 850 | 0x007e0010 0x00000000 0x00000000 0x0000001b |
| 851 | 0x00000000 0x00000000 0x00000000 0x00000000>; |
| 852 | }; |
| 853 | }; |
| 854 | }; |
| 855 | |
| 856 | /* Peripheral USB via ASUS connector */ |
| 857 | usb@c5000000 { |
| 858 | compatible = "nvidia,tegra20-udc"; |
| 859 | status = "okay"; |
| 860 | dr_mode = "peripheral"; |
| 861 | }; |
| 862 | |
| 863 | usb-phy@c5000000 { |
| 864 | status = "okay"; |
| 865 | dr_mode = "peripheral"; |
| 866 | nvidia,xcvr-setup-use-fuses; |
| 867 | nvidia,xcvr-lsfslew = <2>; |
| 868 | nvidia,xcvr-lsrslew = <2>; |
| 869 | vbus-supply = <&vdd_5v0_sys>; |
| 870 | }; |
| 871 | |
| 872 | /* Dock's USB port */ |
| 873 | usb@c5008000 { |
| 874 | status = "okay"; |
| 875 | }; |
| 876 | |
| 877 | usb-phy@c5008000 { |
| 878 | status = "okay"; |
| 879 | nvidia,xcvr-setup-use-fuses; |
| 880 | vbus-supply = <&vdd_5v0_sys>; |
| 881 | }; |
| 882 | |
| 883 | sdmmc1: mmc@c8000000 { |
| 884 | status = "okay"; |
| 885 | |
| 886 | #address-cells = <1>; |
| 887 | #size-cells = <0>; |
| 888 | |
| 889 | assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; |
| 890 | assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; |
| 891 | assigned-clock-rates = <40000000>; |
| 892 | |
| 893 | max-frequency = <40000000>; |
| 894 | keep-power-in-suspend; |
| 895 | bus-width = <4>; |
| 896 | non-removable; |
| 897 | |
| 898 | mmc-pwrseq = <&brcm_wifi_pwrseq>; |
| 899 | vmmc-supply = <&vdd_3v3_sys>; |
| 900 | vqmmc-supply = <&vdd_3v3_sys>; |
| 901 | |
| 902 | /* Azurewave AW-NH615 BCM4329B1 */ |
| 903 | wifi@1 { |
| 904 | compatible = "brcm,bcm4329-fmac"; |
| 905 | reg = <1>; |
| 906 | |
| 907 | interrupt-parent = <&gpio>; |
| 908 | interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>; |
| 909 | interrupt-names = "host-wake"; |
| 910 | }; |
| 911 | }; |
| 912 | |
| 913 | sdmmc3: mmc@c8000400 { |
| 914 | status = "okay"; |
| 915 | bus-width = <4>; |
| 916 | cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; |
| 917 | wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; |
| 918 | power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; |
| 919 | vmmc-supply = <&vdd_3v3_sys>; |
| 920 | vqmmc-supply = <&vdd_3v3_sys>; |
| 921 | }; |
| 922 | |
| 923 | sdmmc4: mmc@c8000600 { |
| 924 | status = "okay"; |
| 925 | bus-width = <8>; |
| 926 | vmmc-supply = <&vcore_emmc>; |
| 927 | vqmmc-supply = <&vdd_3v3_sys>; |
| 928 | non-removable; |
| 929 | }; |
| 930 | |
| 931 | mains: ac-adapter-detect { |
| 932 | compatible = "gpio-charger"; |
| 933 | charger-type = "mains"; |
| 934 | gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; |
| 935 | }; |
| 936 | |
| 937 | backlight: backlight { |
| 938 | compatible = "pwm-backlight"; |
| 939 | |
| 940 | enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; |
| 941 | power-supply = <&vdd_3v3_sys>; |
| 942 | pwms = <&pwm 2 4000000>; |
| 943 | |
| 944 | brightness-levels = <7 255>; |
| 945 | num-interpolated-steps = <248>; |
| 946 | default-brightness-level = <20>; |
| 947 | }; |
| 948 | |
| 949 | /* PMIC has a built-in 32KHz oscillator which is used by PMC */ |
| 950 | clk32k_in: clock-32k-in { |
| 951 | compatible = "fixed-clock"; |
| 952 | clock-frequency = <32768>; |
| 953 | #clock-cells = <0>; |
| 954 | }; |
| 955 | |
| 956 | cpus { |
| 957 | cpu0: cpu@0 { |
| 958 | cpu-supply = <&vdd_cpu>; |
| 959 | operating-points-v2 = <&cpu0_opp_table>; |
| 960 | #cooling-cells = <2>; |
| 961 | }; |
| 962 | |
| 963 | cpu1: cpu@1 { |
| 964 | cpu-supply = <&vdd_cpu>; |
| 965 | operating-points-v2 = <&cpu0_opp_table>; |
| 966 | #cooling-cells = <2>; |
| 967 | }; |
| 968 | }; |
| 969 | |
| 970 | gpio-keys { |
| 971 | compatible = "gpio-keys"; |
| 972 | |
| 973 | dock-hall-sensor { |
| 974 | label = "Lid"; |
| 975 | gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; |
| 976 | linux,input-type = <EV_SW>; |
| 977 | linux,code = <SW_LID>; |
| 978 | debounce-interval = <500>; |
| 979 | wakeup-event-action = <EV_ACT_ASSERTED>; |
| 980 | wakeup-source; |
| 981 | }; |
| 982 | |
| 983 | power { |
| 984 | label = "Power"; |
| 985 | gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
| 986 | linux,code = <KEY_POWER>; |
| 987 | debounce-interval = <10>; |
| 988 | wakeup-event-action = <EV_ACT_ASSERTED>; |
| 989 | wakeup-source; |
| 990 | }; |
| 991 | |
| 992 | volume-up { |
| 993 | label = "Volume Up"; |
| 994 | gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; |
| 995 | linux,code = <KEY_VOLUMEUP>; |
| 996 | debounce-interval = <10>; |
| 997 | wakeup-event-action = <EV_ACT_ASSERTED>; |
| 998 | wakeup-source; |
| 999 | }; |
| 1000 | |
| 1001 | volume-down { |
| 1002 | label = "Volume Down"; |
| 1003 | gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; |
| 1004 | linux,code = <KEY_VOLUMEDOWN>; |
| 1005 | debounce-interval = <10>; |
| 1006 | wakeup-event-action = <EV_ACT_ASSERTED>; |
| 1007 | wakeup-source; |
| 1008 | }; |
| 1009 | }; |
| 1010 | |
| 1011 | display-panel { |
| 1012 | compatible = "panel-lvds"; |
| 1013 | |
| 1014 | /* AUO B101EW05 using custom timings */ |
| 1015 | |
| 1016 | backlight = <&backlight>; |
| 1017 | ddc-i2c-bus = <&lvds_ddc>; |
| 1018 | power-supply = <&vdd_pnl_reg>; |
| 1019 | |
| 1020 | width-mm = <218>; |
| 1021 | height-mm = <135>; |
| 1022 | |
| 1023 | data-mapping = "jeida-18"; |
| 1024 | |
| 1025 | panel-timing { |
| 1026 | clock-frequency = <71200000>; |
| 1027 | hactive = <1280>; |
| 1028 | vactive = <800>; |
| 1029 | hfront-porch = <8>; |
| 1030 | hback-porch = <18>; |
| 1031 | hsync-len = <184>; |
| 1032 | vsync-len = <3>; |
| 1033 | vfront-porch = <4>; |
| 1034 | vback-porch = <8>; |
| 1035 | }; |
| 1036 | |
| 1037 | port { |
| 1038 | panel_input: endpoint { |
| 1039 | remote-endpoint = <&lvds_encoder_output>; |
| 1040 | }; |
| 1041 | }; |
| 1042 | }; |
| 1043 | |
| 1044 | i2cmux { |
| 1045 | compatible = "i2c-mux-pinctrl"; |
| 1046 | #address-cells = <1>; |
| 1047 | #size-cells = <0>; |
| 1048 | |
| 1049 | i2c-parent = <&i2c2>; |
| 1050 | |
| 1051 | pinctrl-names = "ddc", "pta", "idle"; |
| 1052 | pinctrl-0 = <&state_i2cmux_ddc>; |
| 1053 | pinctrl-1 = <&state_i2cmux_pta>; |
| 1054 | pinctrl-2 = <&state_i2cmux_idle>; |
| 1055 | |
| 1056 | hdmi_ddc: i2c@0 { |
| 1057 | reg = <0>; |
| 1058 | #address-cells = <1>; |
| 1059 | #size-cells = <0>; |
| 1060 | }; |
| 1061 | |
| 1062 | lvds_ddc: i2c@1 { |
| 1063 | reg = <1>; |
| 1064 | #address-cells = <1>; |
| 1065 | #size-cells = <0>; |
| 1066 | |
| 1067 | smart-battery@b { |
| 1068 | compatible = "ti,bq20z75", "sbs,sbs-battery"; |
| 1069 | reg = <0xb>; |
| 1070 | sbs,i2c-retry-count = <2>; |
| 1071 | sbs,poll-retry-count = <10>; |
| 1072 | power-supplies = <&mains>; |
| 1073 | }; |
| 1074 | }; |
| 1075 | }; |
| 1076 | |
| 1077 | lvds-encoder { |
| 1078 | compatible = "ti,sn75lvds83", "lvds-encoder"; |
| 1079 | |
| 1080 | powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; |
| 1081 | power-supply = <&vdd_3v3_sys>; |
| 1082 | |
| 1083 | ports { |
| 1084 | #address-cells = <1>; |
| 1085 | #size-cells = <0>; |
| 1086 | |
| 1087 | port@0 { |
| 1088 | reg = <0>; |
| 1089 | |
| 1090 | lvds_encoder_input: endpoint { |
| 1091 | remote-endpoint = <&lcd_output>; |
| 1092 | }; |
| 1093 | }; |
| 1094 | |
| 1095 | port@1 { |
| 1096 | reg = <1>; |
| 1097 | |
| 1098 | lvds_encoder_output: endpoint { |
| 1099 | remote-endpoint = <&panel_input>; |
| 1100 | }; |
| 1101 | }; |
| 1102 | }; |
| 1103 | }; |
| 1104 | |
| 1105 | vdd_5v0_sys: regulator-5v0 { |
| 1106 | compatible = "regulator-fixed"; |
| 1107 | regulator-name = "vdd_5v0"; |
| 1108 | regulator-min-microvolt = <5000000>; |
| 1109 | regulator-max-microvolt = <5000000>; |
| 1110 | regulator-always-on; |
| 1111 | }; |
| 1112 | |
| 1113 | vdd_3v3_sys: regulator-3v3 { |
| 1114 | compatible = "regulator-fixed"; |
| 1115 | regulator-name = "vdd_3v3_vs"; |
| 1116 | regulator-min-microvolt = <3300000>; |
| 1117 | regulator-max-microvolt = <3300000>; |
| 1118 | regulator-always-on; |
| 1119 | vin-supply = <&vdd_5v0_sys>; |
| 1120 | }; |
| 1121 | |
| 1122 | regulator-pcie { |
| 1123 | compatible = "regulator-fixed"; |
| 1124 | regulator-name = "pcie_vdd"; |
| 1125 | regulator-min-microvolt = <1500000>; |
| 1126 | regulator-max-microvolt = <1500000>; |
| 1127 | gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; |
| 1128 | regulator-always-on; |
| 1129 | }; |
| 1130 | |
| 1131 | vdd_pnl_reg: regulator-panel { |
| 1132 | compatible = "regulator-fixed"; |
| 1133 | regulator-name = "vdd_pnl"; |
| 1134 | regulator-min-microvolt = <2800000>; |
| 1135 | regulator-max-microvolt = <2800000>; |
| 1136 | gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; |
| 1137 | enable-active-high; |
| 1138 | }; |
| 1139 | |
| 1140 | vdd_1v8_sys: regulator-1v8 { |
| 1141 | compatible = "regulator-fixed"; |
| 1142 | regulator-name = "vdd_1v8_vs"; |
| 1143 | regulator-min-microvolt = <1800000>; |
| 1144 | regulator-max-microvolt = <1800000>; |
| 1145 | regulator-always-on; |
| 1146 | vin-supply = <&vdd_5v0_sys>; |
| 1147 | }; |
| 1148 | |
| 1149 | vdd_hdmi_en: regulator-hdmi { |
| 1150 | compatible = "regulator-fixed"; |
| 1151 | regulator-name = "vdd_5v0_hdmi_en"; |
| 1152 | regulator-min-microvolt = <5000000>; |
| 1153 | regulator-max-microvolt = <5000000>; |
| 1154 | regulator-always-on; |
| 1155 | vin-supply = <&vdd_5v0_sys>; |
| 1156 | gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; |
| 1157 | enable-active-high; |
| 1158 | }; |
| 1159 | |
| 1160 | sound { |
| 1161 | compatible = "asus,tegra-audio-wm8903-tf101", |
| 1162 | "nvidia,tegra-audio-wm8903"; |
| 1163 | nvidia,model = "Asus EeePad Transformer WM8903"; |
| 1164 | |
| 1165 | nvidia,audio-routing = |
| 1166 | "Headphone Jack", "HPOUTR", |
| 1167 | "Headphone Jack", "HPOUTL", |
| 1168 | "Int Spk", "ROP", |
| 1169 | "Int Spk", "RON", |
| 1170 | "Int Spk", "LOP", |
| 1171 | "Int Spk", "LON", |
| 1172 | "Mic Jack", "MICBIAS", |
| 1173 | "IN1L", "Mic Jack"; |
| 1174 | |
| 1175 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 1176 | nvidia,audio-codec = <&wm8903>; |
| 1177 | |
| 1178 | nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
| 1179 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; |
| 1180 | nvidia,headset; |
| 1181 | |
| 1182 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
| 1183 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, |
| 1184 | <&tegra_car TEGRA20_CLK_CDEV1>; |
| 1185 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
| 1186 | }; |
| 1187 | |
| 1188 | thermal-zones { |
| 1189 | /* |
| 1190 | * NCT1008 has two sensors: |
| 1191 | * |
| 1192 | * 0: internal that monitors ambient/skin temperature |
| 1193 | * 1: external that is connected to the CPU's diode |
| 1194 | * |
| 1195 | * Ideally we should use userspace thermal governor, |
| 1196 | * but it's a much more complex solution. The "skin" |
| 1197 | * zone is a simpler solution which prevents TF101 from |
| 1198 | * getting too hot from a user's tactile perspective. |
| 1199 | * The CPU zone is intended to protect silicon from damage. |
| 1200 | */ |
| 1201 | |
| 1202 | skin-thermal { |
| 1203 | polling-delay-passive = <1000>; /* milliseconds */ |
| 1204 | polling-delay = <5000>; /* milliseconds */ |
| 1205 | |
| 1206 | thermal-sensors = <&nct1008 0>; |
| 1207 | |
| 1208 | trips { |
| 1209 | trip0: skin-alert { |
| 1210 | /* start throttling at 60C */ |
| 1211 | temperature = <60000>; |
| 1212 | hysteresis = <200>; |
| 1213 | type = "passive"; |
| 1214 | }; |
| 1215 | |
| 1216 | trip1: skin-crit { |
| 1217 | /* shut down at 70C */ |
| 1218 | temperature = <70000>; |
| 1219 | hysteresis = <2000>; |
| 1220 | type = "critical"; |
| 1221 | }; |
| 1222 | }; |
| 1223 | |
| 1224 | cooling-maps { |
| 1225 | map0 { |
| 1226 | trip = <&trip0>; |
| 1227 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| 1228 | <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| 1229 | }; |
| 1230 | }; |
| 1231 | }; |
| 1232 | |
| 1233 | cpu-thermal { |
| 1234 | polling-delay-passive = <1000>; /* milliseconds */ |
| 1235 | polling-delay = <5000>; /* milliseconds */ |
| 1236 | |
| 1237 | thermal-sensors = <&nct1008 1>; |
| 1238 | |
| 1239 | trips { |
| 1240 | trip2: cpu-alert { |
| 1241 | /* throttle at 85C until temperature drops to 84.8C */ |
| 1242 | temperature = <85000>; |
| 1243 | hysteresis = <200>; |
| 1244 | type = "passive"; |
| 1245 | }; |
| 1246 | |
| 1247 | trip3: cpu-crit { |
| 1248 | /* shut down at 90C */ |
| 1249 | temperature = <90000>; |
| 1250 | hysteresis = <2000>; |
| 1251 | type = "critical"; |
| 1252 | }; |
| 1253 | }; |
| 1254 | |
| 1255 | cooling-maps { |
| 1256 | map1 { |
| 1257 | trip = <&trip2>; |
| 1258 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| 1259 | <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| 1260 | }; |
| 1261 | }; |
| 1262 | }; |
| 1263 | }; |
| 1264 | |
| 1265 | brcm_wifi_pwrseq: wifi-pwrseq { |
| 1266 | compatible = "mmc-pwrseq-simple"; |
| 1267 | |
| 1268 | clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; |
| 1269 | clock-names = "ext_clock"; |
| 1270 | |
| 1271 | reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; |
| 1272 | post-power-on-delay-ms = <200>; |
| 1273 | power-off-delay-us = <200>; |
| 1274 | }; |
| 1275 | }; |
| 1276 | |
| 1277 | &emc_icc_dvfs_opp_table { |
| 1278 | /delete-node/ opp-666000000; |
| 1279 | /delete-node/ opp-760000000; |
| 1280 | }; |