| Thomas Gleixner | ec8f24b | 2019-05-19 13:07:45 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| Michael Hennerich | cd1678f | 2012-05-29 12:41:19 +0200 | [diff] [blame] | 2 | # |
| 3 | # Frequency |
| 4 | # Direct Digital Synthesis drivers (DDS) |
| 5 | # Clock Distribution device drivers |
| 6 | # Phase-Locked Loop (PLL) frequency synthesizers |
| 7 | # |
| Lars-Peter Clausen | 3edc84e | 2013-07-15 08:45:00 +0100 | [diff] [blame] | 8 | # When adding new entries keep the list in alphabetical order |
| Michael Hennerich | cd1678f | 2012-05-29 12:41:19 +0200 | [diff] [blame] | 9 | |
| 10 | menu "Frequency Synthesizers DDS/PLL" |
| 11 | |
| 12 | menu "Clock Generator/Distribution" |
| 13 | |
| 14 | config AD9523 |
| 15 | tristate "Analog Devices AD9523 Low Jitter Clock Generator" |
| 16 | depends on SPI |
| 17 | help |
| 18 | Say yes here to build support for Analog Devices AD9523 Low Jitter |
| 19 | Clock Generator. The driver provides direct access via sysfs. |
| 20 | |
| 21 | To compile this driver as a module, choose M here: the |
| 22 | module will be called ad9523. |
| 23 | |
| 24 | endmenu |
| Michael Hennerich | e31166f | 2012-05-29 12:41:20 +0200 | [diff] [blame] | 25 | |
| 26 | # |
| 27 | # Phase-Locked Loop (PLL) frequency synthesizers |
| 28 | # |
| 29 | |
| 30 | menu "Phase-Locked Loop (PLL) frequency synthesizers" |
| 31 | |
| 32 | config ADF4350 |
| 33 | tristate "Analog Devices ADF4350/ADF4351 Wideband Synthesizers" |
| 34 | depends on SPI |
| 35 | help |
| 36 | Say yes here to build support for Analog Devices ADF4350/ADF4351 |
| 37 | Wideband Synthesizers. The driver provides direct access via sysfs. |
| 38 | |
| 39 | To compile this driver as a module, choose M here: the |
| 40 | module will be called adf4350. |
| 41 | |
| 42 | endmenu |
| Michael Hennerich | cd1678f | 2012-05-29 12:41:19 +0200 | [diff] [blame] | 43 | endmenu |