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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 36386d6e54d0ebcd5b2e0869f837800293d94c3c / . / arch / arm / boot / dts / sun4i-a10.dtsi
blob: f6405204e7e219d095170c3e9e2b6d05e9e330b4 [file] [log] [blame]
Stefan Roese7423d2d2012-11-26 15:46:12 +0100[diff] [blame]1/*
2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "sunxi.dtsi"
14
15/ {
16 memory {
17 reg = <0x40000000 0x80000000>;
18 };
Maxime Ripard874b4e42013-01-26 15:36:54 +0100[diff] [blame]19
20 soc {
Maxime Riparde10911e2013-01-27 19:26:05 +0100[diff] [blame]21 pio: pinctrl@01c20800 {
Maxime Ripard874b4e42013-01-26 15:36:54 +0100[diff] [blame]22 compatible = "allwinner,sun4i-a10-pinctrl";
23 reg = <0x01c20800 0x400>;
Emilio López36386d62013-03-27 18:20:41 -0300[diff] [blame^]24 clocks = <&apb0_gates 5>;
Maxime Riparde10911e2013-01-27 19:26:05 +0100[diff] [blame]25 gpio-controller;
Maxime Ripard874b4e42013-01-26 15:36:54 +0100[diff] [blame]26 #address-cells = <1>;
27 #size-cells = <0>;
Maxime Riparde10911e2013-01-27 19:26:05 +0100[diff] [blame]28 #gpio-cells = <3>;
Maxime Ripard581981b2013-01-26 15:36:55 +0100[diff] [blame]29
30 uart0_pins_a: uart0@0 {
31 allwinner,pins = "PB22", "PB23";
32 allwinner,function = "uart0";
33 allwinner,drive = <0>;
34 allwinner,pull = <0>;
35 };
36
37 uart0_pins_b: uart0@1 {
38 allwinner,pins = "PF2", "PF4";
39 allwinner,function = "uart0";
40 allwinner,drive = <0>;
41 allwinner,pull = <0>;
42 };
43
44 uart1_pins_a: uart1@0 {
45 allwinner,pins = "PA10", "PA11";
46 allwinner,function = "uart1";
47 allwinner,drive = <0>;
48 allwinner,pull = <0>;
49 };
Maxime Ripard874b4e42013-01-26 15:36:54 +0100[diff] [blame]50 };
Maxime Ripard89b3c992013-02-20 17:25:03 -0800[diff] [blame]51
52 uart0: serial@01c28000 {
53 compatible = "snps,dw-apb-uart";
54 reg = <0x01c28000 0x400>;
55 interrupts = <1>;
56 reg-shift = <2>;
57 reg-io-width = <4>;
Emilio López9ff49ec2013-03-27 18:20:39 -0300[diff] [blame]58 clocks = <&apb1_gates 16>;
Maxime Ripard89b3c992013-02-20 17:25:03 -0800[diff] [blame]59 status = "disabled";
60 };
Maxime Ripard76f14d0a2013-02-20 17:38:27 -0800[diff] [blame]61
62 uart2: serial@01c28800 {
63 compatible = "snps,dw-apb-uart";
64 reg = <0x01c28800 0x400>;
65 interrupts = <3>;
66 reg-shift = <2>;
67 reg-io-width = <4>;
Emilio López9ff49ec2013-03-27 18:20:39 -0300[diff] [blame]68 clocks = <&apb1_gates 18>;
Maxime Ripard76f14d0a2013-02-20 17:38:27 -0800[diff] [blame]69 status = "disabled";
70 };
71
72 uart4: serial@01c29000 {
73 compatible = "snps,dw-apb-uart";
74 reg = <0x01c29000 0x400>;
75 interrupts = <17>;
76 reg-shift = <2>;
77 reg-io-width = <4>;
Emilio López9ff49ec2013-03-27 18:20:39 -0300[diff] [blame]78 clocks = <&apb1_gates 20>;
Maxime Ripard76f14d0a2013-02-20 17:38:27 -0800[diff] [blame]79 status = "disabled";
80 };
81
82 uart5: serial@01c29400 {
83 compatible = "snps,dw-apb-uart";
84 reg = <0x01c29400 0x400>;
85 interrupts = <18>;
86 reg-shift = <2>;
87 reg-io-width = <4>;
Emilio López9ff49ec2013-03-27 18:20:39 -0300[diff] [blame]88 clocks = <&apb1_gates 21>;
Maxime Ripard76f14d0a2013-02-20 17:38:27 -0800[diff] [blame]89 status = "disabled";
90 };
91
92 uart6: serial@01c29800 {
93 compatible = "snps,dw-apb-uart";
94 reg = <0x01c29800 0x400>;
95 interrupts = <19>;
96 reg-shift = <2>;
97 reg-io-width = <4>;
Emilio López9ff49ec2013-03-27 18:20:39 -0300[diff] [blame]98 clocks = <&apb1_gates 22>;
Maxime Ripard76f14d0a2013-02-20 17:38:27 -0800[diff] [blame]99 status = "disabled";
100 };
101
102 uart7: serial@01c29c00 {
103 compatible = "snps,dw-apb-uart";
104 reg = <0x01c29c00 0x400>;
105 interrupts = <20>;
106 reg-shift = <2>;
107 reg-io-width = <4>;
Emilio López9ff49ec2013-03-27 18:20:39 -0300[diff] [blame]108 clocks = <&apb1_gates 23>;
Maxime Ripard76f14d0a2013-02-20 17:38:27 -0800[diff] [blame]109 status = "disabled";
110 };
Maxime Ripard874b4e42013-01-26 15:36:54 +0100[diff] [blame]111 };
Stefan Roese7423d2d2012-11-26 15:46:12 +0100[diff] [blame]112};