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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 35f210eca0fcafacb1f8b53d36e3738f7897a474 / . / arch / arm / boot / dts / tegra30.dtsi
blob: 7159bd353f8cff332dc271561f29c42406777327 [file] [log] [blame]
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>;
6
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]7 host1x {
8 compatible = "nvidia,tegra30-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]12 clocks = <&tegra_car 28>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]13
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 ranges = <0x54000000 0x54000000 0x04000000>;
18
19 mpe {
20 compatible = "nvidia,tegra30-mpe";
21 reg = <0x54040000 0x00040000>;
22 interrupts = <0 68 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]23 clocks = <&tegra_car 60>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]24 };
25
26 vi {
27 compatible = "nvidia,tegra30-vi";
28 reg = <0x54080000 0x00040000>;
29 interrupts = <0 69 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]30 clocks = <&tegra_car 164>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]31 };
32
33 epp {
34 compatible = "nvidia,tegra30-epp";
35 reg = <0x540c0000 0x00040000>;
36 interrupts = <0 70 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]37 clocks = <&tegra_car 19>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]38 };
39
40 isp {
41 compatible = "nvidia,tegra30-isp";
42 reg = <0x54100000 0x00040000>;
43 interrupts = <0 71 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]44 clocks = <&tegra_car 23>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]45 };
46
47 gr2d {
48 compatible = "nvidia,tegra30-gr2d";
49 reg = <0x54140000 0x00040000>;
50 interrupts = <0 72 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]51 clocks = <&tegra_car 21>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]52 };
53
54 gr3d {
55 compatible = "nvidia,tegra30-gr3d";
56 reg = <0x54180000 0x00040000>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]57 clocks = <&tegra_car 24 &tegra_car 98>;
58 clock-names = "3d", "3d2";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]59 };
60
61 dc@54200000 {
62 compatible = "nvidia,tegra30-dc";
63 reg = <0x54200000 0x00040000>;
64 interrupts = <0 73 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]65 clocks = <&tegra_car 27>, <&tegra_car 179>;
66 clock-names = "disp1", "parent";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]67
68 rgb {
69 status = "disabled";
70 };
71 };
72
73 dc@54240000 {
74 compatible = "nvidia,tegra30-dc";
75 reg = <0x54240000 0x00040000>;
76 interrupts = <0 74 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]77 clocks = <&tegra_car 26>, <&tegra_car 179>;
78 clock-names = "disp2", "parent";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]79
80 rgb {
81 status = "disabled";
82 };
83 };
84
85 hdmi {
86 compatible = "nvidia,tegra30-hdmi";
87 reg = <0x54280000 0x00040000>;
88 interrupts = <0 75 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]89 clocks = <&tegra_car 51>, <&tegra_car 189>;
90 clock-names = "hdmi", "parent";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]91 status = "disabled";
92 };
93
94 tvo {
95 compatible = "nvidia,tegra30-tvo";
96 reg = <0x542c0000 0x00040000>;
97 interrupts = <0 76 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]98 clocks = <&tegra_car 169>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]99 status = "disabled";
100 };
101
102 dsi {
103 compatible = "nvidia,tegra30-dsi";
104 reg = <0x54300000 0x00040000>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]105 clocks = <&tegra_car 48>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]106 status = "disabled";
107 };
108 };
109
Stephen Warren73368ba2012-09-19 14:17:24 -0600[diff] [blame]110 timer@50004600 {
111 compatible = "arm,cortex-a9-twd-timer";
112 reg = <0x50040600 0x20>;
113 interrupts = <1 13 0xf04>;
114 };
115
Joseph Lo5ab134a2012-10-29 18:25:45 +0800[diff] [blame]116 cache-controller@50043000 {
117 compatible = "arm,pl310-cache";
118 reg = <0x50043000 0x1000>;
119 arm,data-latency = <6 6 2>;
120 arm,tag-latency = <5 5 2>;
121 cache-unified;
122 cache-level = <2>;
123 };
124
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]125 intc: interrupt-controller {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]126 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]127 reg = <0x50041000 0x1000
128 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]129 interrupt-controller;
130 #interrupt-cells = <3>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]131 };
132
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]133 timer@60005000 {
134 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
135 reg = <0x60005000 0x400>;
136 interrupts = <0 0 0x04
137 0 1 0x04
138 0 41 0x04
139 0 42 0x04
140 0 121 0x04
141 0 122 0x04>;
142 };
143
Prashant Gaikwad95985662013-01-11 13:16:23 +0530[diff] [blame]144 tegra_car: clock {
145 compatible = "nvidia,tegra30-car";
146 reg = <0x60006000 0x1000>;
147 #clock-cells = <1>;
148 };
149
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]150 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]151 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
152 reg = <0x6000a000 0x1400>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]153 interrupts = <0 104 0x04
154 0 105 0x04
155 0 106 0x04
156 0 107 0x04
157 0 108 0x04
158 0 109 0x04
159 0 110 0x04
160 0 111 0x04
161 0 112 0x04
162 0 113 0x04
163 0 114 0x04
164 0 115 0x04
165 0 116 0x04
166 0 117 0x04
167 0 118 0x04
168 0 119 0x04
169 0 128 0x04
170 0 129 0x04
171 0 130 0x04
172 0 131 0x04
173 0 132 0x04
174 0 133 0x04
175 0 134 0x04
176 0 135 0x04
177 0 136 0x04
178 0 137 0x04
179 0 138 0x04
180 0 139 0x04
181 0 140 0x04
182 0 141 0x04
183 0 142 0x04
184 0 143 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]185 clocks = <&tegra_car 34>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]186 };
187
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]188 ahb: ahb {
189 compatible = "nvidia,tegra30-ahb";
190 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
191 };
192
193 gpio: gpio {
Laxman Dewangan35f210e2012-12-19 20:27:12 +0530[diff] [blame^]194 compatible = "nvidia,tegra30-gpio";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]195 reg = <0x6000d000 0x1000>;
196 interrupts = <0 32 0x04
197 0 33 0x04
198 0 34 0x04
199 0 35 0x04
200 0 55 0x04
201 0 87 0x04
202 0 89 0x04
203 0 125 0x04>;
204 #gpio-cells = <2>;
205 gpio-controller;
206 #interrupt-cells = <2>;
207 interrupt-controller;
208 };
209
210 pinmux: pinmux {
211 compatible = "nvidia,tegra30-pinmux";
Pritesh Raithatha322337b2012-10-30 15:37:09 +0530[diff] [blame]212 reg = <0x70000868 0xd4 /* Pad control registers */
213 0x70003000 0x3e4>; /* Mux registers */
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]214 };
215
216 serial@70006000 {
217 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
218 reg = <0x70006000 0x40>;
219 reg-shift = <2>;
220 interrupts = <0 36 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]221 clocks = <&tegra_car 6>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]222 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]223 };
224
225 serial@70006040 {
226 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
227 reg = <0x70006040 0x40>;
228 reg-shift = <2>;
229 interrupts = <0 37 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]230 clocks = <&tegra_car 160>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]231 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]232 };
233
234 serial@70006200 {
235 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
236 reg = <0x70006200 0x100>;
237 reg-shift = <2>;
238 interrupts = <0 46 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]239 clocks = <&tegra_car 55>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]240 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]241 };
242
243 serial@70006300 {
244 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
245 reg = <0x70006300 0x100>;
246 reg-shift = <2>;
247 interrupts = <0 90 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]248 clocks = <&tegra_car 65>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]249 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]250 };
251
252 serial@70006400 {
253 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
254 reg = <0x70006400 0x100>;
255 reg-shift = <2>;
256 interrupts = <0 91 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]257 clocks = <&tegra_car 66>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]258 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]259 };
260
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]261 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]262 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
263 reg = <0x7000a000 0x100>;
264 #pwm-cells = <2>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]265 clocks = <&tegra_car 17>;
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]266 };
267
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame]268 rtc {
269 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
270 reg = <0x7000e000 0x100>;
271 interrupts = <0 2 0x04>;
272 };
273
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]274 i2c@7000c000 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]275 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]276 reg = <0x7000c000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]277 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]278 #address-cells = <1>;
279 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]280 clocks = <&tegra_car 12>, <&tegra_car 182>;
281 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]282 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]283 };
284
285 i2c@7000c400 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]286 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]287 reg = <0x7000c400 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]288 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]289 #address-cells = <1>;
290 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]291 clocks = <&tegra_car 54>, <&tegra_car 182>;
292 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]293 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]294 };
295
296 i2c@7000c500 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]297 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]298 reg = <0x7000c500 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]299 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]300 #address-cells = <1>;
301 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]302 clocks = <&tegra_car 67>, <&tegra_car 182>;
303 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]304 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]305 };
306
307 i2c@7000c700 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]308 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
309 reg = <0x7000c700 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]310 interrupts = <0 120 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]311 #address-cells = <1>;
312 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]313 clocks = <&tegra_car 103>, <&tegra_car 182>;
314 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]315 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]316 };
317
318 i2c@7000d000 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]319 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]320 reg = <0x7000d000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]321 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]322 #address-cells = <1>;
323 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]324 clocks = <&tegra_car 47>, <&tegra_car 182>;
325 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]326 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]327 };
328
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]329 spi@7000d400 {
330 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
331 reg = <0x7000d400 0x200>;
332 interrupts = <0 59 0x04>;
333 nvidia,dma-request-selector = <&apbdma 15>;
334 #address-cells = <1>;
335 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]336 clocks = <&tegra_car 41>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]337 status = "disabled";
338 };
339
340 spi@7000d600 {
341 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
342 reg = <0x7000d600 0x200>;
343 interrupts = <0 82 0x04>;
344 nvidia,dma-request-selector = <&apbdma 16>;
345 #address-cells = <1>;
346 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]347 clocks = <&tegra_car 44>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]348 status = "disabled";
349 };
350
351 spi@7000d800 {
352 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
353 reg = <0x7000d480 0x200>;
354 interrupts = <0 83 0x04>;
355 nvidia,dma-request-selector = <&apbdma 17>;
356 #address-cells = <1>;
357 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]358 clocks = <&tegra_car 46>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]359 status = "disabled";
360 };
361
362 spi@7000da00 {
363 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
364 reg = <0x7000da00 0x200>;
365 interrupts = <0 93 0x04>;
366 nvidia,dma-request-selector = <&apbdma 18>;
367 #address-cells = <1>;
368 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]369 clocks = <&tegra_car 68>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]370 status = "disabled";
371 };
372
373 spi@7000dc00 {
374 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
375 reg = <0x7000dc00 0x200>;
376 interrupts = <0 94 0x04>;
377 nvidia,dma-request-selector = <&apbdma 27>;
378 #address-cells = <1>;
379 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]380 clocks = <&tegra_car 104>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]381 status = "disabled";
382 };
383
384 spi@7000de00 {
385 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
386 reg = <0x7000de00 0x200>;
387 interrupts = <0 79 0x04>;
388 nvidia,dma-request-selector = <&apbdma 28>;
389 #address-cells = <1>;
390 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]391 clocks = <&tegra_car 105>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]392 status = "disabled";
393 };
394
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]395 pmc {
396 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
397 reg = <0x7000e400 0x400>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]398 };
399
hdoyu@nvidia.coma9140aa2012-05-16 19:47:44 +0000[diff] [blame]400 memory-controller {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]401 compatible = "nvidia,tegra30-mc";
402 reg = <0x7000f000 0x010
403 0x7000f03c 0x1b4
404 0x7000f200 0x028
405 0x7000f284 0x17c>;
406 interrupts = <0 77 0x04>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]407 };
408
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]409 smmu {
410 compatible = "nvidia,tegra30-smmu";
411 reg = <0x7000f010 0x02c
412 0x7000f1f0 0x010
413 0x7000f228 0x05c>;
414 nvidia,#asids = <4>; /* # of ASIDs */
415 dma-window = <0 0x40000000>; /* IOVA start & length */
416 nvidia,ahb = <&ahb>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]417 };
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]418
419 ahub {
420 compatible = "nvidia,tegra30-ahub";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]421 reg = <0x70080000 0x200
422 0x70080200 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]423 interrupts = <0 103 0x04>;
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]424 nvidia,dma-request-selector = <&apbdma 1>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]425 clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
426 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
427 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
428 <&tegra_car 110>, <&tegra_car 162>;
429 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
430 "i2s3", "i2s4", "dam0", "dam1", "dam2",
431 "spdif_in";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]432 ranges;
433 #address-cells = <1>;
434 #size-cells = <1>;
435
436 tegra_i2s0: i2s@70080300 {
437 compatible = "nvidia,tegra30-i2s";
438 reg = <0x70080300 0x100>;
439 nvidia,ahub-cif-ids = <4 4>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]440 clocks = <&tegra_car 30>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]441 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]442 };
443
444 tegra_i2s1: i2s@70080400 {
445 compatible = "nvidia,tegra30-i2s";
446 reg = <0x70080400 0x100>;
447 nvidia,ahub-cif-ids = <5 5>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]448 clocks = <&tegra_car 11>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]449 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]450 };
451
452 tegra_i2s2: i2s@70080500 {
453 compatible = "nvidia,tegra30-i2s";
454 reg = <0x70080500 0x100>;
455 nvidia,ahub-cif-ids = <6 6>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]456 clocks = <&tegra_car 18>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]457 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]458 };
459
460 tegra_i2s3: i2s@70080600 {
461 compatible = "nvidia,tegra30-i2s";
462 reg = <0x70080600 0x100>;
463 nvidia,ahub-cif-ids = <7 7>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]464 clocks = <&tegra_car 101>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]465 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]466 };
467
468 tegra_i2s4: i2s@70080700 {
469 compatible = "nvidia,tegra30-i2s";
470 reg = <0x70080700 0x100>;
471 nvidia,ahub-cif-ids = <8 8>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]472 clocks = <&tegra_car 102>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]473 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]474 };
475 };
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]476
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]477 sdhci@78000000 {
478 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
479 reg = <0x78000000 0x200>;
480 interrupts = <0 14 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]481 clocks = <&tegra_car 14>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]482 status = "disabled";
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]483 };
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]484
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]485 sdhci@78000200 {
486 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
487 reg = <0x78000200 0x200>;
488 interrupts = <0 15 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]489 clocks = <&tegra_car 9>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]490 status = "disabled";
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]491 };
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]492
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]493 sdhci@78000400 {
494 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
495 reg = <0x78000400 0x200>;
496 interrupts = <0 19 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]497 clocks = <&tegra_car 69>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]498 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]499 };
500
501 sdhci@78000600 {
502 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
503 reg = <0x78000600 0x200>;
504 interrupts = <0 31 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]505 clocks = <&tegra_car 15>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]506 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]507 };
508
Hiroshi Doyu7d19a342013-01-11 15:11:54 +0200[diff] [blame]509 cpus {
510 #address-cells = <1>;
511 #size-cells = <0>;
512
513 cpu@0 {
514 device_type = "cpu";
515 compatible = "arm,cortex-a9";
516 reg = <0>;
517 };
518
519 cpu@1 {
520 device_type = "cpu";
521 compatible = "arm,cortex-a9";
522 reg = <1>;
523 };
524
525 cpu@2 {
526 device_type = "cpu";
527 compatible = "arm,cortex-a9";
528 reg = <2>;
529 };
530
531 cpu@3 {
532 device_type = "cpu";
533 compatible = "arm,cortex-a9";
534 reg = <3>;
535 };
536 };
537
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]538 pmu {
539 compatible = "arm,cortex-a9-pmu";
540 interrupts = <0 144 0x04
541 0 145 0x04
542 0 146 0x04
543 0 147 0x04>;
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]544 };
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]545};