blob: 127b62ce7b1eb282f822e5b5f122a62569264a14 [file] [log] [blame]
Thomas Gleixner74ba9202019-05-20 09:19:02 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Kevin Hilman7c6337e2007-04-30 19:37:19 +01002/*
3 * TI DaVinci serial driver
4 *
5 * Copyright (C) 2006 Texas Instruments.
Kevin Hilman7c6337e2007-04-30 19:37:19 +01006 */
7
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/serial_8250.h>
11#include <linux/serial_reg.h>
12#include <linux/platform_device.h>
13#include <linux/delay.h>
14#include <linux/clk.h>
Russell Kingfced80c2008-09-06 12:10:45 +010015#include <linux/io.h>
Kevin Hilman7c6337e2007-04-30 19:37:19 +010016
Russell Kinga09e64f2008-08-05 16:14:15 +010017#include <mach/serial.h>
Kevin Hilman617b9252009-04-14 08:04:26 -050018#include <mach/cputype.h>
Kevin Hilman7c6337e2007-04-30 19:37:19 +010019
Kevin Hilman617b9252009-04-14 08:04:26 -050020static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
21 int value)
Kevin Hilman7c6337e2007-04-30 19:37:19 +010022{
23 offset <<= p->regshift;
Cyril Chemparathy9ee1ace2010-05-02 14:28:13 -040024
25 WARN_ONCE(!p->membase, "unmapped write: uart[%d]\n", offset);
26
27 __raw_writel(value, p->membase + offset);
Kevin Hilman7c6337e2007-04-30 19:37:19 +010028}
29
Kevin Hilman7c6337e2007-04-30 19:37:19 +010030static void __init davinci_serial_reset(struct plat_serial8250_port *p)
31{
Kevin Hilman7c6337e2007-04-30 19:37:19 +010032 unsigned int pwremu = 0;
33
Kevin Hilman617b9252009-04-14 08:04:26 -050034 serial_write_reg(p, UART_IER, 0); /* disable all interrupts */
Kevin Hilman7c6337e2007-04-30 19:37:19 +010035
Kevin Hilman617b9252009-04-14 08:04:26 -050036 /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */
37 serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
Kevin Hilman7c6337e2007-04-30 19:37:19 +010038 mdelay(10);
39
40 pwremu |= (0x3 << 13);
41 pwremu |= 0x1;
Kevin Hilman617b9252009-04-14 08:04:26 -050042 serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
43
44 if (cpu_is_davinci_dm646x())
45 serial_write_reg(p, UART_DM646X_SCR,
46 UART_DM646X_SCR_TX_WATERMARK);
47}
48
Manjunathappa, Prakashfcf71572013-06-19 14:45:42 +053049int __init davinci_serial_init(struct platform_device *serial_dev)
Kevin Hilman617b9252009-04-14 08:04:26 -050050{
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +053051 int i, ret = 0;
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +053052 struct device *dev;
53 struct plat_serial8250_port *p;
Manjunathappa, Prakash323761bb2013-06-19 14:45:42 +053054 struct clk *clk;
Kevin Hilman617b9252009-04-14 08:04:26 -050055
56 /*
57 * Make sure the serial ports are muxed on at this point.
Mark A. Greer65e866a2009-03-18 12:36:08 -050058 * You have to mux them off in device drivers later on if not needed.
Kevin Hilman617b9252009-04-14 08:04:26 -050059 */
Manjunathappa, Prakashfcf71572013-06-19 14:45:42 +053060 for (i = 0; serial_dev[i].dev.platform_data != NULL; i++) {
61 dev = &serial_dev[i].dev;
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +053062 p = dev->platform_data;
Kevin Hilman617b9252009-04-14 08:04:26 -050063
Manjunathappa, Prakashfcf71572013-06-19 14:45:42 +053064 ret = platform_device_register(&serial_dev[i]);
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +053065 if (ret)
66 continue;
67
Manjunathappa, Prakash323761bb2013-06-19 14:45:42 +053068 clk = clk_get(dev, NULL);
69 if (IS_ERR(clk)) {
70 pr_err("%s:%d: failed to get UART%d clock\n",
71 __func__, __LINE__, i);
Cyril Chemparathy9ee1ace2010-05-02 14:28:13 -040072 continue;
Manjunathappa, Prakash323761bb2013-06-19 14:45:42 +053073 }
74
75 clk_prepare_enable(clk);
76
77 p->uartclk = clk_get_rate(clk);
Cyril Chemparathy9ee1ace2010-05-02 14:28:13 -040078
79 if (!p->membase && p->mapbase) {
80 p->membase = ioremap(p->mapbase, SZ_4K);
81
82 if (p->membase)
83 p->flags &= ~UPF_IOREMAP;
84 else
85 pr_err("uart regs ioremap failed\n");
86 }
87
Cyril Chemparathye2800002010-05-02 14:28:14 -040088 if (p->membase && p->type != PORT_AR7)
Cyril Chemparathy9ee1ace2010-05-02 14:28:13 -040089 davinci_serial_reset(p);
Kevin Hilman617b9252009-04-14 08:04:26 -050090 }
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +053091 return ret;
Kevin Hilman7c6337e2007-04-30 19:37:19 +010092}