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Thomas Gleixner1a59d1b82019-05-27 08:55:05 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002#ifndef __SOUND_PHASE_H
3#define __SOUND_PHASE_H
4
5/*
6 * ALSA driver for ICEnsemble ICE1712 (Envy24)
7 *
8 * Lowlevel functions for Terratec PHASE 22
9 *
10 * Copyright (c) 2005 Misha Zhilin <misha@epiphan.com>
Vedran Mileticcc67b7f2008-09-07 12:00:02 +020011 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070012
Vedran Mileticcc67b7f2008-09-07 12:00:02 +020013#define PHASE_DEVICE_DESC "{Terratec,Phase 22},"\
14 "{Terratec,Phase 28},"\
15 "{Terrasoniq,TS22},"
Linus Torvalds1da177e2005-04-16 15:20:36 -070016
17#define VT1724_SUBDEVICE_PHASE22 0x3b155011
Simone Zinanniaed058e2005-04-11 14:08:40 +020018#define VT1724_SUBDEVICE_PHASE28 0x3b154911
Misha Zhilin740dc9c2008-08-01 12:45:14 +020019#define VT1724_SUBDEVICE_TS22 0x3b157b11
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
21/* entry point */
Takashi Iwai1b60f6b2007-03-13 22:13:47 +010022extern struct snd_ice1712_card_info snd_vt1724_phase_cards[];
Linus Torvalds1da177e2005-04-16 15:20:36 -070023
Simone Zinanniaed058e2005-04-11 14:08:40 +020024/* PHASE28 GPIO bits */
25#define PHASE28_SPI_MISO (1 << 21)
26#define PHASE28_WM_RESET (1 << 20)
27#define PHASE28_SPI_CLK (1 << 19)
28#define PHASE28_SPI_MOSI (1 << 18)
29#define PHASE28_WM_RW (1 << 17)
30#define PHASE28_AC97_RESET (1 << 16)
31#define PHASE28_DIGITAL_SEL1 (1 << 15)
32#define PHASE28_HP_SEL (1 << 14)
33#define PHASE28_WM_CS (1 << 12)
34#define PHASE28_AC97_COMMIT (1 << 11)
35#define PHASE28_AC97_ADDR (1 << 10)
36#define PHASE28_AC97_DATA_LOW (1 << 9)
37#define PHASE28_AC97_DATA_HIGH (1 << 8)
38#define PHASE28_AC97_DATA_MASK 0xFF
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#endif /* __SOUND_PHASE */