Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1 | /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module |
| 2 | * |
| 3 | * This driver supports the memory controllers found on the Intel |
| 4 | * processor family Sandy Bridge. |
| 5 | * |
| 6 | * This file may be distributed under the terms of the |
| 7 | * GNU General Public License version 2 only. |
| 8 | * |
| 9 | * Copyright (c) 2011 by: |
Mauro Carvalho Chehab | 37e59f8 | 2014-02-07 08:03:07 -0200 | [diff] [blame] | 10 | * Mauro Carvalho Chehab |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/pci.h> |
| 16 | #include <linux/pci_ids.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/edac.h> |
| 20 | #include <linux/mmzone.h> |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 21 | #include <linux/smp.h> |
| 22 | #include <linux/bitmap.h> |
Mauro Carvalho Chehab | 5b889e3 | 2011-11-07 18:26:53 -0300 | [diff] [blame] | 23 | #include <linux/math64.h> |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 24 | #include <asm/processor.h> |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 25 | #include <asm/mce.h> |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 26 | |
| 27 | #include "edac_core.h" |
| 28 | |
| 29 | /* Static vars */ |
| 30 | static LIST_HEAD(sbridge_edac_list); |
| 31 | static DEFINE_MUTEX(sbridge_edac_lock); |
| 32 | static int probed; |
| 33 | |
| 34 | /* |
| 35 | * Alter this version for the module when modifications are made |
| 36 | */ |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 37 | #define SBRIDGE_REVISION " Ver: 1.1.0 " |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 38 | #define EDAC_MOD_STR "sbridge_edac" |
| 39 | |
| 40 | /* |
| 41 | * Debug macros |
| 42 | */ |
| 43 | #define sbridge_printk(level, fmt, arg...) \ |
| 44 | edac_printk(level, "sbridge", fmt, ##arg) |
| 45 | |
| 46 | #define sbridge_mc_printk(mci, level, fmt, arg...) \ |
| 47 | edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg) |
| 48 | |
| 49 | /* |
| 50 | * Get a bit field at register value <v>, from bit <lo> to bit <hi> |
| 51 | */ |
| 52 | #define GET_BITFIELD(v, lo, hi) \ |
Chen, Gong | 10ef6b0 | 2013-10-18 14:29:07 -0700 | [diff] [blame] | 53 | (((v) & GENMASK_ULL(hi, lo)) >> (lo)) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 54 | |
| 55 | /* |
| 56 | * sbridge Memory Controller Registers |
| 57 | */ |
| 58 | |
| 59 | /* |
| 60 | * FIXME: For now, let's order by device function, as it makes |
David Mackey | 15ed103 | 2012-04-17 11:30:52 -0700 | [diff] [blame] | 61 | * easier for driver's development process. This table should be |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 62 | * moved to pci_id.h when submitted upstream |
| 63 | */ |
| 64 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */ |
| 65 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */ |
| 66 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */ |
| 67 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */ |
| 68 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */ |
| 69 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */ |
| 70 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */ |
| 71 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */ |
| 72 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */ |
| 73 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */ |
| 74 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */ |
| 75 | |
| 76 | /* |
| 77 | * Currently, unused, but will be needed in the future |
| 78 | * implementations, as they hold the error counters |
| 79 | */ |
| 80 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */ |
| 81 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */ |
| 82 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */ |
| 83 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */ |
| 84 | |
| 85 | /* Devices 12 Function 6, Offsets 0x80 to 0xcc */ |
Aristeu Rozanski | 464f1d8 | 2013-10-30 13:27:00 -0300 | [diff] [blame] | 86 | static const u32 sbridge_dram_rule[] = { |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 87 | 0x80, 0x88, 0x90, 0x98, 0xa0, |
| 88 | 0xa8, 0xb0, 0xb8, 0xc0, 0xc8, |
| 89 | }; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 90 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 91 | static const u32 ibridge_dram_rule[] = { |
| 92 | 0x60, 0x68, 0x70, 0x78, 0x80, |
| 93 | 0x88, 0x90, 0x98, 0xa0, 0xa8, |
| 94 | 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, |
| 95 | 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, |
| 96 | }; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 97 | |
| 98 | #define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff) |
| 99 | #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3) |
| 100 | #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1) |
| 101 | #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0) |
| 102 | |
| 103 | static char *get_dram_attr(u32 reg) |
| 104 | { |
| 105 | switch(DRAM_ATTR(reg)) { |
| 106 | case 0: |
| 107 | return "DRAM"; |
| 108 | case 1: |
| 109 | return "MMCFG"; |
| 110 | case 2: |
| 111 | return "NXM"; |
| 112 | default: |
| 113 | return "unknown"; |
| 114 | } |
| 115 | } |
| 116 | |
Aristeu Rozanski | ef1ce51 | 2013-10-30 13:27:01 -0300 | [diff] [blame] | 117 | static const u32 sbridge_interleave_list[] = { |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 118 | 0x84, 0x8c, 0x94, 0x9c, 0xa4, |
| 119 | 0xac, 0xb4, 0xbc, 0xc4, 0xcc, |
| 120 | }; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 121 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 122 | static const u32 ibridge_interleave_list[] = { |
| 123 | 0x64, 0x6c, 0x74, 0x7c, 0x84, |
| 124 | 0x8c, 0x94, 0x9c, 0xa4, 0xac, |
| 125 | 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, |
| 126 | 0xdc, 0xe4, 0xec, 0xf4, 0xfc, |
| 127 | }; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 128 | |
Aristeu Rozanski | cc31199 | 2013-10-30 13:27:02 -0300 | [diff] [blame] | 129 | struct interleave_pkg { |
| 130 | unsigned char start; |
| 131 | unsigned char end; |
| 132 | }; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 133 | |
Aristeu Rozanski | cc31199 | 2013-10-30 13:27:02 -0300 | [diff] [blame] | 134 | static const struct interleave_pkg sbridge_interleave_pkg[] = { |
| 135 | { 0, 2 }, |
| 136 | { 3, 5 }, |
| 137 | { 8, 10 }, |
| 138 | { 11, 13 }, |
| 139 | { 16, 18 }, |
| 140 | { 19, 21 }, |
| 141 | { 24, 26 }, |
| 142 | { 27, 29 }, |
| 143 | }; |
| 144 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 145 | static const struct interleave_pkg ibridge_interleave_pkg[] = { |
| 146 | { 0, 3 }, |
| 147 | { 4, 7 }, |
| 148 | { 8, 11 }, |
| 149 | { 12, 15 }, |
| 150 | { 16, 19 }, |
| 151 | { 20, 23 }, |
| 152 | { 24, 27 }, |
| 153 | { 28, 31 }, |
| 154 | }; |
| 155 | |
Aristeu Rozanski | cc31199 | 2013-10-30 13:27:02 -0300 | [diff] [blame] | 156 | static inline int sad_pkg(const struct interleave_pkg *table, u32 reg, |
| 157 | int interleave) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 158 | { |
Aristeu Rozanski | cc31199 | 2013-10-30 13:27:02 -0300 | [diff] [blame] | 159 | return GET_BITFIELD(reg, table[interleave].start, |
| 160 | table[interleave].end); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 161 | } |
| 162 | |
| 163 | /* Devices 12 Function 7 */ |
| 164 | |
| 165 | #define TOLM 0x80 |
| 166 | #define TOHM 0x84 |
| 167 | |
| 168 | #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff) |
| 169 | #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff) |
| 170 | |
| 171 | /* Device 13 Function 6 */ |
| 172 | |
| 173 | #define SAD_TARGET 0xf0 |
| 174 | |
| 175 | #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11) |
| 176 | |
| 177 | #define SAD_CONTROL 0xf4 |
| 178 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 179 | /* Device 14 function 0 */ |
| 180 | |
| 181 | static const u32 tad_dram_rule[] = { |
| 182 | 0x40, 0x44, 0x48, 0x4c, |
| 183 | 0x50, 0x54, 0x58, 0x5c, |
| 184 | 0x60, 0x64, 0x68, 0x6c, |
| 185 | }; |
| 186 | #define MAX_TAD ARRAY_SIZE(tad_dram_rule) |
| 187 | |
| 188 | #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff) |
| 189 | #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11) |
| 190 | #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9) |
| 191 | #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7) |
| 192 | #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5) |
| 193 | #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3) |
| 194 | #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1) |
| 195 | |
| 196 | /* Device 15, function 0 */ |
| 197 | |
| 198 | #define MCMTR 0x7c |
| 199 | |
| 200 | #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2) |
| 201 | #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1) |
| 202 | #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0) |
| 203 | |
| 204 | /* Device 15, function 1 */ |
| 205 | |
| 206 | #define RASENABLES 0xac |
| 207 | #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0) |
| 208 | |
| 209 | /* Device 15, functions 2-5 */ |
| 210 | |
| 211 | static const int mtr_regs[] = { |
| 212 | 0x80, 0x84, 0x88, |
| 213 | }; |
| 214 | |
| 215 | #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19) |
| 216 | #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14) |
| 217 | #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13) |
| 218 | #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4) |
| 219 | #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1) |
| 220 | |
| 221 | static const u32 tad_ch_nilv_offset[] = { |
| 222 | 0x90, 0x94, 0x98, 0x9c, |
| 223 | 0xa0, 0xa4, 0xa8, 0xac, |
| 224 | 0xb0, 0xb4, 0xb8, 0xbc, |
| 225 | }; |
| 226 | #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29) |
| 227 | #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26) |
| 228 | |
| 229 | static const u32 rir_way_limit[] = { |
| 230 | 0x108, 0x10c, 0x110, 0x114, 0x118, |
| 231 | }; |
| 232 | #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit) |
| 233 | |
| 234 | #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31) |
| 235 | #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 236 | |
| 237 | #define MAX_RIR_WAY 8 |
| 238 | |
| 239 | static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = { |
| 240 | { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c }, |
| 241 | { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c }, |
| 242 | { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c }, |
| 243 | { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c }, |
| 244 | { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc }, |
| 245 | }; |
| 246 | |
| 247 | #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19) |
| 248 | #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14) |
| 249 | |
| 250 | /* Device 16, functions 2-7 */ |
| 251 | |
| 252 | /* |
| 253 | * FIXME: Implement the error count reads directly |
| 254 | */ |
| 255 | |
| 256 | static const u32 correrrcnt[] = { |
| 257 | 0x104, 0x108, 0x10c, 0x110, |
| 258 | }; |
| 259 | |
| 260 | #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31) |
| 261 | #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30) |
| 262 | #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15) |
| 263 | #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14) |
| 264 | |
| 265 | static const u32 correrrthrsld[] = { |
| 266 | 0x11c, 0x120, 0x124, 0x128, |
| 267 | }; |
| 268 | |
| 269 | #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30) |
| 270 | #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14) |
| 271 | |
| 272 | |
| 273 | /* Device 17, function 0 */ |
| 274 | |
Aristeu Rozanski | ef1e8d0 | 2013-10-30 13:26:56 -0300 | [diff] [blame] | 275 | #define SB_RANK_CFG_A 0x0328 |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 276 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 277 | #define IB_RANK_CFG_A 0x0320 |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 278 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 279 | /* |
| 280 | * sbridge structs |
| 281 | */ |
| 282 | |
| 283 | #define NUM_CHANNELS 4 |
| 284 | #define MAX_DIMMS 3 /* Max DIMMS per channel */ |
| 285 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 286 | enum type { |
| 287 | SANDY_BRIDGE, |
| 288 | IVY_BRIDGE, |
| 289 | }; |
| 290 | |
Aristeu Rozanski | fb79a50 | 2013-10-30 13:26:57 -0300 | [diff] [blame] | 291 | struct sbridge_pvt; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 292 | struct sbridge_info { |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 293 | enum type type; |
Aristeu Rozanski | 464f1d8 | 2013-10-30 13:27:00 -0300 | [diff] [blame] | 294 | u32 mcmtr; |
| 295 | u32 rankcfgr; |
| 296 | u64 (*get_tolm)(struct sbridge_pvt *pvt); |
| 297 | u64 (*get_tohm)(struct sbridge_pvt *pvt); |
Aristeu Rozanski | b976bcf | 2014-06-02 15:15:24 -0300 | [diff] [blame] | 298 | u64 (*rir_limit)(u32 reg); |
Aristeu Rozanski | 464f1d8 | 2013-10-30 13:27:00 -0300 | [diff] [blame] | 299 | const u32 *dram_rule; |
Aristeu Rozanski | ef1ce51 | 2013-10-30 13:27:01 -0300 | [diff] [blame] | 300 | const u32 *interleave_list; |
Aristeu Rozanski | cc31199 | 2013-10-30 13:27:02 -0300 | [diff] [blame] | 301 | const struct interleave_pkg *interleave_pkg; |
Aristeu Rozanski | 464f1d8 | 2013-10-30 13:27:00 -0300 | [diff] [blame] | 302 | u8 max_sad; |
Aristeu Rozanski | ef1ce51 | 2013-10-30 13:27:01 -0300 | [diff] [blame] | 303 | u8 max_interleave; |
Aristeu Rozanski | f14d689 | 2014-06-02 15:15:23 -0300 | [diff] [blame] | 304 | u8 (*get_node_id)(struct sbridge_pvt *pvt); |
Aristeu Rozanski | 9e37544 | 2014-06-02 15:15:22 -0300 | [diff] [blame] | 305 | enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 306 | }; |
| 307 | |
| 308 | struct sbridge_channel { |
| 309 | u32 ranks; |
| 310 | u32 dimms; |
| 311 | }; |
| 312 | |
| 313 | struct pci_id_descr { |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 314 | int dev_id; |
| 315 | int optional; |
| 316 | }; |
| 317 | |
| 318 | struct pci_id_table { |
| 319 | const struct pci_id_descr *descr; |
| 320 | int n_devs; |
| 321 | }; |
| 322 | |
| 323 | struct sbridge_dev { |
| 324 | struct list_head list; |
| 325 | u8 bus, mc; |
| 326 | u8 node_id, source_id; |
| 327 | struct pci_dev **pdev; |
| 328 | int n_devs; |
| 329 | struct mem_ctl_info *mci; |
| 330 | }; |
| 331 | |
| 332 | struct sbridge_pvt { |
| 333 | struct pci_dev *pci_ta, *pci_ddrio, *pci_ras; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 334 | struct pci_dev *pci_sad0, *pci_sad1; |
| 335 | struct pci_dev *pci_ha0, *pci_ha1; |
| 336 | struct pci_dev *pci_br0, *pci_br1; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 337 | struct pci_dev *pci_tad[NUM_CHANNELS]; |
| 338 | |
| 339 | struct sbridge_dev *sbridge_dev; |
| 340 | |
| 341 | struct sbridge_info info; |
| 342 | struct sbridge_channel channel[NUM_CHANNELS]; |
| 343 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 344 | /* Memory type detection */ |
| 345 | bool is_mirrored, is_lockstep, is_close_pg; |
| 346 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 347 | /* Fifo double buffers */ |
| 348 | struct mce mce_entry[MCE_LOG_LEN]; |
| 349 | struct mce mce_outentry[MCE_LOG_LEN]; |
| 350 | |
| 351 | /* Fifo in/out counters */ |
| 352 | unsigned mce_in, mce_out; |
| 353 | |
| 354 | /* Count indicator to show errors not got */ |
| 355 | unsigned mce_overrun; |
| 356 | |
| 357 | /* Memory description */ |
| 358 | u64 tolm, tohm; |
| 359 | }; |
| 360 | |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 361 | #define PCI_DESCR(device_id, opt) \ |
| 362 | .dev_id = (device_id), \ |
Luck, Tony | de4772c | 2013-03-28 09:59:15 -0700 | [diff] [blame] | 363 | .optional = opt |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 364 | |
| 365 | static const struct pci_id_descr pci_dev_descr_sbridge[] = { |
| 366 | /* Processor Home Agent */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 367 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) }, |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 368 | |
| 369 | /* Memory controller */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 370 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) }, |
| 371 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) }, |
| 372 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) }, |
| 373 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) }, |
| 374 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) }, |
| 375 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) }, |
| 376 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) }, |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 377 | |
| 378 | /* System Address Decoder */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 379 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) }, |
| 380 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) }, |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 381 | |
| 382 | /* Broadcast Registers */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 383 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) }, |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 384 | }; |
| 385 | |
| 386 | #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) } |
| 387 | static const struct pci_id_table pci_dev_descr_sbridge_table[] = { |
| 388 | PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge), |
| 389 | {0,} /* 0 terminated list. */ |
| 390 | }; |
| 391 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 392 | /* This changes depending if 1HA or 2HA: |
| 393 | * 1HA: |
| 394 | * 0x0eb8 (17.0) is DDRIO0 |
| 395 | * 2HA: |
| 396 | * 0x0ebc (17.4) is DDRIO0 |
| 397 | */ |
| 398 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8 |
| 399 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc |
| 400 | |
| 401 | /* pci ids */ |
| 402 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0 |
| 403 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8 |
| 404 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71 |
| 405 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa |
| 406 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab |
| 407 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac |
| 408 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead |
| 409 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8 |
| 410 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9 |
| 411 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca |
| 412 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60 |
| 413 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68 |
| 414 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79 |
| 415 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a |
| 416 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b |
| 417 | |
| 418 | static const struct pci_id_descr pci_dev_descr_ibridge[] = { |
| 419 | /* Processor Home Agent */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 420 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0) }, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 421 | |
| 422 | /* Memory controller */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 423 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0) }, |
| 424 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0) }, |
| 425 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0) }, |
| 426 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0) }, |
| 427 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0) }, |
| 428 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0) }, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 429 | |
| 430 | /* System Address Decoder */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 431 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0) }, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 432 | |
| 433 | /* Broadcast Registers */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 434 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1) }, |
| 435 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0) }, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 436 | |
| 437 | /* Optional, mode 2HA */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 438 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1) }, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 439 | #if 0 |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 440 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1) }, |
| 441 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) }, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 442 | #endif |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 443 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1) }, |
| 444 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1) }, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 445 | |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 446 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1) }, |
| 447 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1) }, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 448 | }; |
| 449 | |
| 450 | static const struct pci_id_table pci_dev_descr_ibridge_table[] = { |
| 451 | PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge), |
| 452 | {0,} /* 0 terminated list. */ |
| 453 | }; |
| 454 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 455 | /* |
| 456 | * pci_device_id table for which devices we are looking for |
| 457 | */ |
Jingoo Han | ba935f4 | 2013-12-06 10:23:08 +0100 | [diff] [blame] | 458 | static const struct pci_device_id sbridge_pci_tbl[] = { |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 459 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)}, |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 460 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)}, |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 461 | {0,} /* 0 terminated list. */ |
| 462 | }; |
| 463 | |
| 464 | |
| 465 | /**************************************************************************** |
David Mackey | 15ed103 | 2012-04-17 11:30:52 -0700 | [diff] [blame] | 466 | Ancillary status routines |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 467 | ****************************************************************************/ |
| 468 | |
| 469 | static inline int numrank(u32 mtr) |
| 470 | { |
| 471 | int ranks = (1 << RANK_CNT_BITS(mtr)); |
| 472 | |
| 473 | if (ranks > 4) { |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 474 | edac_dbg(0, "Invalid number of ranks: %d (max = 4) raw value = %x (%04x)\n", |
| 475 | ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 476 | return -EINVAL; |
| 477 | } |
| 478 | |
| 479 | return ranks; |
| 480 | } |
| 481 | |
| 482 | static inline int numrow(u32 mtr) |
| 483 | { |
| 484 | int rows = (RANK_WIDTH_BITS(mtr) + 12); |
| 485 | |
| 486 | if (rows < 13 || rows > 18) { |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 487 | edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n", |
| 488 | rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 489 | return -EINVAL; |
| 490 | } |
| 491 | |
| 492 | return 1 << rows; |
| 493 | } |
| 494 | |
| 495 | static inline int numcol(u32 mtr) |
| 496 | { |
| 497 | int cols = (COL_WIDTH_BITS(mtr) + 10); |
| 498 | |
| 499 | if (cols > 12) { |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 500 | edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n", |
| 501 | cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 502 | return -EINVAL; |
| 503 | } |
| 504 | |
| 505 | return 1 << cols; |
| 506 | } |
| 507 | |
| 508 | static struct sbridge_dev *get_sbridge_dev(u8 bus) |
| 509 | { |
| 510 | struct sbridge_dev *sbridge_dev; |
| 511 | |
| 512 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { |
| 513 | if (sbridge_dev->bus == bus) |
| 514 | return sbridge_dev; |
| 515 | } |
| 516 | |
| 517 | return NULL; |
| 518 | } |
| 519 | |
| 520 | static struct sbridge_dev *alloc_sbridge_dev(u8 bus, |
| 521 | const struct pci_id_table *table) |
| 522 | { |
| 523 | struct sbridge_dev *sbridge_dev; |
| 524 | |
| 525 | sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL); |
| 526 | if (!sbridge_dev) |
| 527 | return NULL; |
| 528 | |
| 529 | sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs, |
| 530 | GFP_KERNEL); |
| 531 | if (!sbridge_dev->pdev) { |
| 532 | kfree(sbridge_dev); |
| 533 | return NULL; |
| 534 | } |
| 535 | |
| 536 | sbridge_dev->bus = bus; |
| 537 | sbridge_dev->n_devs = table->n_devs; |
| 538 | list_add_tail(&sbridge_dev->list, &sbridge_edac_list); |
| 539 | |
| 540 | return sbridge_dev; |
| 541 | } |
| 542 | |
| 543 | static void free_sbridge_dev(struct sbridge_dev *sbridge_dev) |
| 544 | { |
| 545 | list_del(&sbridge_dev->list); |
| 546 | kfree(sbridge_dev->pdev); |
| 547 | kfree(sbridge_dev); |
| 548 | } |
| 549 | |
Aristeu Rozanski | fb79a50 | 2013-10-30 13:26:57 -0300 | [diff] [blame] | 550 | static u64 sbridge_get_tolm(struct sbridge_pvt *pvt) |
| 551 | { |
| 552 | u32 reg; |
| 553 | |
| 554 | /* Address range is 32:28 */ |
| 555 | pci_read_config_dword(pvt->pci_sad1, TOLM, ®); |
| 556 | return GET_TOLM(reg); |
| 557 | } |
| 558 | |
Aristeu Rozanski | 8fd6a43 | 2013-10-30 13:26:59 -0300 | [diff] [blame] | 559 | static u64 sbridge_get_tohm(struct sbridge_pvt *pvt) |
| 560 | { |
| 561 | u32 reg; |
| 562 | |
| 563 | pci_read_config_dword(pvt->pci_sad1, TOHM, ®); |
| 564 | return GET_TOHM(reg); |
| 565 | } |
| 566 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 567 | static u64 ibridge_get_tolm(struct sbridge_pvt *pvt) |
| 568 | { |
| 569 | u32 reg; |
| 570 | |
| 571 | pci_read_config_dword(pvt->pci_br1, TOLM, ®); |
| 572 | |
| 573 | return GET_TOLM(reg); |
| 574 | } |
| 575 | |
| 576 | static u64 ibridge_get_tohm(struct sbridge_pvt *pvt) |
| 577 | { |
| 578 | u32 reg; |
| 579 | |
| 580 | pci_read_config_dword(pvt->pci_br1, TOHM, ®); |
| 581 | |
| 582 | return GET_TOHM(reg); |
| 583 | } |
| 584 | |
Aristeu Rozanski | b976bcf | 2014-06-02 15:15:24 -0300 | [diff] [blame] | 585 | static u64 rir_limit(u32 reg) |
| 586 | { |
| 587 | return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff; |
| 588 | } |
| 589 | |
Aristeu Rozanski | 9e37544 | 2014-06-02 15:15:22 -0300 | [diff] [blame] | 590 | static enum mem_type get_memory_type(struct sbridge_pvt *pvt) |
| 591 | { |
| 592 | u32 reg; |
| 593 | enum mem_type mtype; |
| 594 | |
| 595 | if (pvt->pci_ddrio) { |
| 596 | pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, |
| 597 | ®); |
| 598 | if (GET_BITFIELD(reg, 11, 11)) |
| 599 | /* FIXME: Can also be LRDIMM */ |
| 600 | mtype = MEM_RDDR3; |
| 601 | else |
| 602 | mtype = MEM_DDR3; |
| 603 | } else |
| 604 | mtype = MEM_UNKNOWN; |
| 605 | |
| 606 | return mtype; |
| 607 | } |
| 608 | |
Aristeu Rozanski | f14d689 | 2014-06-02 15:15:23 -0300 | [diff] [blame] | 609 | static u8 get_node_id(struct sbridge_pvt *pvt) |
| 610 | { |
| 611 | u32 reg; |
| 612 | pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); |
| 613 | return GET_BITFIELD(reg, 0, 2); |
| 614 | } |
| 615 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 616 | static inline u8 sad_pkg_socket(u8 pkg) |
| 617 | { |
| 618 | /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */ |
Aristeu Rozanski | 2ff3a30 | 2014-06-02 15:15:27 -0300 | [diff] [blame^] | 619 | return ((pkg >> 3) << 2) | (pkg & 0x3); |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 620 | } |
| 621 | |
| 622 | static inline u8 sad_pkg_ha(u8 pkg) |
| 623 | { |
| 624 | return (pkg >> 2) & 0x1; |
| 625 | } |
| 626 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 627 | /**************************************************************************** |
| 628 | Memory check routines |
| 629 | ****************************************************************************/ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 630 | static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 631 | { |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 632 | struct pci_dev *pdev = NULL; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 633 | |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 634 | do { |
| 635 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev); |
| 636 | if (pdev && pdev->bus->number == bus) |
| 637 | break; |
| 638 | } while (pdev); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 639 | |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 640 | return pdev; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 641 | } |
| 642 | |
| 643 | /** |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 644 | * check_if_ecc_is_active() - Checks if ECC is active |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 645 | * bus: Device bus |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 646 | */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 647 | static int check_if_ecc_is_active(const u8 bus, enum type type) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 648 | { |
| 649 | struct pci_dev *pdev = NULL; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 650 | u32 mcmtr, id; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 651 | |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 652 | if (type == IVY_BRIDGE) |
| 653 | id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA; |
| 654 | else |
| 655 | id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA; |
| 656 | |
| 657 | pdev = get_pdev_same_bus(bus, id); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 658 | if (!pdev) { |
| 659 | sbridge_printk(KERN_ERR, "Couldn't find PCI device " |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 660 | "%04x:%04x! on bus %02d\n", |
| 661 | PCI_VENDOR_ID_INTEL, id, bus); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 662 | return -ENODEV; |
| 663 | } |
| 664 | |
| 665 | pci_read_config_dword(pdev, MCMTR, &mcmtr); |
| 666 | if (!IS_ECC_ENABLED(mcmtr)) { |
| 667 | sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n"); |
| 668 | return -ENODEV; |
| 669 | } |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 670 | return 0; |
| 671 | } |
| 672 | |
Mauro Carvalho Chehab | 084a4fc | 2012-01-27 18:38:08 -0300 | [diff] [blame] | 673 | static int get_dimm_config(struct mem_ctl_info *mci) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 674 | { |
| 675 | struct sbridge_pvt *pvt = mci->pvt_info; |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 676 | struct dimm_info *dimm; |
Mauro Carvalho Chehab | deb09dd | 2012-09-20 12:09:30 -0300 | [diff] [blame] | 677 | unsigned i, j, banks, ranks, rows, cols, npages; |
| 678 | u64 size; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 679 | u32 reg; |
| 680 | enum edac_type mode; |
Mark A. Grondona | c6e13b5 | 2011-10-18 11:02:58 -0200 | [diff] [blame] | 681 | enum mem_type mtype; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 682 | |
Aristeu Rozanski | 5f8a1b8 | 2013-10-30 13:26:58 -0300 | [diff] [blame] | 683 | pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 684 | pvt->sbridge_dev->source_id = SOURCE_ID(reg); |
| 685 | |
Aristeu Rozanski | f14d689 | 2014-06-02 15:15:23 -0300 | [diff] [blame] | 686 | pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt); |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 687 | edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n", |
| 688 | pvt->sbridge_dev->mc, |
| 689 | pvt->sbridge_dev->node_id, |
| 690 | pvt->sbridge_dev->source_id); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 691 | |
| 692 | pci_read_config_dword(pvt->pci_ras, RASENABLES, ®); |
| 693 | if (IS_MIRROR_ENABLED(reg)) { |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 694 | edac_dbg(0, "Memory mirror is enabled\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 695 | pvt->is_mirrored = true; |
| 696 | } else { |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 697 | edac_dbg(0, "Memory mirror is disabled\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 698 | pvt->is_mirrored = false; |
| 699 | } |
| 700 | |
| 701 | pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr); |
| 702 | if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 703 | edac_dbg(0, "Lockstep is enabled\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 704 | mode = EDAC_S8ECD8ED; |
| 705 | pvt->is_lockstep = true; |
| 706 | } else { |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 707 | edac_dbg(0, "Lockstep is disabled\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 708 | mode = EDAC_S4ECD4ED; |
| 709 | pvt->is_lockstep = false; |
| 710 | } |
| 711 | if (IS_CLOSE_PG(pvt->info.mcmtr)) { |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 712 | edac_dbg(0, "address map is on closed page mode\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 713 | pvt->is_close_pg = true; |
| 714 | } else { |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 715 | edac_dbg(0, "address map is on open page mode\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 716 | pvt->is_close_pg = false; |
| 717 | } |
| 718 | |
Aristeu Rozanski | 9e37544 | 2014-06-02 15:15:22 -0300 | [diff] [blame] | 719 | mtype = pvt->info.get_memory_type(pvt); |
| 720 | if (mtype == MEM_RDDR3) |
| 721 | edac_dbg(0, "Memory is registered\n"); |
| 722 | else if (mtype == MEM_UNKNOWN) |
Luck, Tony | de4772c | 2013-03-28 09:59:15 -0700 | [diff] [blame] | 723 | edac_dbg(0, "Cannot determine memory type\n"); |
Aristeu Rozanski | 9e37544 | 2014-06-02 15:15:22 -0300 | [diff] [blame] | 724 | else |
| 725 | edac_dbg(0, "Memory is unregistered\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 726 | |
| 727 | /* On all supported DDR3 DIMM types, there are 8 banks available */ |
| 728 | banks = 8; |
| 729 | |
| 730 | for (i = 0; i < NUM_CHANNELS; i++) { |
| 731 | u32 mtr; |
| 732 | |
| 733 | for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) { |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 734 | dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, |
| 735 | i, j, 0); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 736 | pci_read_config_dword(pvt->pci_tad[i], |
| 737 | mtr_regs[j], &mtr); |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 738 | edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 739 | if (IS_DIMM_PRESENT(mtr)) { |
| 740 | pvt->channel[i].dimms++; |
| 741 | |
| 742 | ranks = numrank(mtr); |
| 743 | rows = numrow(mtr); |
| 744 | cols = numcol(mtr); |
| 745 | |
| 746 | /* DDR3 has 8 I/O banks */ |
Mauro Carvalho Chehab | deb09dd | 2012-09-20 12:09:30 -0300 | [diff] [blame] | 747 | size = ((u64)rows * cols * banks * ranks) >> (20 - 3); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 748 | npages = MiB_TO_PAGES(size); |
| 749 | |
Mauro Carvalho Chehab | deb09dd | 2012-09-20 12:09:30 -0300 | [diff] [blame] | 750 | edac_dbg(0, "mc#%d: channel %d, dimm %d, %Ld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 751 | pvt->sbridge_dev->mc, i, j, |
| 752 | size, npages, |
| 753 | banks, ranks, rows, cols); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 754 | |
Mauro Carvalho Chehab | a895bf8 | 2012-01-28 09:09:38 -0300 | [diff] [blame] | 755 | dimm->nr_pages = npages; |
Mauro Carvalho Chehab | 084a4fc | 2012-01-27 18:38:08 -0300 | [diff] [blame] | 756 | dimm->grain = 32; |
| 757 | dimm->dtype = (banks == 8) ? DEV_X8 : DEV_X4; |
| 758 | dimm->mtype = mtype; |
| 759 | dimm->edac_mode = mode; |
| 760 | snprintf(dimm->label, sizeof(dimm->label), |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 761 | "CPU_SrcID#%u_Channel#%u_DIMM#%u", |
| 762 | pvt->sbridge_dev->source_id, i, j); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 763 | } |
| 764 | } |
| 765 | } |
| 766 | |
| 767 | return 0; |
| 768 | } |
| 769 | |
| 770 | static void get_memory_layout(const struct mem_ctl_info *mci) |
| 771 | { |
| 772 | struct sbridge_pvt *pvt = mci->pvt_info; |
| 773 | int i, j, k, n_sads, n_tads, sad_interl; |
| 774 | u32 reg; |
| 775 | u64 limit, prv = 0; |
| 776 | u64 tmp_mb; |
Mauro Carvalho Chehab | 5b889e3 | 2011-11-07 18:26:53 -0300 | [diff] [blame] | 777 | u32 mb, kb; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 778 | u32 rir_way; |
| 779 | |
| 780 | /* |
| 781 | * Step 1) Get TOLM/TOHM ranges |
| 782 | */ |
| 783 | |
Aristeu Rozanski | fb79a50 | 2013-10-30 13:26:57 -0300 | [diff] [blame] | 784 | pvt->tolm = pvt->info.get_tolm(pvt); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 785 | tmp_mb = (1 + pvt->tolm) >> 20; |
| 786 | |
Mauro Carvalho Chehab | 5b889e3 | 2011-11-07 18:26:53 -0300 | [diff] [blame] | 787 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 788 | edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tolm); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 789 | |
| 790 | /* Address range is already 45:25 */ |
Aristeu Rozanski | 8fd6a43 | 2013-10-30 13:26:59 -0300 | [diff] [blame] | 791 | pvt->tohm = pvt->info.get_tohm(pvt); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 792 | tmp_mb = (1 + pvt->tohm) >> 20; |
| 793 | |
Mauro Carvalho Chehab | 5b889e3 | 2011-11-07 18:26:53 -0300 | [diff] [blame] | 794 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
Mauro Carvalho Chehab | da14d93 | 2012-10-25 09:07:21 -0200 | [diff] [blame] | 795 | edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tohm); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 796 | |
| 797 | /* |
| 798 | * Step 2) Get SAD range and SAD Interleave list |
| 799 | * TAD registers contain the interleave wayness. However, it |
| 800 | * seems simpler to just discover it indirectly, with the |
| 801 | * algorithm bellow. |
| 802 | */ |
| 803 | prv = 0; |
Aristeu Rozanski | 464f1d8 | 2013-10-30 13:27:00 -0300 | [diff] [blame] | 804 | for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 805 | /* SAD_LIMIT Address range is 45:26 */ |
Aristeu Rozanski | 464f1d8 | 2013-10-30 13:27:00 -0300 | [diff] [blame] | 806 | pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 807 | ®); |
| 808 | limit = SAD_LIMIT(reg); |
| 809 | |
| 810 | if (!DRAM_RULE_ENABLE(reg)) |
| 811 | continue; |
| 812 | |
| 813 | if (limit <= prv) |
| 814 | break; |
| 815 | |
| 816 | tmp_mb = (limit + 1) >> 20; |
Mauro Carvalho Chehab | 5b889e3 | 2011-11-07 18:26:53 -0300 | [diff] [blame] | 817 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 818 | edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n", |
| 819 | n_sads, |
| 820 | get_dram_attr(reg), |
| 821 | mb, kb, |
| 822 | ((u64)tmp_mb) << 20L, |
| 823 | INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]", |
| 824 | reg); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 825 | prv = limit; |
| 826 | |
Aristeu Rozanski | ef1ce51 | 2013-10-30 13:27:01 -0300 | [diff] [blame] | 827 | pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 828 | ®); |
Aristeu Rozanski | cc31199 | 2013-10-30 13:27:02 -0300 | [diff] [blame] | 829 | sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 830 | for (j = 0; j < 8; j++) { |
Aristeu Rozanski | cc31199 | 2013-10-30 13:27:02 -0300 | [diff] [blame] | 831 | u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); |
| 832 | if (j > 0 && sad_interl == pkg) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 833 | break; |
| 834 | |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 835 | edac_dbg(0, "SAD#%d, interleave #%d: %d\n", |
Aristeu Rozanski | cc31199 | 2013-10-30 13:27:02 -0300 | [diff] [blame] | 836 | n_sads, j, pkg); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 837 | } |
| 838 | } |
| 839 | |
| 840 | /* |
| 841 | * Step 3) Get TAD range |
| 842 | */ |
| 843 | prv = 0; |
| 844 | for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { |
| 845 | pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads], |
| 846 | ®); |
| 847 | limit = TAD_LIMIT(reg); |
| 848 | if (limit <= prv) |
| 849 | break; |
| 850 | tmp_mb = (limit + 1) >> 20; |
| 851 | |
Mauro Carvalho Chehab | 5b889e3 | 2011-11-07 18:26:53 -0300 | [diff] [blame] | 852 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 853 | edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n", |
| 854 | n_tads, mb, kb, |
| 855 | ((u64)tmp_mb) << 20L, |
| 856 | (u32)TAD_SOCK(reg), |
| 857 | (u32)TAD_CH(reg), |
| 858 | (u32)TAD_TGT0(reg), |
| 859 | (u32)TAD_TGT1(reg), |
| 860 | (u32)TAD_TGT2(reg), |
| 861 | (u32)TAD_TGT3(reg), |
| 862 | reg); |
Hui Wang | 7fae0db | 2012-02-06 04:11:01 -0300 | [diff] [blame] | 863 | prv = limit; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 864 | } |
| 865 | |
| 866 | /* |
| 867 | * Step 4) Get TAD offsets, per each channel |
| 868 | */ |
| 869 | for (i = 0; i < NUM_CHANNELS; i++) { |
| 870 | if (!pvt->channel[i].dimms) |
| 871 | continue; |
| 872 | for (j = 0; j < n_tads; j++) { |
| 873 | pci_read_config_dword(pvt->pci_tad[i], |
| 874 | tad_ch_nilv_offset[j], |
| 875 | ®); |
| 876 | tmp_mb = TAD_OFFSET(reg) >> 20; |
Mauro Carvalho Chehab | 5b889e3 | 2011-11-07 18:26:53 -0300 | [diff] [blame] | 877 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 878 | edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n", |
| 879 | i, j, |
| 880 | mb, kb, |
| 881 | ((u64)tmp_mb) << 20L, |
| 882 | reg); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 883 | } |
| 884 | } |
| 885 | |
| 886 | /* |
| 887 | * Step 6) Get RIR Wayness/Limit, per each channel |
| 888 | */ |
| 889 | for (i = 0; i < NUM_CHANNELS; i++) { |
| 890 | if (!pvt->channel[i].dimms) |
| 891 | continue; |
| 892 | for (j = 0; j < MAX_RIR_RANGES; j++) { |
| 893 | pci_read_config_dword(pvt->pci_tad[i], |
| 894 | rir_way_limit[j], |
| 895 | ®); |
| 896 | |
| 897 | if (!IS_RIR_VALID(reg)) |
| 898 | continue; |
| 899 | |
Aristeu Rozanski | b976bcf | 2014-06-02 15:15:24 -0300 | [diff] [blame] | 900 | tmp_mb = pvt->info.rir_limit(reg) >> 20; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 901 | rir_way = 1 << RIR_WAY(reg); |
Mauro Carvalho Chehab | 5b889e3 | 2011-11-07 18:26:53 -0300 | [diff] [blame] | 902 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 903 | edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n", |
| 904 | i, j, |
| 905 | mb, kb, |
| 906 | ((u64)tmp_mb) << 20L, |
| 907 | rir_way, |
| 908 | reg); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 909 | |
| 910 | for (k = 0; k < rir_way; k++) { |
| 911 | pci_read_config_dword(pvt->pci_tad[i], |
| 912 | rir_offset[j][k], |
| 913 | ®); |
| 914 | tmp_mb = RIR_OFFSET(reg) << 6; |
| 915 | |
Mauro Carvalho Chehab | 5b889e3 | 2011-11-07 18:26:53 -0300 | [diff] [blame] | 916 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 917 | edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n", |
| 918 | i, j, k, |
| 919 | mb, kb, |
| 920 | ((u64)tmp_mb) << 20L, |
| 921 | (u32)RIR_RNK_TGT(reg), |
| 922 | reg); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 923 | } |
| 924 | } |
| 925 | } |
| 926 | } |
| 927 | |
Rashika Kheria | 8112c0c | 2013-12-14 19:32:09 +0530 | [diff] [blame] | 928 | static struct mem_ctl_info *get_mci_for_node_id(u8 node_id) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 929 | { |
| 930 | struct sbridge_dev *sbridge_dev; |
| 931 | |
| 932 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { |
| 933 | if (sbridge_dev->node_id == node_id) |
| 934 | return sbridge_dev->mci; |
| 935 | } |
| 936 | return NULL; |
| 937 | } |
| 938 | |
| 939 | static int get_memory_error_data(struct mem_ctl_info *mci, |
| 940 | u64 addr, |
| 941 | u8 *socket, |
| 942 | long *channel_mask, |
| 943 | u8 *rank, |
Mauro Carvalho Chehab | e17a2f42a | 2012-05-11 11:41:45 -0300 | [diff] [blame] | 944 | char **area_type, char *msg) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 945 | { |
| 946 | struct mem_ctl_info *new_mci; |
| 947 | struct sbridge_pvt *pvt = mci->pvt_info; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 948 | struct pci_dev *pci_ha; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 949 | int n_rir, n_sads, n_tads, sad_way, sck_xch; |
| 950 | int sad_interl, idx, base_ch; |
| 951 | int interleave_mode; |
Aristeu Rozanski | ef1ce51 | 2013-10-30 13:27:01 -0300 | [diff] [blame] | 952 | unsigned sad_interleave[pvt->info.max_interleave]; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 953 | u32 reg; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 954 | u8 ch_way, sck_way, pkg, sad_ha = 0; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 955 | u32 tad_offset; |
| 956 | u32 rir_way; |
Mauro Carvalho Chehab | 5b889e3 | 2011-11-07 18:26:53 -0300 | [diff] [blame] | 957 | u32 mb, kb; |
Aristeu Rozanski | bd4b968 | 2013-11-21 09:08:03 -0500 | [diff] [blame] | 958 | u64 ch_addr, offset, limit = 0, prv = 0; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 959 | |
| 960 | |
| 961 | /* |
| 962 | * Step 0) Check if the address is at special memory ranges |
| 963 | * The check bellow is probably enough to fill all cases where |
| 964 | * the error is not inside a memory, except for the legacy |
| 965 | * range (e. g. VGA addresses). It is unlikely, however, that the |
| 966 | * memory controller would generate an error on that range. |
| 967 | */ |
Mauro Carvalho Chehab | 5b889e3 | 2011-11-07 18:26:53 -0300 | [diff] [blame] | 968 | if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) { |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 969 | sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 970 | return -EINVAL; |
| 971 | } |
| 972 | if (addr >= (u64)pvt->tohm) { |
| 973 | sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 974 | return -EINVAL; |
| 975 | } |
| 976 | |
| 977 | /* |
| 978 | * Step 1) Get socket |
| 979 | */ |
Aristeu Rozanski | 464f1d8 | 2013-10-30 13:27:00 -0300 | [diff] [blame] | 980 | for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { |
| 981 | pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 982 | ®); |
| 983 | |
| 984 | if (!DRAM_RULE_ENABLE(reg)) |
| 985 | continue; |
| 986 | |
| 987 | limit = SAD_LIMIT(reg); |
| 988 | if (limit <= prv) { |
| 989 | sprintf(msg, "Can't discover the memory socket"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 990 | return -EINVAL; |
| 991 | } |
| 992 | if (addr <= limit) |
| 993 | break; |
| 994 | prv = limit; |
| 995 | } |
Aristeu Rozanski | 464f1d8 | 2013-10-30 13:27:00 -0300 | [diff] [blame] | 996 | if (n_sads == pvt->info.max_sad) { |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 997 | sprintf(msg, "Can't discover the memory socket"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 998 | return -EINVAL; |
| 999 | } |
Mauro Carvalho Chehab | e17a2f42a | 2012-05-11 11:41:45 -0300 | [diff] [blame] | 1000 | *area_type = get_dram_attr(reg); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1001 | interleave_mode = INTERLEAVE_MODE(reg); |
| 1002 | |
Aristeu Rozanski | ef1ce51 | 2013-10-30 13:27:01 -0300 | [diff] [blame] | 1003 | pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1004 | ®); |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1005 | |
| 1006 | if (pvt->info.type == SANDY_BRIDGE) { |
| 1007 | sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); |
| 1008 | for (sad_way = 0; sad_way < 8; sad_way++) { |
| 1009 | u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); |
| 1010 | if (sad_way > 0 && sad_interl == pkg) |
| 1011 | break; |
| 1012 | sad_interleave[sad_way] = pkg; |
| 1013 | edac_dbg(0, "SAD interleave #%d: %d\n", |
| 1014 | sad_way, sad_interleave[sad_way]); |
| 1015 | } |
| 1016 | edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n", |
| 1017 | pvt->sbridge_dev->mc, |
| 1018 | n_sads, |
| 1019 | addr, |
| 1020 | limit, |
| 1021 | sad_way + 7, |
| 1022 | !interleave_mode ? "" : "XOR[18:16]"); |
| 1023 | if (interleave_mode) |
| 1024 | idx = ((addr >> 6) ^ (addr >> 16)) & 7; |
| 1025 | else |
| 1026 | idx = (addr >> 6) & 7; |
| 1027 | switch (sad_way) { |
| 1028 | case 1: |
| 1029 | idx = 0; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1030 | break; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1031 | case 2: |
| 1032 | idx = idx & 1; |
| 1033 | break; |
| 1034 | case 4: |
| 1035 | idx = idx & 3; |
| 1036 | break; |
| 1037 | case 8: |
| 1038 | break; |
| 1039 | default: |
| 1040 | sprintf(msg, "Can't discover socket interleave"); |
| 1041 | return -EINVAL; |
| 1042 | } |
| 1043 | *socket = sad_interleave[idx]; |
| 1044 | edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n", |
| 1045 | idx, sad_way, *socket); |
| 1046 | } else { |
| 1047 | /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */ |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1048 | idx = (addr >> 6) & 7; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1049 | pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); |
| 1050 | *socket = sad_pkg_socket(pkg); |
| 1051 | sad_ha = sad_pkg_ha(pkg); |
| 1052 | edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n", |
| 1053 | idx, *socket, sad_ha); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1054 | } |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1055 | |
| 1056 | /* |
| 1057 | * Move to the proper node structure, in order to access the |
| 1058 | * right PCI registers |
| 1059 | */ |
| 1060 | new_mci = get_mci_for_node_id(*socket); |
| 1061 | if (!new_mci) { |
| 1062 | sprintf(msg, "Struct for socket #%u wasn't initialized", |
| 1063 | *socket); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1064 | return -EINVAL; |
| 1065 | } |
| 1066 | mci = new_mci; |
| 1067 | pvt = mci->pvt_info; |
| 1068 | |
| 1069 | /* |
| 1070 | * Step 2) Get memory channel |
| 1071 | */ |
| 1072 | prv = 0; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1073 | if (pvt->info.type == SANDY_BRIDGE) |
| 1074 | pci_ha = pvt->pci_ha0; |
| 1075 | else { |
| 1076 | if (sad_ha) |
| 1077 | pci_ha = pvt->pci_ha1; |
| 1078 | else |
| 1079 | pci_ha = pvt->pci_ha0; |
| 1080 | } |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1081 | for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1082 | pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1083 | limit = TAD_LIMIT(reg); |
| 1084 | if (limit <= prv) { |
| 1085 | sprintf(msg, "Can't discover the memory channel"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1086 | return -EINVAL; |
| 1087 | } |
| 1088 | if (addr <= limit) |
| 1089 | break; |
| 1090 | prv = limit; |
| 1091 | } |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1092 | if (n_tads == MAX_TAD) { |
| 1093 | sprintf(msg, "Can't discover the memory channel"); |
| 1094 | return -EINVAL; |
| 1095 | } |
| 1096 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1097 | ch_way = TAD_CH(reg) + 1; |
| 1098 | sck_way = TAD_SOCK(reg) + 1; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1099 | |
| 1100 | if (ch_way == 3) |
| 1101 | idx = addr >> 6; |
| 1102 | else |
| 1103 | idx = addr >> (6 + sck_way); |
| 1104 | idx = idx % ch_way; |
| 1105 | |
| 1106 | /* |
| 1107 | * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ??? |
| 1108 | */ |
| 1109 | switch (idx) { |
| 1110 | case 0: |
| 1111 | base_ch = TAD_TGT0(reg); |
| 1112 | break; |
| 1113 | case 1: |
| 1114 | base_ch = TAD_TGT1(reg); |
| 1115 | break; |
| 1116 | case 2: |
| 1117 | base_ch = TAD_TGT2(reg); |
| 1118 | break; |
| 1119 | case 3: |
| 1120 | base_ch = TAD_TGT3(reg); |
| 1121 | break; |
| 1122 | default: |
| 1123 | sprintf(msg, "Can't discover the TAD target"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1124 | return -EINVAL; |
| 1125 | } |
| 1126 | *channel_mask = 1 << base_ch; |
| 1127 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1128 | pci_read_config_dword(pvt->pci_tad[base_ch], |
| 1129 | tad_ch_nilv_offset[n_tads], |
| 1130 | &tad_offset); |
| 1131 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1132 | if (pvt->is_mirrored) { |
| 1133 | *channel_mask |= 1 << ((base_ch + 2) % 4); |
| 1134 | switch(ch_way) { |
| 1135 | case 2: |
| 1136 | case 4: |
| 1137 | sck_xch = 1 << sck_way * (ch_way >> 1); |
| 1138 | break; |
| 1139 | default: |
| 1140 | sprintf(msg, "Invalid mirror set. Can't decode addr"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1141 | return -EINVAL; |
| 1142 | } |
| 1143 | } else |
| 1144 | sck_xch = (1 << sck_way) * ch_way; |
| 1145 | |
| 1146 | if (pvt->is_lockstep) |
| 1147 | *channel_mask |= 1 << ((base_ch + 1) % 4); |
| 1148 | |
| 1149 | offset = TAD_OFFSET(tad_offset); |
| 1150 | |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1151 | edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n", |
| 1152 | n_tads, |
| 1153 | addr, |
| 1154 | limit, |
| 1155 | (u32)TAD_SOCK(reg), |
| 1156 | ch_way, |
| 1157 | offset, |
| 1158 | idx, |
| 1159 | base_ch, |
| 1160 | *channel_mask); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1161 | |
| 1162 | /* Calculate channel address */ |
| 1163 | /* Remove the TAD offset */ |
| 1164 | |
| 1165 | if (offset > addr) { |
| 1166 | sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!", |
| 1167 | offset, addr); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1168 | return -EINVAL; |
| 1169 | } |
| 1170 | addr -= offset; |
| 1171 | /* Store the low bits [0:6] of the addr */ |
| 1172 | ch_addr = addr & 0x7f; |
| 1173 | /* Remove socket wayness and remove 6 bits */ |
| 1174 | addr >>= 6; |
Mauro Carvalho Chehab | 5b889e3 | 2011-11-07 18:26:53 -0300 | [diff] [blame] | 1175 | addr = div_u64(addr, sck_xch); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1176 | #if 0 |
| 1177 | /* Divide by channel way */ |
| 1178 | addr = addr / ch_way; |
| 1179 | #endif |
| 1180 | /* Recover the last 6 bits */ |
| 1181 | ch_addr |= addr << 6; |
| 1182 | |
| 1183 | /* |
| 1184 | * Step 3) Decode rank |
| 1185 | */ |
| 1186 | for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) { |
| 1187 | pci_read_config_dword(pvt->pci_tad[base_ch], |
| 1188 | rir_way_limit[n_rir], |
| 1189 | ®); |
| 1190 | |
| 1191 | if (!IS_RIR_VALID(reg)) |
| 1192 | continue; |
| 1193 | |
Aristeu Rozanski | b976bcf | 2014-06-02 15:15:24 -0300 | [diff] [blame] | 1194 | limit = pvt->info.rir_limit(reg); |
Mauro Carvalho Chehab | 5b889e3 | 2011-11-07 18:26:53 -0300 | [diff] [blame] | 1195 | mb = div_u64_rem(limit >> 20, 1000, &kb); |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1196 | edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n", |
| 1197 | n_rir, |
| 1198 | mb, kb, |
| 1199 | limit, |
| 1200 | 1 << RIR_WAY(reg)); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1201 | if (ch_addr <= limit) |
| 1202 | break; |
| 1203 | } |
| 1204 | if (n_rir == MAX_RIR_RANGES) { |
| 1205 | sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx", |
| 1206 | ch_addr); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1207 | return -EINVAL; |
| 1208 | } |
| 1209 | rir_way = RIR_WAY(reg); |
| 1210 | if (pvt->is_close_pg) |
| 1211 | idx = (ch_addr >> 6); |
| 1212 | else |
| 1213 | idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */ |
| 1214 | idx %= 1 << rir_way; |
| 1215 | |
| 1216 | pci_read_config_dword(pvt->pci_tad[base_ch], |
| 1217 | rir_offset[n_rir][idx], |
| 1218 | ®); |
| 1219 | *rank = RIR_RNK_TGT(reg); |
| 1220 | |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1221 | edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", |
| 1222 | n_rir, |
| 1223 | ch_addr, |
| 1224 | limit, |
| 1225 | rir_way, |
| 1226 | idx); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1227 | |
| 1228 | return 0; |
| 1229 | } |
| 1230 | |
| 1231 | /**************************************************************************** |
| 1232 | Device initialization routines: put/get, init/exit |
| 1233 | ****************************************************************************/ |
| 1234 | |
| 1235 | /* |
| 1236 | * sbridge_put_all_devices 'put' all the devices that we have |
| 1237 | * reserved via 'get' |
| 1238 | */ |
| 1239 | static void sbridge_put_devices(struct sbridge_dev *sbridge_dev) |
| 1240 | { |
| 1241 | int i; |
| 1242 | |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1243 | edac_dbg(0, "\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1244 | for (i = 0; i < sbridge_dev->n_devs; i++) { |
| 1245 | struct pci_dev *pdev = sbridge_dev->pdev[i]; |
| 1246 | if (!pdev) |
| 1247 | continue; |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1248 | edac_dbg(0, "Removing dev %02x:%02x.%d\n", |
| 1249 | pdev->bus->number, |
| 1250 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1251 | pci_dev_put(pdev); |
| 1252 | } |
| 1253 | } |
| 1254 | |
| 1255 | static void sbridge_put_all_devices(void) |
| 1256 | { |
| 1257 | struct sbridge_dev *sbridge_dev, *tmp; |
| 1258 | |
| 1259 | list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) { |
| 1260 | sbridge_put_devices(sbridge_dev); |
| 1261 | free_sbridge_dev(sbridge_dev); |
| 1262 | } |
| 1263 | } |
| 1264 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1265 | static int sbridge_get_onedevice(struct pci_dev **prev, |
| 1266 | u8 *num_mc, |
| 1267 | const struct pci_id_table *table, |
| 1268 | const unsigned devno) |
| 1269 | { |
| 1270 | struct sbridge_dev *sbridge_dev; |
| 1271 | const struct pci_id_descr *dev_descr = &table->descr[devno]; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1272 | struct pci_dev *pdev = NULL; |
| 1273 | u8 bus = 0; |
| 1274 | |
Jiang Liu | ec5a0b3 | 2014-02-17 13:10:23 +0800 | [diff] [blame] | 1275 | sbridge_printk(KERN_DEBUG, |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1276 | "Seeking for: PCI ID %04x:%04x\n", |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1277 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
| 1278 | |
| 1279 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
| 1280 | dev_descr->dev_id, *prev); |
| 1281 | |
| 1282 | if (!pdev) { |
| 1283 | if (*prev) { |
| 1284 | *prev = pdev; |
| 1285 | return 0; |
| 1286 | } |
| 1287 | |
| 1288 | if (dev_descr->optional) |
| 1289 | return 0; |
| 1290 | |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1291 | /* if the HA wasn't found */ |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1292 | if (devno == 0) |
| 1293 | return -ENODEV; |
| 1294 | |
| 1295 | sbridge_printk(KERN_INFO, |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1296 | "Device not found: %04x:%04x\n", |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1297 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
| 1298 | |
| 1299 | /* End of list, leave */ |
| 1300 | return -ENODEV; |
| 1301 | } |
| 1302 | bus = pdev->bus->number; |
| 1303 | |
| 1304 | sbridge_dev = get_sbridge_dev(bus); |
| 1305 | if (!sbridge_dev) { |
| 1306 | sbridge_dev = alloc_sbridge_dev(bus, table); |
| 1307 | if (!sbridge_dev) { |
| 1308 | pci_dev_put(pdev); |
| 1309 | return -ENOMEM; |
| 1310 | } |
| 1311 | (*num_mc)++; |
| 1312 | } |
| 1313 | |
| 1314 | if (sbridge_dev->pdev[devno]) { |
| 1315 | sbridge_printk(KERN_ERR, |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1316 | "Duplicated device for %04x:%04x\n", |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1317 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
| 1318 | pci_dev_put(pdev); |
| 1319 | return -ENODEV; |
| 1320 | } |
| 1321 | |
| 1322 | sbridge_dev->pdev[devno] = pdev; |
| 1323 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1324 | /* Be sure that the device is enabled */ |
| 1325 | if (unlikely(pci_enable_device(pdev) < 0)) { |
| 1326 | sbridge_printk(KERN_ERR, |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1327 | "Couldn't enable %04x:%04x\n", |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1328 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
| 1329 | return -ENODEV; |
| 1330 | } |
| 1331 | |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1332 | edac_dbg(0, "Detected %04x:%04x\n", |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1333 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1334 | |
| 1335 | /* |
| 1336 | * As stated on drivers/pci/search.c, the reference count for |
| 1337 | * @from is always decremented if it is not %NULL. So, as we need |
| 1338 | * to get all devices up to null, we need to do a get for the device |
| 1339 | */ |
| 1340 | pci_dev_get(pdev); |
| 1341 | |
| 1342 | *prev = pdev; |
| 1343 | |
| 1344 | return 0; |
| 1345 | } |
| 1346 | |
Aristeu Rozanski | 5153a0f | 2013-10-30 13:27:03 -0300 | [diff] [blame] | 1347 | /* |
| 1348 | * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1349 | * devices we want to reference for this driver. |
Aristeu Rozanski | 5153a0f | 2013-10-30 13:27:03 -0300 | [diff] [blame] | 1350 | * @num_mc: pointer to the memory controllers count, to be incremented in case |
| 1351 | * of success. |
| 1352 | * @table: model specific table |
| 1353 | * |
| 1354 | * returns 0 in case of success or error code |
| 1355 | */ |
| 1356 | static int sbridge_get_all_devices(u8 *num_mc, |
| 1357 | const struct pci_id_table *table) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1358 | { |
| 1359 | int i, rc; |
| 1360 | struct pci_dev *pdev = NULL; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1361 | |
| 1362 | while (table && table->descr) { |
| 1363 | for (i = 0; i < table->n_devs; i++) { |
| 1364 | pdev = NULL; |
| 1365 | do { |
| 1366 | rc = sbridge_get_onedevice(&pdev, num_mc, |
| 1367 | table, i); |
| 1368 | if (rc < 0) { |
| 1369 | if (i == 0) { |
| 1370 | i = table->n_devs; |
| 1371 | break; |
| 1372 | } |
| 1373 | sbridge_put_all_devices(); |
| 1374 | return -ENODEV; |
| 1375 | } |
| 1376 | } while (pdev); |
| 1377 | } |
| 1378 | table++; |
| 1379 | } |
| 1380 | |
| 1381 | return 0; |
| 1382 | } |
| 1383 | |
Aristeu Rozanski | ea779b5 | 2013-10-30 13:27:04 -0300 | [diff] [blame] | 1384 | static int sbridge_mci_bind_devs(struct mem_ctl_info *mci, |
| 1385 | struct sbridge_dev *sbridge_dev) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1386 | { |
| 1387 | struct sbridge_pvt *pvt = mci->pvt_info; |
| 1388 | struct pci_dev *pdev; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1389 | int i; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1390 | |
| 1391 | for (i = 0; i < sbridge_dev->n_devs; i++) { |
| 1392 | pdev = sbridge_dev->pdev[i]; |
| 1393 | if (!pdev) |
| 1394 | continue; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1395 | |
| 1396 | switch (pdev->device) { |
| 1397 | case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0: |
| 1398 | pvt->pci_sad0 = pdev; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1399 | break; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1400 | case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1: |
| 1401 | pvt->pci_sad1 = pdev; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1402 | break; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1403 | case PCI_DEVICE_ID_INTEL_SBRIDGE_BR: |
| 1404 | pvt->pci_br0 = pdev; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1405 | break; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1406 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0: |
| 1407 | pvt->pci_ha0 = pdev; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1408 | break; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1409 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA: |
| 1410 | pvt->pci_ta = pdev; |
| 1411 | break; |
| 1412 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS: |
| 1413 | pvt->pci_ras = pdev; |
| 1414 | break; |
| 1415 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0: |
| 1416 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1: |
| 1417 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2: |
| 1418 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3: |
| 1419 | { |
| 1420 | int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0; |
| 1421 | pvt->pci_tad[id] = pdev; |
| 1422 | } |
| 1423 | break; |
| 1424 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO: |
| 1425 | pvt->pci_ddrio = pdev; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1426 | break; |
| 1427 | default: |
| 1428 | goto error; |
| 1429 | } |
| 1430 | |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1431 | edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n", |
| 1432 | pdev->vendor, pdev->device, |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1433 | sbridge_dev->bus, |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1434 | pdev); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1435 | } |
| 1436 | |
| 1437 | /* Check if everything were registered */ |
| 1438 | if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 || |
Luck, Tony | de4772c | 2013-03-28 09:59:15 -0700 | [diff] [blame] | 1439 | !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1440 | goto enodev; |
| 1441 | |
| 1442 | for (i = 0; i < NUM_CHANNELS; i++) { |
| 1443 | if (!pvt->pci_tad[i]) |
| 1444 | goto enodev; |
| 1445 | } |
| 1446 | return 0; |
| 1447 | |
| 1448 | enodev: |
| 1449 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); |
| 1450 | return -ENODEV; |
| 1451 | |
| 1452 | error: |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1453 | sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n", |
| 1454 | PCI_VENDOR_ID_INTEL, pdev->device); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1455 | return -EINVAL; |
| 1456 | } |
| 1457 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1458 | static int ibridge_mci_bind_devs(struct mem_ctl_info *mci, |
| 1459 | struct sbridge_dev *sbridge_dev) |
| 1460 | { |
| 1461 | struct sbridge_pvt *pvt = mci->pvt_info; |
| 1462 | struct pci_dev *pdev, *tmp; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1463 | int i; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1464 | bool mode_2ha = false; |
| 1465 | |
| 1466 | tmp = pci_get_device(PCI_VENDOR_ID_INTEL, |
| 1467 | PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, NULL); |
| 1468 | if (tmp) { |
| 1469 | mode_2ha = true; |
| 1470 | pci_dev_put(tmp); |
| 1471 | } |
| 1472 | |
| 1473 | for (i = 0; i < sbridge_dev->n_devs; i++) { |
| 1474 | pdev = sbridge_dev->pdev[i]; |
| 1475 | if (!pdev) |
| 1476 | continue; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1477 | |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1478 | switch (pdev->device) { |
| 1479 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0: |
| 1480 | pvt->pci_ha0 = pdev; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1481 | break; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1482 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA: |
| 1483 | pvt->pci_ta = pdev; |
| 1484 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS: |
| 1485 | pvt->pci_ras = pdev; |
| 1486 | break; |
| 1487 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2: |
| 1488 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3: |
| 1489 | /* if we have 2 HAs active, channels 2 and 3 |
| 1490 | * are in other device */ |
| 1491 | if (mode_2ha) |
| 1492 | break; |
| 1493 | /* fall through */ |
| 1494 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0: |
| 1495 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1: |
| 1496 | { |
| 1497 | int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0; |
| 1498 | pvt->pci_tad[id] = pdev; |
| 1499 | } |
| 1500 | break; |
| 1501 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0: |
| 1502 | pvt->pci_ddrio = pdev; |
| 1503 | break; |
| 1504 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0: |
| 1505 | if (!mode_2ha) |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1506 | pvt->pci_ddrio = pdev; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1507 | break; |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1508 | case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD: |
| 1509 | pvt->pci_sad0 = pdev; |
| 1510 | break; |
| 1511 | case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0: |
| 1512 | pvt->pci_br0 = pdev; |
| 1513 | break; |
| 1514 | case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1: |
| 1515 | pvt->pci_br1 = pdev; |
| 1516 | break; |
| 1517 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1: |
| 1518 | pvt->pci_ha1 = pdev; |
| 1519 | break; |
| 1520 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0: |
| 1521 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1: |
| 1522 | { |
| 1523 | int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 2; |
| 1524 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1525 | /* we shouldn't have this device if we have just one |
| 1526 | * HA present */ |
| 1527 | WARN_ON(!mode_2ha); |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1528 | pvt->pci_tad[id] = pdev; |
| 1529 | } |
| 1530 | break; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1531 | default: |
| 1532 | goto error; |
| 1533 | } |
| 1534 | |
| 1535 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", |
| 1536 | sbridge_dev->bus, |
| 1537 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
| 1538 | pdev); |
| 1539 | } |
| 1540 | |
| 1541 | /* Check if everything were registered */ |
| 1542 | if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 || |
| 1543 | !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras || |
| 1544 | !pvt->pci_ta) |
| 1545 | goto enodev; |
| 1546 | |
| 1547 | for (i = 0; i < NUM_CHANNELS; i++) { |
| 1548 | if (!pvt->pci_tad[i]) |
| 1549 | goto enodev; |
| 1550 | } |
| 1551 | return 0; |
| 1552 | |
| 1553 | enodev: |
| 1554 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); |
| 1555 | return -ENODEV; |
| 1556 | |
| 1557 | error: |
| 1558 | sbridge_printk(KERN_ERR, |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1559 | "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL, |
| 1560 | pdev->device); |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1561 | return -EINVAL; |
| 1562 | } |
| 1563 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1564 | /**************************************************************************** |
| 1565 | Error check routines |
| 1566 | ****************************************************************************/ |
| 1567 | |
| 1568 | /* |
| 1569 | * While Sandy Bridge has error count registers, SMI BIOS read values from |
| 1570 | * and resets the counters. So, they are not reliable for the OS to read |
| 1571 | * from them. So, we have no option but to just trust on whatever MCE is |
| 1572 | * telling us about the errors. |
| 1573 | */ |
| 1574 | static void sbridge_mce_output_error(struct mem_ctl_info *mci, |
| 1575 | const struct mce *m) |
| 1576 | { |
| 1577 | struct mem_ctl_info *new_mci; |
| 1578 | struct sbridge_pvt *pvt = mci->pvt_info; |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1579 | enum hw_event_mc_err_type tp_event; |
Mauro Carvalho Chehab | e17a2f42a | 2012-05-11 11:41:45 -0300 | [diff] [blame] | 1580 | char *type, *optype, msg[256]; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1581 | bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); |
| 1582 | bool overflow = GET_BITFIELD(m->status, 62, 62); |
| 1583 | bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1584 | bool recoverable; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1585 | u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); |
| 1586 | u32 mscod = GET_BITFIELD(m->status, 16, 31); |
| 1587 | u32 errcode = GET_BITFIELD(m->status, 0, 15); |
| 1588 | u32 channel = GET_BITFIELD(m->status, 0, 3); |
| 1589 | u32 optypenum = GET_BITFIELD(m->status, 4, 6); |
| 1590 | long channel_mask, first_channel; |
| 1591 | u8 rank, socket; |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1592 | int rc, dimm; |
Mauro Carvalho Chehab | e17a2f42a | 2012-05-11 11:41:45 -0300 | [diff] [blame] | 1593 | char *area_type = NULL; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1594 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1595 | if (pvt->info.type == IVY_BRIDGE) |
| 1596 | recoverable = true; |
| 1597 | else |
| 1598 | recoverable = GET_BITFIELD(m->status, 56, 56); |
| 1599 | |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1600 | if (uncorrected_error) { |
| 1601 | if (ripv) { |
| 1602 | type = "FATAL"; |
| 1603 | tp_event = HW_EVENT_ERR_FATAL; |
| 1604 | } else { |
| 1605 | type = "NON_FATAL"; |
| 1606 | tp_event = HW_EVENT_ERR_UNCORRECTED; |
| 1607 | } |
| 1608 | } else { |
| 1609 | type = "CORRECTED"; |
| 1610 | tp_event = HW_EVENT_ERR_CORRECTED; |
| 1611 | } |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1612 | |
| 1613 | /* |
David Mackey | 15ed103 | 2012-04-17 11:30:52 -0700 | [diff] [blame] | 1614 | * According with Table 15-9 of the Intel Architecture spec vol 3A, |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1615 | * memory errors should fit in this mask: |
| 1616 | * 000f 0000 1mmm cccc (binary) |
| 1617 | * where: |
| 1618 | * f = Correction Report Filtering Bit. If 1, subsequent errors |
| 1619 | * won't be shown |
| 1620 | * mmm = error type |
| 1621 | * cccc = channel |
| 1622 | * If the mask doesn't match, report an error to the parsing logic |
| 1623 | */ |
| 1624 | if (! ((errcode & 0xef80) == 0x80)) { |
| 1625 | optype = "Can't parse: it is not a mem"; |
| 1626 | } else { |
| 1627 | switch (optypenum) { |
| 1628 | case 0: |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1629 | optype = "generic undef request error"; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1630 | break; |
| 1631 | case 1: |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1632 | optype = "memory read error"; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1633 | break; |
| 1634 | case 2: |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1635 | optype = "memory write error"; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1636 | break; |
| 1637 | case 3: |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1638 | optype = "addr/cmd error"; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1639 | break; |
| 1640 | case 4: |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1641 | optype = "memory scrubbing error"; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1642 | break; |
| 1643 | default: |
| 1644 | optype = "reserved"; |
| 1645 | break; |
| 1646 | } |
| 1647 | } |
| 1648 | |
Aristeu Rozanski | be3036d | 2013-10-30 13:27:05 -0300 | [diff] [blame] | 1649 | /* Only decode errors with an valid address (ADDRV) */ |
| 1650 | if (!GET_BITFIELD(m->status, 58, 58)) |
| 1651 | return; |
| 1652 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1653 | rc = get_memory_error_data(mci, m->addr, &socket, |
Mauro Carvalho Chehab | e17a2f42a | 2012-05-11 11:41:45 -0300 | [diff] [blame] | 1654 | &channel_mask, &rank, &area_type, msg); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1655 | if (rc < 0) |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1656 | goto err_parsing; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1657 | new_mci = get_mci_for_node_id(socket); |
| 1658 | if (!new_mci) { |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1659 | strcpy(msg, "Error: socket got corrupted!"); |
| 1660 | goto err_parsing; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1661 | } |
| 1662 | mci = new_mci; |
| 1663 | pvt = mci->pvt_info; |
| 1664 | |
| 1665 | first_channel = find_first_bit(&channel_mask, NUM_CHANNELS); |
| 1666 | |
| 1667 | if (rank < 4) |
| 1668 | dimm = 0; |
| 1669 | else if (rank < 8) |
| 1670 | dimm = 1; |
| 1671 | else |
| 1672 | dimm = 2; |
| 1673 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1674 | |
| 1675 | /* |
Mauro Carvalho Chehab | e17a2f42a | 2012-05-11 11:41:45 -0300 | [diff] [blame] | 1676 | * FIXME: On some memory configurations (mirror, lockstep), the |
| 1677 | * Memory Controller can't point the error to a single DIMM. The |
| 1678 | * EDAC core should be handling the channel mask, in order to point |
| 1679 | * to the group of dimm's where the error may be happening. |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1680 | */ |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1681 | snprintf(msg, sizeof(msg), |
Mauro Carvalho Chehab | c105383 | 2012-06-04 13:40:05 -0300 | [diff] [blame] | 1682 | "%s%s area:%s err_code:%04x:%04x socket:%d channel_mask:%ld rank:%d", |
Mauro Carvalho Chehab | e17a2f42a | 2012-05-11 11:41:45 -0300 | [diff] [blame] | 1683 | overflow ? " OVERFLOW" : "", |
| 1684 | (uncorrected_error && recoverable) ? " recoverable" : "", |
| 1685 | area_type, |
| 1686 | mscod, errcode, |
| 1687 | socket, |
| 1688 | channel_mask, |
| 1689 | rank); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1690 | |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1691 | edac_dbg(0, "%s\n", msg); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1692 | |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1693 | /* FIXME: need support for channel mask */ |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1694 | |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1695 | /* Call the helper to output message */ |
Mauro Carvalho Chehab | c105383 | 2012-06-04 13:40:05 -0300 | [diff] [blame] | 1696 | edac_mc_handle_error(tp_event, mci, core_err_cnt, |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1697 | m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, |
| 1698 | channel, dimm, -1, |
Mauro Carvalho Chehab | 03f7eae | 2012-06-04 11:29:25 -0300 | [diff] [blame] | 1699 | optype, msg); |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1700 | return; |
| 1701 | err_parsing: |
Mauro Carvalho Chehab | c105383 | 2012-06-04 13:40:05 -0300 | [diff] [blame] | 1702 | edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0, |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1703 | -1, -1, -1, |
Mauro Carvalho Chehab | 03f7eae | 2012-06-04 11:29:25 -0300 | [diff] [blame] | 1704 | msg, ""); |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1705 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1706 | } |
| 1707 | |
| 1708 | /* |
| 1709 | * sbridge_check_error Retrieve and process errors reported by the |
| 1710 | * hardware. Called by the Core module. |
| 1711 | */ |
| 1712 | static void sbridge_check_error(struct mem_ctl_info *mci) |
| 1713 | { |
| 1714 | struct sbridge_pvt *pvt = mci->pvt_info; |
| 1715 | int i; |
| 1716 | unsigned count = 0; |
| 1717 | struct mce *m; |
| 1718 | |
| 1719 | /* |
| 1720 | * MCE first step: Copy all mce errors into a temporary buffer |
| 1721 | * We use a double buffering here, to reduce the risk of |
| 1722 | * loosing an error. |
| 1723 | */ |
| 1724 | smp_rmb(); |
| 1725 | count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in) |
| 1726 | % MCE_LOG_LEN; |
| 1727 | if (!count) |
| 1728 | return; |
| 1729 | |
| 1730 | m = pvt->mce_outentry; |
| 1731 | if (pvt->mce_in + count > MCE_LOG_LEN) { |
| 1732 | unsigned l = MCE_LOG_LEN - pvt->mce_in; |
| 1733 | |
| 1734 | memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l); |
| 1735 | smp_wmb(); |
| 1736 | pvt->mce_in = 0; |
| 1737 | count -= l; |
| 1738 | m += l; |
| 1739 | } |
| 1740 | memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count); |
| 1741 | smp_wmb(); |
| 1742 | pvt->mce_in += count; |
| 1743 | |
| 1744 | smp_rmb(); |
| 1745 | if (pvt->mce_overrun) { |
| 1746 | sbridge_printk(KERN_ERR, "Lost %d memory errors\n", |
| 1747 | pvt->mce_overrun); |
| 1748 | smp_wmb(); |
| 1749 | pvt->mce_overrun = 0; |
| 1750 | } |
| 1751 | |
| 1752 | /* |
| 1753 | * MCE second step: parse errors and display |
| 1754 | */ |
| 1755 | for (i = 0; i < count; i++) |
| 1756 | sbridge_mce_output_error(mci, &pvt->mce_outentry[i]); |
| 1757 | } |
| 1758 | |
| 1759 | /* |
| 1760 | * sbridge_mce_check_error Replicates mcelog routine to get errors |
| 1761 | * This routine simply queues mcelog errors, and |
| 1762 | * return. The error itself should be handled later |
| 1763 | * by sbridge_check_error. |
| 1764 | * WARNING: As this routine should be called at NMI time, extra care should |
| 1765 | * be taken to avoid deadlocks, and to be as fast as possible. |
| 1766 | */ |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 1767 | static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val, |
| 1768 | void *data) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1769 | { |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 1770 | struct mce *mce = (struct mce *)data; |
| 1771 | struct mem_ctl_info *mci; |
| 1772 | struct sbridge_pvt *pvt; |
Aristeu Rozanski | cf40f80 | 2014-03-11 15:45:41 -0400 | [diff] [blame] | 1773 | char *type; |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 1774 | |
Chen, Gong | fd52103 | 2013-12-06 01:17:09 -0500 | [diff] [blame] | 1775 | if (get_edac_report_status() == EDAC_REPORTING_DISABLED) |
| 1776 | return NOTIFY_DONE; |
| 1777 | |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 1778 | mci = get_mci_for_node_id(mce->socketid); |
| 1779 | if (!mci) |
| 1780 | return NOTIFY_BAD; |
| 1781 | pvt = mci->pvt_info; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1782 | |
| 1783 | /* |
| 1784 | * Just let mcelog handle it if the error is |
| 1785 | * outside the memory controller. A memory error |
| 1786 | * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0. |
| 1787 | * bit 12 has an special meaning. |
| 1788 | */ |
| 1789 | if ((mce->status & 0xefff) >> 7 != 1) |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 1790 | return NOTIFY_DONE; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1791 | |
Aristeu Rozanski | cf40f80 | 2014-03-11 15:45:41 -0400 | [diff] [blame] | 1792 | if (mce->mcgstatus & MCG_STATUS_MCIP) |
| 1793 | type = "Exception"; |
| 1794 | else |
| 1795 | type = "Event"; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1796 | |
Aristeu Rozanski | 49856dc | 2014-03-11 15:45:42 -0400 | [diff] [blame] | 1797 | sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1798 | |
Aristeu Rozanski | 49856dc | 2014-03-11 15:45:42 -0400 | [diff] [blame] | 1799 | sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx " |
| 1800 | "Bank %d: %016Lx\n", mce->extcpu, type, |
| 1801 | mce->mcgstatus, mce->bank, mce->status); |
| 1802 | sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc); |
| 1803 | sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr); |
| 1804 | sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1805 | |
Aristeu Rozanski | 49856dc | 2014-03-11 15:45:42 -0400 | [diff] [blame] | 1806 | sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET " |
| 1807 | "%u APIC %x\n", mce->cpuvendor, mce->cpuid, |
| 1808 | mce->time, mce->socketid, mce->apicid); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1809 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1810 | /* Only handle if it is the right mc controller */ |
| 1811 | if (cpu_data(mce->cpu).phys_proc_id != pvt->sbridge_dev->mc) |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 1812 | return NOTIFY_DONE; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1813 | |
| 1814 | smp_rmb(); |
| 1815 | if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) { |
| 1816 | smp_wmb(); |
| 1817 | pvt->mce_overrun++; |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 1818 | return NOTIFY_DONE; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1819 | } |
| 1820 | |
| 1821 | /* Copy memory error at the ringbuffer */ |
| 1822 | memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce)); |
| 1823 | smp_wmb(); |
| 1824 | pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN; |
| 1825 | |
| 1826 | /* Handle fatal errors immediately */ |
| 1827 | if (mce->mcgstatus & 1) |
| 1828 | sbridge_check_error(mci); |
| 1829 | |
| 1830 | /* Advice mcelog that the error were handled */ |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 1831 | return NOTIFY_STOP; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1832 | } |
| 1833 | |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 1834 | static struct notifier_block sbridge_mce_dec = { |
| 1835 | .notifier_call = sbridge_mce_check_error, |
| 1836 | }; |
| 1837 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1838 | /**************************************************************************** |
| 1839 | EDAC register/unregister logic |
| 1840 | ****************************************************************************/ |
| 1841 | |
| 1842 | static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev) |
| 1843 | { |
| 1844 | struct mem_ctl_info *mci = sbridge_dev->mci; |
| 1845 | struct sbridge_pvt *pvt; |
| 1846 | |
| 1847 | if (unlikely(!mci || !mci->pvt_info)) { |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1848 | edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1849 | |
| 1850 | sbridge_printk(KERN_ERR, "Couldn't find mci handler\n"); |
| 1851 | return; |
| 1852 | } |
| 1853 | |
| 1854 | pvt = mci->pvt_info; |
| 1855 | |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1856 | edac_dbg(0, "MC: mci = %p, dev = %p\n", |
| 1857 | mci, &sbridge_dev->pdev[0]->dev); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1858 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1859 | /* Remove MC sysfs nodes */ |
Mauro Carvalho Chehab | fd68750 | 2012-03-16 07:44:18 -0300 | [diff] [blame] | 1860 | edac_mc_del_mc(mci->pdev); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1861 | |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1862 | edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1863 | kfree(mci->ctl_name); |
| 1864 | edac_mc_free(mci); |
| 1865 | sbridge_dev->mci = NULL; |
| 1866 | } |
| 1867 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1868 | static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1869 | { |
| 1870 | struct mem_ctl_info *mci; |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1871 | struct edac_mc_layer layers[2]; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1872 | struct sbridge_pvt *pvt; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1873 | struct pci_dev *pdev = sbridge_dev->pdev[0]; |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1874 | int rc; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1875 | |
| 1876 | /* Check the number of active and not disabled channels */ |
Aristeu Rozanski | dbc954d | 2014-06-02 15:15:25 -0300 | [diff] [blame] | 1877 | rc = check_if_ecc_is_active(sbridge_dev->bus, type); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1878 | if (unlikely(rc < 0)) |
| 1879 | return rc; |
| 1880 | |
| 1881 | /* allocate a new MC control structure */ |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1882 | layers[0].type = EDAC_MC_LAYER_CHANNEL; |
| 1883 | layers[0].size = NUM_CHANNELS; |
| 1884 | layers[0].is_virt_csrow = false; |
| 1885 | layers[1].type = EDAC_MC_LAYER_SLOT; |
| 1886 | layers[1].size = MAX_DIMMS; |
| 1887 | layers[1].is_virt_csrow = true; |
Mauro Carvalho Chehab | ca0907b | 2012-05-02 14:37:00 -0300 | [diff] [blame] | 1888 | mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers, |
Mauro Carvalho Chehab | c36e3e7 | 2012-04-16 15:12:22 -0300 | [diff] [blame] | 1889 | sizeof(*pvt)); |
| 1890 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1891 | if (unlikely(!mci)) |
| 1892 | return -ENOMEM; |
| 1893 | |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1894 | edac_dbg(0, "MC: mci = %p, dev = %p\n", |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1895 | mci, &pdev->dev); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1896 | |
| 1897 | pvt = mci->pvt_info; |
| 1898 | memset(pvt, 0, sizeof(*pvt)); |
| 1899 | |
| 1900 | /* Associate sbridge_dev and mci for future usage */ |
| 1901 | pvt->sbridge_dev = sbridge_dev; |
| 1902 | sbridge_dev->mci = mci; |
| 1903 | |
| 1904 | mci->mtype_cap = MEM_FLAG_DDR3; |
| 1905 | mci->edac_ctl_cap = EDAC_FLAG_NONE; |
| 1906 | mci->edac_cap = EDAC_FLAG_NONE; |
| 1907 | mci->mod_name = "sbridge_edac.c"; |
| 1908 | mci->mod_ver = SBRIDGE_REVISION; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1909 | mci->dev_name = pci_name(pdev); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1910 | mci->ctl_page_to_phys = NULL; |
| 1911 | |
| 1912 | /* Set the function pointer to an actual operation function */ |
| 1913 | mci->edac_check = sbridge_check_error; |
| 1914 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1915 | pvt->info.type = type; |
| 1916 | if (type == IVY_BRIDGE) { |
| 1917 | pvt->info.rankcfgr = IB_RANK_CFG_A; |
| 1918 | pvt->info.get_tolm = ibridge_get_tolm; |
| 1919 | pvt->info.get_tohm = ibridge_get_tohm; |
| 1920 | pvt->info.dram_rule = ibridge_dram_rule; |
Aristeu Rozanski | 9e37544 | 2014-06-02 15:15:22 -0300 | [diff] [blame] | 1921 | pvt->info.get_memory_type = get_memory_type; |
Aristeu Rozanski | f14d689 | 2014-06-02 15:15:23 -0300 | [diff] [blame] | 1922 | pvt->info.get_node_id = get_node_id; |
Aristeu Rozanski | b976bcf | 2014-06-02 15:15:24 -0300 | [diff] [blame] | 1923 | pvt->info.rir_limit = rir_limit; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1924 | pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); |
| 1925 | pvt->info.interleave_list = ibridge_interleave_list; |
| 1926 | pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); |
| 1927 | pvt->info.interleave_pkg = ibridge_interleave_pkg; |
| 1928 | mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx); |
| 1929 | |
| 1930 | /* Store pci devices at mci for faster access */ |
| 1931 | rc = ibridge_mci_bind_devs(mci, sbridge_dev); |
| 1932 | if (unlikely(rc < 0)) |
| 1933 | goto fail0; |
| 1934 | } else { |
| 1935 | pvt->info.rankcfgr = SB_RANK_CFG_A; |
| 1936 | pvt->info.get_tolm = sbridge_get_tolm; |
| 1937 | pvt->info.get_tohm = sbridge_get_tohm; |
| 1938 | pvt->info.dram_rule = sbridge_dram_rule; |
Aristeu Rozanski | 9e37544 | 2014-06-02 15:15:22 -0300 | [diff] [blame] | 1939 | pvt->info.get_memory_type = get_memory_type; |
Aristeu Rozanski | f14d689 | 2014-06-02 15:15:23 -0300 | [diff] [blame] | 1940 | pvt->info.get_node_id = get_node_id; |
Aristeu Rozanski | b976bcf | 2014-06-02 15:15:24 -0300 | [diff] [blame] | 1941 | pvt->info.rir_limit = rir_limit; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1942 | pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule); |
| 1943 | pvt->info.interleave_list = sbridge_interleave_list; |
| 1944 | pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list); |
| 1945 | pvt->info.interleave_pkg = sbridge_interleave_pkg; |
| 1946 | mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx); |
| 1947 | |
| 1948 | /* Store pci devices at mci for faster access */ |
| 1949 | rc = sbridge_mci_bind_devs(mci, sbridge_dev); |
| 1950 | if (unlikely(rc < 0)) |
| 1951 | goto fail0; |
| 1952 | } |
| 1953 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1954 | |
| 1955 | /* Get dimm basic config and the memory layout */ |
| 1956 | get_dimm_config(mci); |
| 1957 | get_memory_layout(mci); |
| 1958 | |
| 1959 | /* record ptr to the generic device */ |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1960 | mci->pdev = &pdev->dev; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1961 | |
| 1962 | /* add this new MC control structure to EDAC's list of MCs */ |
| 1963 | if (unlikely(edac_mc_add_mc(mci))) { |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 1964 | edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1965 | rc = -EINVAL; |
| 1966 | goto fail0; |
| 1967 | } |
| 1968 | |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1969 | return 0; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1970 | |
| 1971 | fail0: |
| 1972 | kfree(mci->ctl_name); |
| 1973 | edac_mc_free(mci); |
| 1974 | sbridge_dev->mci = NULL; |
| 1975 | return rc; |
| 1976 | } |
| 1977 | |
| 1978 | /* |
| 1979 | * sbridge_probe Probe for ONE instance of device to see if it is |
| 1980 | * present. |
| 1981 | * return: |
| 1982 | * 0 for FOUND a device |
| 1983 | * < 0 for error code |
| 1984 | */ |
| 1985 | |
Greg Kroah-Hartman | 9b3c6e8 | 2012-12-21 13:23:51 -0800 | [diff] [blame] | 1986 | static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1987 | { |
| 1988 | int rc; |
| 1989 | u8 mc, num_mc = 0; |
| 1990 | struct sbridge_dev *sbridge_dev; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 1991 | enum type type; |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 1992 | |
| 1993 | /* get the pci devices we want to reserve for our use */ |
| 1994 | mutex_lock(&sbridge_edac_lock); |
| 1995 | |
| 1996 | /* |
| 1997 | * All memory controllers are allocated at the first pass. |
| 1998 | */ |
| 1999 | if (unlikely(probed >= 1)) { |
| 2000 | mutex_unlock(&sbridge_edac_lock); |
| 2001 | return -ENODEV; |
| 2002 | } |
| 2003 | probed++; |
| 2004 | |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2005 | if (pdev->device == PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA) { |
| 2006 | rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_ibridge_table); |
| 2007 | type = IVY_BRIDGE; |
| 2008 | } else { |
| 2009 | rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table); |
| 2010 | type = SANDY_BRIDGE; |
| 2011 | } |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2012 | if (unlikely(rc < 0)) |
| 2013 | goto fail0; |
| 2014 | mc = 0; |
| 2015 | |
| 2016 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 2017 | edac_dbg(0, "Registering MC#%d (%d of %d)\n", |
| 2018 | mc, mc + 1, num_mc); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2019 | sbridge_dev->mc = mc++; |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2020 | rc = sbridge_register_mci(sbridge_dev, type); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2021 | if (unlikely(rc < 0)) |
| 2022 | goto fail1; |
| 2023 | } |
| 2024 | |
| 2025 | sbridge_printk(KERN_INFO, "Driver loaded.\n"); |
| 2026 | |
| 2027 | mutex_unlock(&sbridge_edac_lock); |
| 2028 | return 0; |
| 2029 | |
| 2030 | fail1: |
| 2031 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) |
| 2032 | sbridge_unregister_mci(sbridge_dev); |
| 2033 | |
| 2034 | sbridge_put_all_devices(); |
| 2035 | fail0: |
| 2036 | mutex_unlock(&sbridge_edac_lock); |
| 2037 | return rc; |
| 2038 | } |
| 2039 | |
| 2040 | /* |
| 2041 | * sbridge_remove destructor for one instance of device |
| 2042 | * |
| 2043 | */ |
Greg Kroah-Hartman | 9b3c6e8 | 2012-12-21 13:23:51 -0800 | [diff] [blame] | 2044 | static void sbridge_remove(struct pci_dev *pdev) |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2045 | { |
| 2046 | struct sbridge_dev *sbridge_dev; |
| 2047 | |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 2048 | edac_dbg(0, "\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2049 | |
| 2050 | /* |
| 2051 | * we have a trouble here: pdev value for removal will be wrong, since |
| 2052 | * it will point to the X58 register used to detect that the machine |
| 2053 | * is a Nehalem or upper design. However, due to the way several PCI |
| 2054 | * devices are grouped together to provide MC functionality, we need |
| 2055 | * to use a different method for releasing the devices |
| 2056 | */ |
| 2057 | |
| 2058 | mutex_lock(&sbridge_edac_lock); |
| 2059 | |
| 2060 | if (unlikely(!probed)) { |
| 2061 | mutex_unlock(&sbridge_edac_lock); |
| 2062 | return; |
| 2063 | } |
| 2064 | |
| 2065 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) |
| 2066 | sbridge_unregister_mci(sbridge_dev); |
| 2067 | |
| 2068 | /* Release PCI resources */ |
| 2069 | sbridge_put_all_devices(); |
| 2070 | |
| 2071 | probed--; |
| 2072 | |
| 2073 | mutex_unlock(&sbridge_edac_lock); |
| 2074 | } |
| 2075 | |
| 2076 | MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl); |
| 2077 | |
| 2078 | /* |
| 2079 | * sbridge_driver pci_driver structure for this module |
| 2080 | * |
| 2081 | */ |
| 2082 | static struct pci_driver sbridge_driver = { |
| 2083 | .name = "sbridge_edac", |
| 2084 | .probe = sbridge_probe, |
Greg Kroah-Hartman | 9b3c6e8 | 2012-12-21 13:23:51 -0800 | [diff] [blame] | 2085 | .remove = sbridge_remove, |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2086 | .id_table = sbridge_pci_tbl, |
| 2087 | }; |
| 2088 | |
| 2089 | /* |
| 2090 | * sbridge_init Module entry function |
| 2091 | * Try to initialize this module for its devices |
| 2092 | */ |
| 2093 | static int __init sbridge_init(void) |
| 2094 | { |
| 2095 | int pci_rc; |
| 2096 | |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 2097 | edac_dbg(2, "\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2098 | |
| 2099 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
| 2100 | opstate_init(); |
| 2101 | |
| 2102 | pci_rc = pci_register_driver(&sbridge_driver); |
Chen Gong | e35fca4 | 2012-05-08 20:40:12 -0300 | [diff] [blame] | 2103 | if (pci_rc >= 0) { |
| 2104 | mce_register_decode_chain(&sbridge_mce_dec); |
Chen, Gong | fd52103 | 2013-12-06 01:17:09 -0500 | [diff] [blame] | 2105 | if (get_edac_report_status() == EDAC_REPORTING_DISABLED) |
| 2106 | sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2107 | return 0; |
Chen Gong | e35fca4 | 2012-05-08 20:40:12 -0300 | [diff] [blame] | 2108 | } |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2109 | |
| 2110 | sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n", |
| 2111 | pci_rc); |
| 2112 | |
| 2113 | return pci_rc; |
| 2114 | } |
| 2115 | |
| 2116 | /* |
| 2117 | * sbridge_exit() Module exit function |
| 2118 | * Unregister the driver |
| 2119 | */ |
| 2120 | static void __exit sbridge_exit(void) |
| 2121 | { |
Joe Perches | 956b9ba1 | 2012-04-29 17:08:39 -0300 | [diff] [blame] | 2122 | edac_dbg(2, "\n"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2123 | pci_unregister_driver(&sbridge_driver); |
Chen Gong | e35fca4 | 2012-05-08 20:40:12 -0300 | [diff] [blame] | 2124 | mce_unregister_decode_chain(&sbridge_mce_dec); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2125 | } |
| 2126 | |
| 2127 | module_init(sbridge_init); |
| 2128 | module_exit(sbridge_exit); |
| 2129 | |
| 2130 | module_param(edac_op_state, int, 0444); |
| 2131 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |
| 2132 | |
| 2133 | MODULE_LICENSE("GPL"); |
Mauro Carvalho Chehab | 37e59f8 | 2014-02-07 08:03:07 -0200 | [diff] [blame] | 2134 | MODULE_AUTHOR("Mauro Carvalho Chehab"); |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2135 | MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); |
Aristeu Rozanski | 4d715a8 | 2013-10-30 13:27:06 -0300 | [diff] [blame] | 2136 | MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - " |
Mauro Carvalho Chehab | eebf11a | 2011-10-20 19:18:01 -0200 | [diff] [blame] | 2137 | SBRIDGE_REVISION); |