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Catalin Marinasb3901d52012-03-05 11:49:28 +00001/*
2 * Based on arch/arm/kernel/process.c
3 *
4 * Original Copyright (C) 1995 Linus Torvalds
5 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
6 * Copyright (C) 2012 ARM Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <stdarg.h>
22
AKASHI Takahirofd92d4a2014-04-30 10:51:32 +010023#include <linux/compat.h>
Ard Biesheuvel60c0d452015-03-06 15:49:24 +010024#include <linux/efi.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000025#include <linux/export.h>
26#include <linux/sched.h>
27#include <linux/kernel.h>
28#include <linux/mm.h>
29#include <linux/stddef.h>
30#include <linux/unistd.h>
31#include <linux/user.h>
32#include <linux/delay.h>
33#include <linux/reboot.h>
34#include <linux/interrupt.h>
35#include <linux/kallsyms.h>
36#include <linux/init.h>
37#include <linux/cpu.h>
38#include <linux/elfcore.h>
39#include <linux/pm.h>
40#include <linux/tick.h>
41#include <linux/utsname.h>
42#include <linux/uaccess.h>
43#include <linux/random.h>
44#include <linux/hw_breakpoint.h>
45#include <linux/personality.h>
46#include <linux/notifier.h>
Jisheng Zhang096b3222015-09-16 22:23:21 +080047#include <trace/events/power.h>
Mark Rutlandc02433d2016-11-03 20:23:13 +000048#include <linux/percpu.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000049
James Morse57f49592016-02-05 14:58:48 +000050#include <asm/alternative.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000051#include <asm/compat.h>
52#include <asm/cacheflush.h>
James Morsed0854412016-10-18 11:27:48 +010053#include <asm/exec.h>
Will Deaconec45d1c2013-01-17 12:31:45 +000054#include <asm/fpsimd.h>
55#include <asm/mmu_context.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000056#include <asm/processor.h>
57#include <asm/stacktrace.h>
Catalin Marinasb3901d52012-03-05 11:49:28 +000058
Laura Abbottc0c264a2014-06-25 23:55:03 +010059#ifdef CONFIG_CC_STACKPROTECTOR
60#include <linux/stackprotector.h>
61unsigned long __stack_chk_guard __read_mostly;
62EXPORT_SYMBOL(__stack_chk_guard);
63#endif
64
Catalin Marinasb3901d52012-03-05 11:49:28 +000065/*
66 * Function pointers to optional machine specific functions
67 */
68void (*pm_power_off)(void);
69EXPORT_SYMBOL_GPL(pm_power_off);
70
Catalin Marinasb0946fc2013-07-23 11:05:10 +010071void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
Catalin Marinasb3901d52012-03-05 11:49:28 +000072
Catalin Marinasb3901d52012-03-05 11:49:28 +000073/*
74 * This is our default idle handler.
75 */
Thomas Gleixner00872982013-03-21 22:49:39 +010076void arch_cpu_idle(void)
Catalin Marinasb3901d52012-03-05 11:49:28 +000077{
78 /*
79 * This should do all the clock switching and wait for interrupt
80 * tricks
81 */
Jisheng Zhang096b3222015-09-16 22:23:21 +080082 trace_cpu_idle_rcuidle(1, smp_processor_id());
Nicolas Pitre69905662014-02-17 10:59:30 -050083 cpu_do_idle();
84 local_irq_enable();
Jisheng Zhang096b3222015-09-16 22:23:21 +080085 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
Catalin Marinasb3901d52012-03-05 11:49:28 +000086}
87
Mark Rutland9327e2c2013-10-24 20:30:18 +010088#ifdef CONFIG_HOTPLUG_CPU
89void arch_cpu_idle_dead(void)
90{
91 cpu_die();
92}
93#endif
94
Arun KS90f51a02014-05-07 02:41:22 +010095/*
96 * Called by kexec, immediately prior to machine_kexec().
97 *
98 * This must completely disable all secondary CPUs; simply causing those CPUs
99 * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
100 * kexec'd kernel to use any and all RAM as it sees fit, without having to
101 * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
102 * functionality embodied in disable_nonboot_cpus() to achieve this.
103 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000104void machine_shutdown(void)
105{
Arun KS90f51a02014-05-07 02:41:22 +0100106 disable_nonboot_cpus();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000107}
108
Arun KS90f51a02014-05-07 02:41:22 +0100109/*
110 * Halting simply requires that the secondary CPUs stop performing any
111 * activity (executing tasks, handling interrupts). smp_send_stop()
112 * achieves this.
113 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000114void machine_halt(void)
115{
Arun KSb9acc492014-05-07 02:41:23 +0100116 local_irq_disable();
Arun KS90f51a02014-05-07 02:41:22 +0100117 smp_send_stop();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000118 while (1);
119}
120
Arun KS90f51a02014-05-07 02:41:22 +0100121/*
122 * Power-off simply requires that the secondary CPUs stop performing any
123 * activity (executing tasks, handling interrupts). smp_send_stop()
124 * achieves this. When the system power is turned off, it will take all CPUs
125 * with it.
126 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000127void machine_power_off(void)
128{
Arun KSb9acc492014-05-07 02:41:23 +0100129 local_irq_disable();
Arun KS90f51a02014-05-07 02:41:22 +0100130 smp_send_stop();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000131 if (pm_power_off)
132 pm_power_off();
133}
134
Arun KS90f51a02014-05-07 02:41:22 +0100135/*
136 * Restart requires that the secondary CPUs stop performing any activity
Mark Rutland68234df2015-04-20 10:24:35 +0100137 * while the primary CPU resets the system. Systems with multiple CPUs must
Arun KS90f51a02014-05-07 02:41:22 +0100138 * provide a HW restart implementation, to ensure that all CPUs reset at once.
139 * This is required so that any code running after reset on the primary CPU
140 * doesn't have to co-ordinate with other CPUs to ensure they aren't still
141 * executing pre-reset code, and using RAM that the primary CPU's code wishes
142 * to use. Implementing such co-ordination would be essentially impossible.
143 */
Catalin Marinasb3901d52012-03-05 11:49:28 +0000144void machine_restart(char *cmd)
145{
Catalin Marinasb3901d52012-03-05 11:49:28 +0000146 /* Disable interrupts first */
147 local_irq_disable();
Arun KSb9acc492014-05-07 02:41:23 +0100148 smp_send_stop();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000149
Ard Biesheuvel60c0d452015-03-06 15:49:24 +0100150 /*
151 * UpdateCapsule() depends on the system being reset via
152 * ResetSystem().
153 */
154 if (efi_enabled(EFI_RUNTIME_SERVICES))
155 efi_reboot(reboot_mode, NULL);
156
Catalin Marinasb3901d52012-03-05 11:49:28 +0000157 /* Now call the architecture specific reboot code. */
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000158 if (arm_pm_restart)
Marc Zyngierff701302013-07-11 12:13:00 +0100159 arm_pm_restart(reboot_mode, cmd);
Guenter Roeck1c7ffc32014-09-26 00:03:16 +0000160 else
161 do_kernel_restart(cmd);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000162
163 /*
164 * Whoops - the architecture was unable to reboot.
165 */
166 printk("Reboot failed -- System halted\n");
167 while (1);
168}
169
170void __show_regs(struct pt_regs *regs)
171{
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100172 int i, top_reg;
173 u64 lr, sp;
174
175 if (compat_user_mode(regs)) {
176 lr = regs->compat_lr;
177 sp = regs->compat_sp;
178 top_reg = 12;
179 } else {
180 lr = regs->regs[30];
181 sp = regs->sp;
182 top_reg = 29;
183 }
Catalin Marinasb3901d52012-03-05 11:49:28 +0000184
Tejun Heoa43cb952013-04-30 15:27:17 -0700185 show_regs_print_info(KERN_DEFAULT);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000186 print_symbol("PC is at %s\n", instruction_pointer(regs));
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100187 print_symbol("LR is at %s\n", lr);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000188 printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
Catalin Marinas6ca68e82013-09-17 18:49:46 +0100189 regs->pc, lr, regs->pstate);
190 printk("sp : %016llx\n", sp);
Mark Rutlanddb4b0712016-10-20 12:23:16 +0100191
192 i = top_reg;
193
194 while (i >= 0) {
Catalin Marinasb3901d52012-03-05 11:49:28 +0000195 printk("x%-2d: %016llx ", i, regs->regs[i]);
Mark Rutlanddb4b0712016-10-20 12:23:16 +0100196 i--;
197
198 if (i % 2 == 0) {
199 pr_cont("x%-2d: %016llx ", i, regs->regs[i]);
200 i--;
201 }
202
203 pr_cont("\n");
Catalin Marinasb3901d52012-03-05 11:49:28 +0000204 }
205 printk("\n");
206}
207
208void show_regs(struct pt_regs * regs)
209{
210 printk("\n");
Catalin Marinasb3901d52012-03-05 11:49:28 +0000211 __show_regs(regs);
212}
213
Will Deaconeb35bdd72014-09-11 14:38:16 +0100214static void tls_thread_flush(void)
215{
Mark Rutlandadf75892016-09-08 13:55:38 +0100216 write_sysreg(0, tpidr_el0);
Will Deaconeb35bdd72014-09-11 14:38:16 +0100217
218 if (is_compat_task()) {
219 current->thread.tp_value = 0;
220
221 /*
222 * We need to ensure ordering between the shadow state and the
223 * hardware state, so that we don't corrupt the hardware state
224 * with a stale shadow state during context switch.
225 */
226 barrier();
Mark Rutlandadf75892016-09-08 13:55:38 +0100227 write_sysreg(0, tpidrro_el0);
Will Deaconeb35bdd72014-09-11 14:38:16 +0100228 }
229}
230
Catalin Marinasb3901d52012-03-05 11:49:28 +0000231void flush_thread(void)
232{
233 fpsimd_flush_thread();
Will Deaconeb35bdd72014-09-11 14:38:16 +0100234 tls_thread_flush();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000235 flush_ptrace_hw_breakpoint(current);
236}
237
238void release_thread(struct task_struct *dead_task)
239{
240}
241
242int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
243{
Janet Liu6eb6c802015-06-11 12:04:32 +0800244 if (current->mm)
245 fpsimd_preserve_current_state();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000246 *dst = *src;
247 return 0;
248}
249
250asmlinkage void ret_from_fork(void) asm("ret_from_fork");
251
252int copy_thread(unsigned long clone_flags, unsigned long stack_start,
Al Viroafa86fc2012-10-22 22:51:14 -0400253 unsigned long stk_sz, struct task_struct *p)
Catalin Marinasb3901d52012-03-05 11:49:28 +0000254{
255 struct pt_regs *childregs = task_pt_regs(p);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000256
Catalin Marinasb3901d52012-03-05 11:49:28 +0000257 memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
Catalin Marinasb3901d52012-03-05 11:49:28 +0000258
Al Viro9ac08002012-10-21 15:56:52 -0400259 if (likely(!(p->flags & PF_KTHREAD))) {
260 *childregs = *current_pt_regs();
Catalin Marinasc34501d2012-10-05 12:31:20 +0100261 childregs->regs[0] = 0;
Will Deacond00a3812015-05-27 15:39:40 +0100262
263 /*
264 * Read the current TLS pointer from tpidr_el0 as it may be
265 * out-of-sync with the saved value.
266 */
Mark Rutlandadf75892016-09-08 13:55:38 +0100267 *task_user_tls(p) = read_sysreg(tpidr_el0);
Will Deacond00a3812015-05-27 15:39:40 +0100268
269 if (stack_start) {
270 if (is_compat_thread(task_thread_info(p)))
Al Viroe0fd18c2012-10-18 00:55:54 -0400271 childregs->compat_sp = stack_start;
Will Deacond00a3812015-05-27 15:39:40 +0100272 else
Al Viroe0fd18c2012-10-18 00:55:54 -0400273 childregs->sp = stack_start;
Catalin Marinasc34501d2012-10-05 12:31:20 +0100274 }
Will Deacond00a3812015-05-27 15:39:40 +0100275
Catalin Marinasc34501d2012-10-05 12:31:20 +0100276 /*
277 * If a TLS pointer was passed to clone (4th argument), use it
278 * for the new thread.
279 */
280 if (clone_flags & CLONE_SETTLS)
Will Deacond00a3812015-05-27 15:39:40 +0100281 p->thread.tp_value = childregs->regs[3];
Catalin Marinasc34501d2012-10-05 12:31:20 +0100282 } else {
283 memset(childregs, 0, sizeof(struct pt_regs));
284 childregs->pstate = PSR_MODE_EL1h;
James Morse57f49592016-02-05 14:58:48 +0000285 if (IS_ENABLED(CONFIG_ARM64_UAO) &&
Suzuki K Poulosea4023f682016-11-08 13:56:20 +0000286 cpus_have_const_cap(ARM64_HAS_UAO))
James Morse57f49592016-02-05 14:58:48 +0000287 childregs->pstate |= PSR_UAO_BIT;
Catalin Marinasc34501d2012-10-05 12:31:20 +0100288 p->thread.cpu_context.x19 = stack_start;
289 p->thread.cpu_context.x20 = stk_sz;
290 }
291 p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
292 p->thread.cpu_context.sp = (unsigned long)childregs;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000293
294 ptrace_hw_copy_thread(p);
295
296 return 0;
297}
298
299static void tls_thread_switch(struct task_struct *next)
300{
301 unsigned long tpidr, tpidrro;
302
Mark Rutlandadf75892016-09-08 13:55:38 +0100303 tpidr = read_sysreg(tpidr_el0);
Will Deacond00a3812015-05-27 15:39:40 +0100304 *task_user_tls(current) = tpidr;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000305
Will Deacond00a3812015-05-27 15:39:40 +0100306 tpidr = *task_user_tls(next);
307 tpidrro = is_compat_thread(task_thread_info(next)) ?
308 next->thread.tp_value : 0;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000309
Mark Rutlandadf75892016-09-08 13:55:38 +0100310 write_sysreg(tpidr, tpidr_el0);
311 write_sysreg(tpidrro, tpidrro_el0);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000312}
313
James Morse57f49592016-02-05 14:58:48 +0000314/* Restore the UAO state depending on next's addr_limit */
James Morsed0854412016-10-18 11:27:48 +0100315void uao_thread_switch(struct task_struct *next)
James Morse57f49592016-02-05 14:58:48 +0000316{
Catalin Marinase9506312016-02-18 15:50:04 +0000317 if (IS_ENABLED(CONFIG_ARM64_UAO)) {
318 if (task_thread_info(next)->addr_limit == KERNEL_DS)
319 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO));
320 else
321 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO));
322 }
James Morse57f49592016-02-05 14:58:48 +0000323}
324
Catalin Marinasb3901d52012-03-05 11:49:28 +0000325/*
Mark Rutlandc02433d2016-11-03 20:23:13 +0000326 * We store our current task in sp_el0, which is clobbered by userspace. Keep a
327 * shadow copy so that we can restore this upon entry from userspace.
328 *
329 * This is *only* for exception entry from EL0, and is not valid until we
330 * __switch_to() a user task.
331 */
332DEFINE_PER_CPU(struct task_struct *, __entry_task);
333
334static void entry_task_switch(struct task_struct *next)
335{
336 __this_cpu_write(__entry_task, next);
337}
338
339/*
Catalin Marinasb3901d52012-03-05 11:49:28 +0000340 * Thread switching.
341 */
342struct task_struct *__switch_to(struct task_struct *prev,
343 struct task_struct *next)
344{
345 struct task_struct *last;
346
347 fpsimd_thread_switch(next);
348 tls_thread_switch(next);
349 hw_breakpoint_thread_switch(next);
Christopher Covington33257322013-04-03 19:01:01 +0100350 contextidr_thread_switch(next);
Mark Rutlandc02433d2016-11-03 20:23:13 +0000351 entry_task_switch(next);
James Morse57f49592016-02-05 14:58:48 +0000352 uao_thread_switch(next);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000353
Catalin Marinas5108c672013-04-24 14:47:02 +0100354 /*
355 * Complete any pending TLB or cache maintenance on this CPU in case
356 * the thread migrates to a different CPU.
357 */
Will Deacon98f76852014-05-02 16:24:10 +0100358 dsb(ish);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000359
360 /* the actual thread switch */
361 last = cpu_switch_to(prev, next);
362
363 return last;
364}
365
Catalin Marinasb3901d52012-03-05 11:49:28 +0000366unsigned long get_wchan(struct task_struct *p)
367{
368 struct stackframe frame;
Mark Rutland9bbd4c52016-11-03 20:23:08 +0000369 unsigned long stack_page, ret = 0;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000370 int count = 0;
371 if (!p || p == current || p->state == TASK_RUNNING)
372 return 0;
373
Mark Rutland9bbd4c52016-11-03 20:23:08 +0000374 stack_page = (unsigned long)try_get_task_stack(p);
375 if (!stack_page)
376 return 0;
377
Catalin Marinasb3901d52012-03-05 11:49:28 +0000378 frame.fp = thread_saved_fp(p);
379 frame.sp = thread_saved_sp(p);
380 frame.pc = thread_saved_pc(p);
AKASHI Takahiro20380bb2015-12-15 17:33:41 +0900381#ifdef CONFIG_FUNCTION_GRAPH_TRACER
382 frame.graph = p->curr_ret_stack;
383#endif
Catalin Marinasb3901d52012-03-05 11:49:28 +0000384 do {
Konstantin Khlebnikov408c3652013-12-05 13:30:10 +0000385 if (frame.sp < stack_page ||
386 frame.sp >= stack_page + THREAD_SIZE ||
AKASHI Takahirofe13f952015-12-15 17:33:40 +0900387 unwind_frame(p, &frame))
Mark Rutland9bbd4c52016-11-03 20:23:08 +0000388 goto out;
389 if (!in_sched_functions(frame.pc)) {
390 ret = frame.pc;
391 goto out;
392 }
Catalin Marinasb3901d52012-03-05 11:49:28 +0000393 } while (count ++ < 16);
Mark Rutland9bbd4c52016-11-03 20:23:08 +0000394
395out:
396 put_task_stack(p);
397 return ret;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000398}
399
400unsigned long arch_align_stack(unsigned long sp)
401{
402 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
403 sp -= get_random_int() & ~PAGE_MASK;
404 return sp & ~0xf;
405}
406
Catalin Marinasb3901d52012-03-05 11:49:28 +0000407unsigned long arch_randomize_brk(struct mm_struct *mm)
408{
Kees Cook61462c82016-05-10 10:55:49 -0700409 if (is_compat_task())
Jason Cooperfa5114c2016-10-11 13:54:02 -0700410 return randomize_page(mm->brk, 0x02000000);
Kees Cook61462c82016-05-10 10:55:49 -0700411 else
Jason Cooperfa5114c2016-10-11 13:54:02 -0700412 return randomize_page(mm->brk, 0x40000000);
Catalin Marinasb3901d52012-03-05 11:49:28 +0000413}