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Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Jamie Ilesc9353ae2011-01-24 12:19:12 +00002/*
3 * Copyright 2010-2011 Picochip Ltd., Jamie Iles
4 * http://www.picochip.com
5 *
Jamie Ilesc9353ae2011-01-24 12:19:12 +00006 * This file implements a driver for the Synopsys DesignWare watchdog device
Baruch Siach58a251f2013-12-30 14:25:54 +02007 * in the many subsystems. The watchdog has 16 different timeout periods
Jamie Ilesc9353ae2011-01-24 12:19:12 +00008 * and these are a function of the input clock frequency.
9 *
10 * The DesignWare watchdog cannot be stopped once it has been started so we
Guenter Roeckf29a72c2016-02-28 13:12:19 -080011 * do not implement a stop function. The watchdog core will continue to send
12 * heartbeat requests after the watchdog device has been closed.
Jamie Ilesc9353ae2011-01-24 12:19:12 +000013 */
Joe Perches27c766a2012-02-15 15:06:19 -080014
Jamie Ilesc9353ae2011-01-24 12:19:12 +000015#include <linux/bitops.h>
16#include <linux/clk.h>
Jisheng Zhang31228f42014-09-23 15:42:12 +080017#include <linux/delay.h>
Jamie Ilesc9353ae2011-01-24 12:19:12 +000018#include <linux/err.h>
Jamie Ilesc9353ae2011-01-24 12:19:12 +000019#include <linux/io.h>
20#include <linux/kernel.h>
Jamie Ilesc9353ae2011-01-24 12:19:12 +000021#include <linux/module.h>
22#include <linux/moduleparam.h>
Dinh Nguyen58e56372013-10-22 11:59:12 -050023#include <linux/of.h>
Jamie Ilesc9353ae2011-01-24 12:19:12 +000024#include <linux/pm.h>
25#include <linux/platform_device.h>
Steffen Trumtrar65a3b692017-05-22 10:51:39 +020026#include <linux/reset.h>
Jamie Ilesc9353ae2011-01-24 12:19:12 +000027#include <linux/watchdog.h>
28
29#define WDOG_CONTROL_REG_OFFSET 0x00
30#define WDOG_CONTROL_REG_WDT_EN_MASK 0x01
Brian Norrisa81abbb2018-03-09 19:46:06 -080031#define WDOG_CONTROL_REG_RESP_MODE_MASK 0x02
Jamie Ilesc9353ae2011-01-24 12:19:12 +000032#define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04
Jisheng Zhangdfa07142014-09-23 15:42:11 +080033#define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4
Jamie Ilesc9353ae2011-01-24 12:19:12 +000034#define WDOG_CURRENT_COUNT_REG_OFFSET 0x08
35#define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c
36#define WDOG_COUNTER_RESTART_KICK_VALUE 0x76
37
38/* The maximum TOP (timeout period) value that can be set in the watchdog. */
39#define DW_WDT_MAX_TOP 15
40
Doug Andersonb5ade9b2015-01-27 14:25:17 -080041#define DW_WDT_DEFAULT_SECONDS 30
42
Wim Van Sebroeck86a1e182012-03-05 16:51:11 +010043static bool nowayout = WATCHDOG_NOWAYOUT;
44module_param(nowayout, bool, 0);
Jamie Ilesc9353ae2011-01-24 12:19:12 +000045MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
46 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
47
Guenter Roeckf29a72c2016-02-28 13:12:19 -080048struct dw_wdt {
Jamie Ilesc9353ae2011-01-24 12:19:12 +000049 void __iomem *regs;
50 struct clk *clk;
Guenter Roeckc97344f2016-08-09 22:35:58 -070051 unsigned long rate;
Guenter Roeckf29a72c2016-02-28 13:12:19 -080052 struct watchdog_device wdd;
Steffen Trumtrar65a3b692017-05-22 10:51:39 +020053 struct reset_control *rst;
Brian Norris8c088372018-03-09 19:46:07 -080054 /* Save/restore */
55 u32 control;
56 u32 timeout;
Guenter Roeckf29a72c2016-02-28 13:12:19 -080057};
Jamie Ilesc9353ae2011-01-24 12:19:12 +000058
Guenter Roeckf29a72c2016-02-28 13:12:19 -080059#define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd)
60
61static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt)
Jamie Ilesc9353ae2011-01-24 12:19:12 +000062{
Guenter Roeckf29a72c2016-02-28 13:12:19 -080063 return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) &
Jamie Ilesc9353ae2011-01-24 12:19:12 +000064 WDOG_CONTROL_REG_WDT_EN_MASK;
65}
66
Guenter Roeckf29a72c2016-02-28 13:12:19 -080067static inline int dw_wdt_top_in_seconds(struct dw_wdt *dw_wdt, unsigned top)
Jamie Ilesc9353ae2011-01-24 12:19:12 +000068{
69 /*
70 * There are 16 possible timeout values in 0..15 where the number of
71 * cycles is 2 ^ (16 + i) and the watchdog counts down.
72 */
Guenter Roeckc97344f2016-08-09 22:35:58 -070073 return (1U << (16 + top)) / dw_wdt->rate;
Jamie Ilesc9353ae2011-01-24 12:19:12 +000074}
75
Guenter Roeckf29a72c2016-02-28 13:12:19 -080076static int dw_wdt_get_top(struct dw_wdt *dw_wdt)
Jamie Ilesc9353ae2011-01-24 12:19:12 +000077{
Guenter Roeckf29a72c2016-02-28 13:12:19 -080078 int top = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;
Jamie Ilesc9353ae2011-01-24 12:19:12 +000079
Guenter Roeckf29a72c2016-02-28 13:12:19 -080080 return dw_wdt_top_in_seconds(dw_wdt, top);
Jamie Ilesc9353ae2011-01-24 12:19:12 +000081}
82
Guenter Roeckf29a72c2016-02-28 13:12:19 -080083static int dw_wdt_ping(struct watchdog_device *wdd)
Jamie Ilesc9353ae2011-01-24 12:19:12 +000084{
Guenter Roeckf29a72c2016-02-28 13:12:19 -080085 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
Jamie Ilesc9353ae2011-01-24 12:19:12 +000086
Guenter Roeckf29a72c2016-02-28 13:12:19 -080087 writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs +
Doug Andersona0085012015-01-27 14:25:16 -080088 WDOG_COUNTER_RESTART_REG_OFFSET);
Guenter Roeckf29a72c2016-02-28 13:12:19 -080089
90 return 0;
Doug Andersona0085012015-01-27 14:25:16 -080091}
92
Guenter Roeckf29a72c2016-02-28 13:12:19 -080093static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s)
Jamie Ilesc9353ae2011-01-24 12:19:12 +000094{
Guenter Roeckf29a72c2016-02-28 13:12:19 -080095 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
Jamie Ilesc9353ae2011-01-24 12:19:12 +000096 int i, top_val = DW_WDT_MAX_TOP;
97
98 /*
99 * Iterate over the timeout values until we find the closest match. We
100 * always look for >=.
101 */
102 for (i = 0; i <= DW_WDT_MAX_TOP; ++i)
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800103 if (dw_wdt_top_in_seconds(dw_wdt, i) >= top_s) {
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000104 top_val = i;
105 break;
106 }
107
Doug Andersona0085012015-01-27 14:25:16 -0800108 /*
109 * Set the new value in the watchdog. Some versions of dw_wdt
110 * have have TOPINIT in the TIMEOUT_RANGE register (as per
111 * CP_WDT_DUAL_TOP in WDT_COMP_PARAMS_1). On those we
112 * effectively get a pat of the watchdog right here.
113 */
Jisheng Zhangdfa07142014-09-23 15:42:11 +0800114 writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT,
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800115 dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000116
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800117 wdd->timeout = dw_wdt_top_in_seconds(dw_wdt, top_val);
Doug Andersona0085012015-01-27 14:25:16 -0800118
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800119 return 0;
120}
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000121
Brian Norrisa81abbb2018-03-09 19:46:06 -0800122static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt)
123{
124 u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
125
126 /* Disable interrupt mode; always perform system reset. */
127 val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
128 /* Enable watchdog. */
129 val |= WDOG_CONTROL_REG_WDT_EN_MASK;
130 writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
131}
132
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800133static int dw_wdt_start(struct watchdog_device *wdd)
134{
135 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
136
137 dw_wdt_set_timeout(wdd, wdd->timeout);
Brian Norrisa81abbb2018-03-09 19:46:06 -0800138 dw_wdt_arm_system_reset(dw_wdt);
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800139
140 return 0;
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000141}
142
Oleksij Rempel1bfe8882017-09-26 08:11:22 +0200143static int dw_wdt_stop(struct watchdog_device *wdd)
144{
145 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
146
147 if (!dw_wdt->rst) {
148 set_bit(WDOG_HW_RUNNING, &wdd->status);
149 return 0;
150 }
151
152 reset_control_assert(dw_wdt->rst);
153 reset_control_deassert(dw_wdt->rst);
154
155 return 0;
156}
157
Guenter Roecka70dcc02017-01-04 12:27:21 -0800158static int dw_wdt_restart(struct watchdog_device *wdd,
159 unsigned long action, void *data)
Jisheng Zhang31228f42014-09-23 15:42:12 +0800160{
Guenter Roecka70dcc02017-01-04 12:27:21 -0800161 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
Jisheng Zhang31228f42014-09-23 15:42:12 +0800162
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800163 writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
Brian Norrisa81abbb2018-03-09 19:46:06 -0800164 if (dw_wdt_is_enabled(dw_wdt))
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800165 writel(WDOG_COUNTER_RESTART_KICK_VALUE,
166 dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);
Jisheng Zhang31228f42014-09-23 15:42:12 +0800167 else
Brian Norrisa81abbb2018-03-09 19:46:06 -0800168 dw_wdt_arm_system_reset(dw_wdt);
Jisheng Zhang31228f42014-09-23 15:42:12 +0800169
170 /* wait for reset to assert... */
171 mdelay(500);
172
Guenter Roecka70dcc02017-01-04 12:27:21 -0800173 return 0;
Jisheng Zhang31228f42014-09-23 15:42:12 +0800174}
175
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800176static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd)
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000177{
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800178 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000179
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800180 return readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET) /
Guenter Roeckc97344f2016-08-09 22:35:58 -0700181 dw_wdt->rate;
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000182}
183
184static const struct watchdog_info dw_wdt_ident = {
185 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
186 WDIOF_MAGICCLOSE,
187 .identity = "Synopsys DesignWare Watchdog",
188};
189
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800190static const struct watchdog_ops dw_wdt_ops = {
191 .owner = THIS_MODULE,
192 .start = dw_wdt_start,
Oleksij Rempel1bfe8882017-09-26 08:11:22 +0200193 .stop = dw_wdt_stop,
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800194 .ping = dw_wdt_ping,
195 .set_timeout = dw_wdt_set_timeout,
196 .get_timeleft = dw_wdt_get_timeleft,
Guenter Roecka70dcc02017-01-04 12:27:21 -0800197 .restart = dw_wdt_restart,
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800198};
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000199
Heiko Stübnerad83c6c2013-06-26 20:03:52 +0200200#ifdef CONFIG_PM_SLEEP
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000201static int dw_wdt_suspend(struct device *dev)
202{
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800203 struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
204
Brian Norris8c088372018-03-09 19:46:07 -0800205 dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
206 dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
207
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800208 clk_disable_unprepare(dw_wdt->clk);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000209
210 return 0;
211}
212
213static int dw_wdt_resume(struct device *dev)
214{
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800215 struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
216 int err = clk_prepare_enable(dw_wdt->clk);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000217
218 if (err)
219 return err;
220
Brian Norris8c088372018-03-09 19:46:07 -0800221 writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
222 writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
223
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800224 dw_wdt_ping(&dw_wdt->wdd);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000225
226 return 0;
227}
Heiko Stübnerad83c6c2013-06-26 20:03:52 +0200228#endif /* CONFIG_PM_SLEEP */
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000229
Heiko Stübnerad83c6c2013-06-26 20:03:52 +0200230static SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000231
Bill Pemberton2d991a12012-11-19 13:21:41 -0500232static int dw_wdt_drv_probe(struct platform_device *pdev)
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000233{
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800234 struct device *dev = &pdev->dev;
235 struct watchdog_device *wdd;
236 struct dw_wdt *dw_wdt;
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000237 int ret;
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000238
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800239 dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL);
240 if (!dw_wdt)
241 return -ENOMEM;
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000242
Guenter Roeck0f0a6a22019-04-02 12:01:53 -0700243 dw_wdt->regs = devm_platform_ioremap_resource(pdev, 0);
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800244 if (IS_ERR(dw_wdt->regs))
245 return PTR_ERR(dw_wdt->regs);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000246
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800247 dw_wdt->clk = devm_clk_get(dev, NULL);
248 if (IS_ERR(dw_wdt->clk))
249 return PTR_ERR(dw_wdt->clk);
250
251 ret = clk_prepare_enable(dw_wdt->clk);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000252 if (ret)
Jingoo Hancf3cc8c2013-04-29 18:15:26 +0900253 return ret;
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000254
Guenter Roeckc97344f2016-08-09 22:35:58 -0700255 dw_wdt->rate = clk_get_rate(dw_wdt->clk);
256 if (dw_wdt->rate == 0) {
257 ret = -EINVAL;
258 goto out_disable_clk;
259 }
260
Steffen Trumtrar65a3b692017-05-22 10:51:39 +0200261 dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
262 if (IS_ERR(dw_wdt->rst)) {
263 ret = PTR_ERR(dw_wdt->rst);
264 goto out_disable_clk;
265 }
266
267 reset_control_deassert(dw_wdt->rst);
268
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800269 wdd = &dw_wdt->wdd;
270 wdd->info = &dw_wdt_ident;
271 wdd->ops = &dw_wdt_ops;
272 wdd->min_timeout = 1;
273 wdd->max_hw_heartbeat_ms =
274 dw_wdt_top_in_seconds(dw_wdt, DW_WDT_MAX_TOP) * 1000;
275 wdd->parent = dev;
276
277 watchdog_set_drvdata(wdd, dw_wdt);
278 watchdog_set_nowayout(wdd, nowayout);
279 watchdog_init_timeout(wdd, 0, dev);
280
281 /*
282 * If the watchdog is already running, use its already configured
283 * timeout. Otherwise use the default or the value provided through
284 * devicetree.
285 */
286 if (dw_wdt_is_enabled(dw_wdt)) {
287 wdd->timeout = dw_wdt_get_top(dw_wdt);
288 set_bit(WDOG_HW_RUNNING, &wdd->status);
289 } else {
290 wdd->timeout = DW_WDT_DEFAULT_SECONDS;
291 watchdog_init_timeout(wdd, 0, dev);
292 }
293
294 platform_set_drvdata(pdev, dw_wdt);
295
Guenter Roecka70dcc02017-01-04 12:27:21 -0800296 watchdog_set_restart_priority(wdd, 128);
297
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800298 ret = watchdog_register_device(wdd);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000299 if (ret)
300 goto out_disable_clk;
301
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000302 return 0;
303
304out_disable_clk:
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800305 clk_disable_unprepare(dw_wdt->clk);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000306 return ret;
307}
308
Bill Pemberton4b12b892012-11-19 13:26:24 -0500309static int dw_wdt_drv_remove(struct platform_device *pdev)
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000310{
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800311 struct dw_wdt *dw_wdt = platform_get_drvdata(pdev);
Jisheng Zhang31228f42014-09-23 15:42:12 +0800312
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800313 watchdog_unregister_device(&dw_wdt->wdd);
Steffen Trumtrar65a3b692017-05-22 10:51:39 +0200314 reset_control_assert(dw_wdt->rst);
Guenter Roeckf29a72c2016-02-28 13:12:19 -0800315 clk_disable_unprepare(dw_wdt->clk);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000316
317 return 0;
318}
319
Dinh Nguyen58e56372013-10-22 11:59:12 -0500320#ifdef CONFIG_OF
321static const struct of_device_id dw_wdt_of_match[] = {
322 { .compatible = "snps,dw-wdt", },
323 { /* sentinel */ }
324};
325MODULE_DEVICE_TABLE(of, dw_wdt_of_match);
326#endif
327
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000328static struct platform_driver dw_wdt_driver = {
329 .probe = dw_wdt_drv_probe,
Bill Pemberton82268712012-11-19 13:21:12 -0500330 .remove = dw_wdt_drv_remove,
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000331 .driver = {
332 .name = "dw_wdt",
Dinh Nguyen58e56372013-10-22 11:59:12 -0500333 .of_match_table = of_match_ptr(dw_wdt_of_match),
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000334 .pm = &dw_wdt_pm_ops,
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000335 },
336};
337
Axel Linb8ec6112011-11-29 13:56:27 +0800338module_platform_driver(dw_wdt_driver);
Jamie Ilesc9353ae2011-01-24 12:19:12 +0000339
340MODULE_AUTHOR("Jamie Iles");
341MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver");
342MODULE_LICENSE("GPL");