Andreas Färber | 54f884c | 2018-01-21 17:31:36 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Actions Semi S500 SoC |
| 4 | * |
| 5 | * Copyright (c) 2016-2017 Andreas Färber |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
Cristian Ciocaltea | b4d1e23 | 2020-12-29 23:17:16 +0200 | [diff] [blame] | 8 | #include <dt-bindings/clock/actions,s500-cmu.h> |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 9 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Andreas Färber | 4dc8bf9 | 2017-06-05 21:20:17 +0200 | [diff] [blame] | 10 | #include <dt-bindings/power/owl-s500-powergate.h> |
Cristian Ciocaltea | 0c2e4ec | 2020-12-29 23:17:18 +0200 | [diff] [blame] | 11 | #include <dt-bindings/reset/actions,s500-reset.h> |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 12 | |
| 13 | / { |
| 14 | compatible = "actions,s500"; |
| 15 | interrupt-parent = <&gic>; |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <1>; |
| 18 | |
| 19 | aliases { |
| 20 | }; |
| 21 | |
| 22 | chosen { |
| 23 | }; |
| 24 | |
| 25 | cpus { |
| 26 | #address-cells = <1>; |
| 27 | #size-cells = <0>; |
| 28 | |
| 29 | cpu0: cpu@0 { |
| 30 | device_type = "cpu"; |
| 31 | compatible = "arm,cortex-a9"; |
| 32 | reg = <0x0>; |
Andreas Färber | ad90c2b | 2017-02-26 17:24:54 +0100 | [diff] [blame] | 33 | enable-method = "actions,s500-smp"; |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 34 | }; |
| 35 | |
| 36 | cpu1: cpu@1 { |
| 37 | device_type = "cpu"; |
| 38 | compatible = "arm,cortex-a9"; |
| 39 | reg = <0x1>; |
Andreas Färber | ad90c2b | 2017-02-26 17:24:54 +0100 | [diff] [blame] | 40 | enable-method = "actions,s500-smp"; |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 41 | }; |
| 42 | |
| 43 | cpu2: cpu@2 { |
| 44 | device_type = "cpu"; |
| 45 | compatible = "arm,cortex-a9"; |
| 46 | reg = <0x2>; |
Andreas Färber | ad90c2b | 2017-02-26 17:24:54 +0100 | [diff] [blame] | 47 | enable-method = "actions,s500-smp"; |
Andreas Färber | 4dc8bf9 | 2017-06-05 21:20:17 +0200 | [diff] [blame] | 48 | power-domains = <&sps S500_PD_CPU2>; |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 49 | }; |
| 50 | |
| 51 | cpu3: cpu@3 { |
| 52 | device_type = "cpu"; |
| 53 | compatible = "arm,cortex-a9"; |
| 54 | reg = <0x3>; |
Andreas Färber | ad90c2b | 2017-02-26 17:24:54 +0100 | [diff] [blame] | 55 | enable-method = "actions,s500-smp"; |
Andreas Färber | 4dc8bf9 | 2017-06-05 21:20:17 +0200 | [diff] [blame] | 56 | power-domains = <&sps S500_PD_CPU3>; |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 57 | }; |
| 58 | }; |
| 59 | |
| 60 | arm-pmu { |
| 61 | compatible = "arm,cortex-a9-pmu"; |
| 62 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| 63 | <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, |
| 64 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, |
| 65 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 66 | interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; |
| 67 | }; |
| 68 | |
| 69 | hosc: hosc { |
| 70 | compatible = "fixed-clock"; |
| 71 | clock-frequency = <24000000>; |
| 72 | #clock-cells = <0>; |
| 73 | }; |
| 74 | |
Cristian Ciocaltea | b4d1e23 | 2020-12-29 23:17:16 +0200 | [diff] [blame] | 75 | losc: losc { |
| 76 | compatible = "fixed-clock"; |
| 77 | clock-frequency = <32768>; |
| 78 | #clock-cells = <0>; |
| 79 | }; |
| 80 | |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 81 | soc { |
| 82 | compatible = "simple-bus"; |
| 83 | #address-cells = <1>; |
| 84 | #size-cells = <1>; |
| 85 | ranges; |
| 86 | |
| 87 | scu: scu@b0020000 { |
| 88 | compatible = "arm,cortex-a9-scu"; |
| 89 | reg = <0xb0020000 0x100>; |
| 90 | }; |
| 91 | |
| 92 | global_timer: timer@b0020200 { |
| 93 | compatible = "arm,cortex-a9-global-timer"; |
| 94 | reg = <0xb0020200 0x100>; |
Cristian Ciocaltea | 55f6c99 | 2020-08-28 16:53:17 +0300 | [diff] [blame] | 95 | interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 96 | status = "disabled"; |
| 97 | }; |
| 98 | |
| 99 | twd_timer: timer@b0020600 { |
| 100 | compatible = "arm,cortex-a9-twd-timer"; |
| 101 | reg = <0xb0020600 0x20>; |
Cristian Ciocaltea | 55f6c99 | 2020-08-28 16:53:17 +0300 | [diff] [blame] | 102 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 103 | status = "disabled"; |
| 104 | }; |
| 105 | |
| 106 | twd_wdt: wdt@b0020620 { |
| 107 | compatible = "arm,cortex-a9-twd-wdt"; |
| 108 | reg = <0xb0020620 0xe0>; |
Cristian Ciocaltea | 55f6c99 | 2020-08-28 16:53:17 +0300 | [diff] [blame] | 109 | interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 110 | status = "disabled"; |
| 111 | }; |
| 112 | |
| 113 | gic: interrupt-controller@b0021000 { |
| 114 | compatible = "arm,cortex-a9-gic"; |
| 115 | reg = <0xb0021000 0x1000>, |
| 116 | <0xb0020100 0x0100>; |
| 117 | interrupt-controller; |
| 118 | #interrupt-cells = <3>; |
| 119 | }; |
| 120 | |
| 121 | l2: cache-controller@b0022000 { |
| 122 | compatible = "arm,pl310-cache"; |
| 123 | reg = <0xb0022000 0x1000>; |
| 124 | cache-unified; |
| 125 | cache-level = <2>; |
| 126 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
| 127 | arm,tag-latency = <3 3 2>; |
| 128 | arm,data-latency = <5 3 3>; |
| 129 | }; |
| 130 | |
| 131 | uart0: serial@b0120000 { |
| 132 | compatible = "actions,s500-uart", "actions,owl-uart"; |
| 133 | reg = <0xb0120000 0x2000>; |
| 134 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
Cristian Ciocaltea | 11bc96b | 2020-12-29 23:17:17 +0200 | [diff] [blame] | 135 | clocks = <&cmu CLK_UART0>; |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 136 | status = "disabled"; |
| 137 | }; |
| 138 | |
| 139 | uart1: serial@b0122000 { |
| 140 | compatible = "actions,s500-uart", "actions,owl-uart"; |
| 141 | reg = <0xb0122000 0x2000>; |
| 142 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
Cristian Ciocaltea | 11bc96b | 2020-12-29 23:17:17 +0200 | [diff] [blame] | 143 | clocks = <&cmu CLK_UART1>; |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 144 | status = "disabled"; |
| 145 | }; |
| 146 | |
| 147 | uart2: serial@b0124000 { |
| 148 | compatible = "actions,s500-uart", "actions,owl-uart"; |
| 149 | reg = <0xb0124000 0x2000>; |
| 150 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
Cristian Ciocaltea | 11bc96b | 2020-12-29 23:17:17 +0200 | [diff] [blame] | 151 | clocks = <&cmu CLK_UART2>; |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 152 | status = "disabled"; |
| 153 | }; |
| 154 | |
| 155 | uart3: serial@b0126000 { |
| 156 | compatible = "actions,s500-uart", "actions,owl-uart"; |
| 157 | reg = <0xb0126000 0x2000>; |
| 158 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
Cristian Ciocaltea | 11bc96b | 2020-12-29 23:17:17 +0200 | [diff] [blame] | 159 | clocks = <&cmu CLK_UART3>; |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 160 | status = "disabled"; |
| 161 | }; |
| 162 | |
| 163 | uart4: serial@b0128000 { |
| 164 | compatible = "actions,s500-uart", "actions,owl-uart"; |
| 165 | reg = <0xb0128000 0x2000>; |
| 166 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
Cristian Ciocaltea | 11bc96b | 2020-12-29 23:17:17 +0200 | [diff] [blame] | 167 | clocks = <&cmu CLK_UART4>; |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 168 | status = "disabled"; |
| 169 | }; |
| 170 | |
| 171 | uart5: serial@b012a000 { |
| 172 | compatible = "actions,s500-uart", "actions,owl-uart"; |
| 173 | reg = <0xb012a000 0x2000>; |
| 174 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
Cristian Ciocaltea | 11bc96b | 2020-12-29 23:17:17 +0200 | [diff] [blame] | 175 | clocks = <&cmu CLK_UART5>; |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 176 | status = "disabled"; |
| 177 | }; |
| 178 | |
| 179 | uart6: serial@b012c000 { |
| 180 | compatible = "actions,s500-uart", "actions,owl-uart"; |
| 181 | reg = <0xb012c000 0x2000>; |
| 182 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
Cristian Ciocaltea | 11bc96b | 2020-12-29 23:17:17 +0200 | [diff] [blame] | 183 | clocks = <&cmu CLK_UART6>; |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 184 | status = "disabled"; |
| 185 | }; |
| 186 | |
Cristian Ciocaltea | b4d1e23 | 2020-12-29 23:17:16 +0200 | [diff] [blame] | 187 | cmu: clock-controller@b0160000 { |
| 188 | compatible = "actions,s500-cmu"; |
| 189 | reg = <0xb0160000 0x8000>; |
| 190 | clocks = <&hosc>, <&losc>; |
| 191 | #clock-cells = <1>; |
Cristian Ciocaltea | 0c2e4ec | 2020-12-29 23:17:18 +0200 | [diff] [blame] | 192 | #reset-cells = <1>; |
Cristian Ciocaltea | b4d1e23 | 2020-12-29 23:17:16 +0200 | [diff] [blame] | 193 | }; |
| 194 | |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 195 | timer: timer@b0168000 { |
| 196 | compatible = "actions,s500-timer"; |
| 197 | reg = <0xb0168000 0x8000>; |
| 198 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| 199 | <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 200 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, |
| 201 | <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| 202 | interrupt-names = "2hz0", "2hz1", "timer0", "timer1"; |
| 203 | }; |
Andreas Färber | 740f6beb | 2017-02-26 04:08:53 +0100 | [diff] [blame] | 204 | |
| 205 | sps: power-controller@b01b0100 { |
| 206 | compatible = "actions,s500-sps"; |
| 207 | reg = <0xb01b0100 0x100>; |
| 208 | #power-domain-cells = <1>; |
| 209 | }; |
Cristian Ciocaltea | 2cfb1b3 | 2020-12-29 23:17:21 +0200 | [diff] [blame^] | 210 | |
| 211 | dma: dma-controller@b0260000 { |
| 212 | compatible = "actions,s500-dma"; |
| 213 | reg = <0xb0260000 0xd00>; |
| 214 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, |
| 215 | <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, |
| 216 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, |
| 217 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
| 218 | #dma-cells = <1>; |
| 219 | dma-channels = <12>; |
| 220 | dma-requests = <46>; |
| 221 | clocks = <&cmu CLK_DMAC>; |
| 222 | power-domains = <&sps S500_PD_DMA>; |
| 223 | }; |
Andreas Färber | fdfe7f4 | 2017-02-15 11:15:20 +0100 | [diff] [blame] | 224 | }; |
| 225 | }; |