blob: e7a793961408d09c5e36991d45e2156f85faaca5 [file] [log] [blame]
Thomas Gleixnercaab2772019-06-03 07:44:50 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Marc Zyngierf27bb132012-03-05 11:49:33 +00002/*
3 * Copyright (C) 2012 ARM Ltd.
Marc Zyngierf27bb132012-03-05 11:49:33 +00004 */
5
6#include <linux/linkage.h>
7#include <linux/const.h>
8#include <asm/assembler.h>
9#include <asm/page.h>
Andrew Pinski60e0a092016-02-02 12:46:26 +000010#include <asm/cpufeature.h>
11#include <asm/alternative.h>
Marc Zyngierf27bb132012-03-05 11:49:33 +000012
13/*
14 * Copy a page from src to dest (both are page aligned)
15 *
16 * Parameters:
17 * x0 - dest
18 * x1 - src
19 */
Mark Brown3ac0f452020-01-06 19:58:17 +000020SYM_FUNC_START(copy_page)
Mark Rutland6ba3b552016-09-07 11:07:09 +010021alternative_if ARM64_HAS_NO_HW_PREFETCH
Ard Biesheuvel288be972017-07-12 15:44:14 +010022 // Prefetch three cache lines ahead.
23 prfm pldl1strm, [x1, #128]
24 prfm pldl1strm, [x1, #256]
25 prfm pldl1strm, [x1, #384]
Mark Rutland6ba3b552016-09-07 11:07:09 +010026alternative_else_nop_endif
Andrew Pinski60e0a092016-02-02 12:46:26 +000027
Will Deacon223e23e2016-02-02 12:46:25 +000028 ldp x2, x3, [x1]
Marc Zyngierf27bb132012-03-05 11:49:33 +000029 ldp x4, x5, [x1, #16]
30 ldp x6, x7, [x1, #32]
31 ldp x8, x9, [x1, #48]
Will Deacon223e23e2016-02-02 12:46:25 +000032 ldp x10, x11, [x1, #64]
33 ldp x12, x13, [x1, #80]
34 ldp x14, x15, [x1, #96]
35 ldp x16, x17, [x1, #112]
36
Ard Biesheuvel7f153cc2019-12-06 14:13:38 -080037 add x0, x0, #256
Will Deacon223e23e2016-02-02 12:46:25 +000038 add x1, x1, #128
391:
Ard Biesheuvel7f153cc2019-12-06 14:13:38 -080040 tst x0, #(PAGE_SIZE - 1)
Will Deacon223e23e2016-02-02 12:46:25 +000041
Mark Rutland6ba3b552016-09-07 11:07:09 +010042alternative_if ARM64_HAS_NO_HW_PREFETCH
Ard Biesheuvel288be972017-07-12 15:44:14 +010043 prfm pldl1strm, [x1, #384]
Mark Rutland6ba3b552016-09-07 11:07:09 +010044alternative_else_nop_endif
Andrew Pinski60e0a092016-02-02 12:46:26 +000045
Ard Biesheuvel7f153cc2019-12-06 14:13:38 -080046 stnp x2, x3, [x0, #-256]
Will Deacon223e23e2016-02-02 12:46:25 +000047 ldp x2, x3, [x1]
Ard Biesheuvel7f153cc2019-12-06 14:13:38 -080048 stnp x4, x5, [x0, #16 - 256]
Will Deacon223e23e2016-02-02 12:46:25 +000049 ldp x4, x5, [x1, #16]
Ard Biesheuvel7f153cc2019-12-06 14:13:38 -080050 stnp x6, x7, [x0, #32 - 256]
Will Deacon223e23e2016-02-02 12:46:25 +000051 ldp x6, x7, [x1, #32]
Ard Biesheuvel7f153cc2019-12-06 14:13:38 -080052 stnp x8, x9, [x0, #48 - 256]
Will Deacon223e23e2016-02-02 12:46:25 +000053 ldp x8, x9, [x1, #48]
Ard Biesheuvel7f153cc2019-12-06 14:13:38 -080054 stnp x10, x11, [x0, #64 - 256]
Will Deacon223e23e2016-02-02 12:46:25 +000055 ldp x10, x11, [x1, #64]
Ard Biesheuvel7f153cc2019-12-06 14:13:38 -080056 stnp x12, x13, [x0, #80 - 256]
Will Deacon223e23e2016-02-02 12:46:25 +000057 ldp x12, x13, [x1, #80]
Ard Biesheuvel7f153cc2019-12-06 14:13:38 -080058 stnp x14, x15, [x0, #96 - 256]
Will Deacon223e23e2016-02-02 12:46:25 +000059 ldp x14, x15, [x1, #96]
Ard Biesheuvel7f153cc2019-12-06 14:13:38 -080060 stnp x16, x17, [x0, #112 - 256]
Will Deacon223e23e2016-02-02 12:46:25 +000061 ldp x16, x17, [x1, #112]
62
63 add x0, x0, #128
64 add x1, x1, #128
65
Ard Biesheuvel7f153cc2019-12-06 14:13:38 -080066 b.ne 1b
Will Deacon223e23e2016-02-02 12:46:25 +000067
Ard Biesheuvel7f153cc2019-12-06 14:13:38 -080068 stnp x2, x3, [x0, #-256]
69 stnp x4, x5, [x0, #16 - 256]
70 stnp x6, x7, [x0, #32 - 256]
71 stnp x8, x9, [x0, #48 - 256]
72 stnp x10, x11, [x0, #64 - 256]
73 stnp x12, x13, [x0, #80 - 256]
74 stnp x14, x15, [x0, #96 - 256]
75 stnp x16, x17, [x0, #112 - 256]
Will Deacon223e23e2016-02-02 12:46:25 +000076
Marc Zyngierf27bb132012-03-05 11:49:33 +000077 ret
Mark Brown3ac0f452020-01-06 19:58:17 +000078SYM_FUNC_END(copy_page)
Mark Rutland50fdecb2018-12-07 18:08:19 +000079EXPORT_SYMBOL(copy_page)