Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #include <linux/init.h> |
| 2 | #include <linux/bitops.h> |
| 3 | #include <linux/mm.h> |
| 4 | #include <asm/io.h> |
| 5 | #include <asm/processor.h> |
Andi Kleen | d3f7eae | 2007-08-10 22:31:07 +0200 | [diff] [blame] | 6 | #include <asm/apic.h> |
Thomas Gleixner | c1e3619 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 7 | #include <asm/mach_apic.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | |
| 9 | #include "cpu.h" |
| 10 | |
| 11 | /* |
| 12 | * B step AMD K6 before B 9730xxxx have hardware bugs that can cause |
| 13 | * misexecution of code under Linux. Owners of such processors should |
| 14 | * contact AMD for precise details and a CPU swap. |
| 15 | * |
| 16 | * See http://www.multimania.com/poulot/k6bug.html |
| 17 | * http://www.amd.com/K6/k6docs/revgd.html |
| 18 | * |
| 19 | * The following test is erm.. interesting. AMD neglected to up |
| 20 | * the chip setting when fixing the bug but they also tweaked some |
| 21 | * performance at the same time.. |
| 22 | */ |
| 23 | |
| 24 | extern void vide(void); |
| 25 | __asm__(".align 4\nvide: ret"); |
| 26 | |
Andi Kleen | d3f7eae | 2007-08-10 22:31:07 +0200 | [diff] [blame] | 27 | #ifdef CONFIG_X86_LOCAL_APIC |
Andi Kleen | 3556ddf | 2007-04-02 12:14:12 +0200 | [diff] [blame] | 28 | #define ENABLE_C1E_MASK 0x18000000 |
| 29 | #define CPUID_PROCESSOR_SIGNATURE 1 |
| 30 | #define CPUID_XFAM 0x0ff00000 |
| 31 | #define CPUID_XFAM_K8 0x00000000 |
| 32 | #define CPUID_XFAM_10H 0x00100000 |
| 33 | #define CPUID_XFAM_11H 0x00200000 |
| 34 | #define CPUID_XMOD 0x000f0000 |
| 35 | #define CPUID_XMOD_REV_F 0x00040000 |
| 36 | |
| 37 | /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */ |
| 38 | static __cpuinit int amd_apic_timer_broken(void) |
| 39 | { |
| 40 | u32 lo, hi; |
| 41 | u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); |
| 42 | switch (eax & CPUID_XFAM) { |
| 43 | case CPUID_XFAM_K8: |
| 44 | if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F) |
| 45 | break; |
| 46 | case CPUID_XFAM_10H: |
| 47 | case CPUID_XFAM_11H: |
| 48 | rdmsr(MSR_K8_ENABLE_C1E, lo, hi); |
Thomas Gleixner | c1e3619 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 49 | if (lo & ENABLE_C1E_MASK) { |
| 50 | if (smp_processor_id() != boot_cpu_physical_apicid) |
| 51 | printk(KERN_INFO "AMD C1E detected late. " |
| 52 | " Force timer broadcast.\n"); |
Andi Kleen | 3556ddf | 2007-04-02 12:14:12 +0200 | [diff] [blame] | 53 | return 1; |
Thomas Gleixner | c1e3619 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 54 | } |
| 55 | break; |
| 56 | default: |
| 57 | /* err on the side of caution */ |
Andi Kleen | 3556ddf | 2007-04-02 12:14:12 +0200 | [diff] [blame] | 58 | return 1; |
Thomas Gleixner | c1e3619 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 59 | } |
Andi Kleen | 3556ddf | 2007-04-02 12:14:12 +0200 | [diff] [blame] | 60 | return 0; |
| 61 | } |
Andi Kleen | d3f7eae | 2007-08-10 22:31:07 +0200 | [diff] [blame] | 62 | #endif |
Andi Kleen | 3556ddf | 2007-04-02 12:14:12 +0200 | [diff] [blame] | 63 | |
Andi Kleen | f039b75 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 64 | int force_mwait __cpuinitdata; |
| 65 | |
Andi Kleen | 2b16a23 | 2008-01-30 13:32:40 +0100 | [diff] [blame^] | 66 | void __cpuinit early_init_amd(struct cpuinfo_x86 *c) |
| 67 | { |
| 68 | if (cpuid_eax(0x80000000) >= 0x80000007) { |
| 69 | c->x86_power = cpuid_edx(0x80000007); |
| 70 | if (c->x86_power & (1<<8)) |
| 71 | set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); |
| 72 | } |
| 73 | } |
| 74 | |
Magnus Damm | b4af3f7 | 2006-09-26 10:52:36 +0200 | [diff] [blame] | 75 | static void __cpuinit init_amd(struct cpuinfo_x86 *c) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 76 | { |
| 77 | u32 l, h; |
| 78 | int mbytes = num_physpages >> (20-PAGE_SHIFT); |
| 79 | int r; |
| 80 | |
Andi Kleen | 7d318d7 | 2005-09-29 22:05:55 +0200 | [diff] [blame] | 81 | #ifdef CONFIG_SMP |
Andi Kleen | 3c92c2b | 2005-10-11 01:28:33 +0200 | [diff] [blame] | 82 | unsigned long long value; |
Andi Kleen | 7d318d7 | 2005-09-29 22:05:55 +0200 | [diff] [blame] | 83 | |
| 84 | /* Disable TLB flush filter by setting HWCR.FFDIS on K8 |
| 85 | * bit 6 of msr C001_0015 |
| 86 | * |
| 87 | * Errata 63 for SH-B3 steppings |
| 88 | * Errata 122 for all steppings (F+ have it disabled by default) |
| 89 | */ |
| 90 | if (c->x86 == 15) { |
| 91 | rdmsrl(MSR_K7_HWCR, value); |
| 92 | value |= 1 << 6; |
| 93 | wrmsrl(MSR_K7_HWCR, value); |
| 94 | } |
| 95 | #endif |
| 96 | |
Andi Kleen | 2b16a23 | 2008-01-30 13:32:40 +0100 | [diff] [blame^] | 97 | early_init_amd(c); |
| 98 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 99 | /* |
| 100 | * FIXME: We should handle the K5 here. Set up the write |
| 101 | * range and also turn on MSR 83 bits 4 and 31 (write alloc, |
| 102 | * no bus pipeline) |
| 103 | */ |
| 104 | |
| 105 | /* Bit 31 in normal CPUID used for nonstandard 3DNow ID; |
| 106 | 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */ |
| 107 | clear_bit(0*32+31, c->x86_capability); |
| 108 | |
| 109 | r = get_model_name(c); |
| 110 | |
| 111 | switch(c->x86) |
| 112 | { |
| 113 | case 4: |
| 114 | /* |
| 115 | * General Systems BIOSen alias the cpu frequency registers |
| 116 | * of the Elan at 0x000df000. Unfortuantly, one of the Linux |
| 117 | * drivers subsequently pokes it, and changes the CPU speed. |
| 118 | * Workaround : Remove the unneeded alias. |
| 119 | */ |
| 120 | #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ |
| 121 | #define CBAR_ENB (0x80000000) |
| 122 | #define CBAR_KEY (0X000000CB) |
| 123 | if (c->x86_model==9 || c->x86_model == 10) { |
| 124 | if (inl (CBAR) & CBAR_ENB) |
| 125 | outl (0 | CBAR_KEY, CBAR); |
| 126 | } |
| 127 | break; |
| 128 | case 5: |
| 129 | if( c->x86_model < 6 ) |
| 130 | { |
| 131 | /* Based on AMD doc 20734R - June 2000 */ |
| 132 | if ( c->x86_model == 0 ) { |
| 133 | clear_bit(X86_FEATURE_APIC, c->x86_capability); |
| 134 | set_bit(X86_FEATURE_PGE, c->x86_capability); |
| 135 | } |
| 136 | break; |
| 137 | } |
| 138 | |
| 139 | if ( c->x86_model == 6 && c->x86_mask == 1 ) { |
| 140 | const int K6_BUG_LOOP = 1000000; |
| 141 | int n; |
| 142 | void (*f_vide)(void); |
| 143 | unsigned long d, d2; |
| 144 | |
| 145 | printk(KERN_INFO "AMD K6 stepping B detected - "); |
| 146 | |
| 147 | /* |
| 148 | * It looks like AMD fixed the 2.6.2 bug and improved indirect |
| 149 | * calls at the same time. |
| 150 | */ |
| 151 | |
| 152 | n = K6_BUG_LOOP; |
| 153 | f_vide = vide; |
| 154 | rdtscl(d); |
| 155 | while (n--) |
| 156 | f_vide(); |
| 157 | rdtscl(d2); |
| 158 | d = d2-d; |
Dave Jones | 6df0532 | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 159 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 160 | if (d > 20*K6_BUG_LOOP) |
| 161 | printk("system stability may be impaired when more than 32 MB are used.\n"); |
| 162 | else |
| 163 | printk("probably OK (after B9730xxxx).\n"); |
| 164 | printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); |
| 165 | } |
| 166 | |
| 167 | /* K6 with old style WHCR */ |
| 168 | if (c->x86_model < 8 || |
| 169 | (c->x86_model== 8 && c->x86_mask < 8)) { |
| 170 | /* We can only write allocate on the low 508Mb */ |
| 171 | if(mbytes>508) |
| 172 | mbytes=508; |
| 173 | |
| 174 | rdmsr(MSR_K6_WHCR, l, h); |
| 175 | if ((l&0x0000FFFF)==0) { |
| 176 | unsigned long flags; |
| 177 | l=(1<<0)|((mbytes/4)<<1); |
| 178 | local_irq_save(flags); |
| 179 | wbinvd(); |
| 180 | wrmsr(MSR_K6_WHCR, l, h); |
| 181 | local_irq_restore(flags); |
| 182 | printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", |
| 183 | mbytes); |
| 184 | } |
| 185 | break; |
| 186 | } |
| 187 | |
| 188 | if ((c->x86_model == 8 && c->x86_mask >7) || |
| 189 | c->x86_model == 9 || c->x86_model == 13) { |
| 190 | /* The more serious chips .. */ |
| 191 | |
| 192 | if(mbytes>4092) |
| 193 | mbytes=4092; |
| 194 | |
| 195 | rdmsr(MSR_K6_WHCR, l, h); |
| 196 | if ((l&0xFFFF0000)==0) { |
| 197 | unsigned long flags; |
| 198 | l=((mbytes>>2)<<22)|(1<<16); |
| 199 | local_irq_save(flags); |
| 200 | wbinvd(); |
| 201 | wrmsr(MSR_K6_WHCR, l, h); |
| 202 | local_irq_restore(flags); |
| 203 | printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", |
| 204 | mbytes); |
| 205 | } |
| 206 | |
| 207 | /* Set MTRR capability flag if appropriate */ |
| 208 | if (c->x86_model == 13 || c->x86_model == 9 || |
| 209 | (c->x86_model == 8 && c->x86_mask >= 8)) |
| 210 | set_bit(X86_FEATURE_K6_MTRR, c->x86_capability); |
| 211 | break; |
| 212 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 213 | |
Jordan Crouse | f90b811 | 2006-01-06 00:12:14 -0800 | [diff] [blame] | 214 | if (c->x86_model == 10) { |
| 215 | /* AMD Geode LX is model 10 */ |
| 216 | /* placeholder for any needed mods */ |
| 217 | break; |
| 218 | } |
| 219 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 220 | case 6: /* An Athlon/Duron */ |
| 221 | |
| 222 | /* Bit 15 of Athlon specific MSR 15, needs to be 0 |
| 223 | * to enable SSE on Palomino/Morgan/Barton CPU's. |
| 224 | * If the BIOS didn't enable it already, enable it here. |
| 225 | */ |
| 226 | if (c->x86_model >= 6 && c->x86_model <= 10) { |
| 227 | if (!cpu_has(c, X86_FEATURE_XMM)) { |
| 228 | printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); |
| 229 | rdmsr(MSR_K7_HWCR, l, h); |
| 230 | l &= ~0x00008000; |
| 231 | wrmsr(MSR_K7_HWCR, l, h); |
| 232 | set_bit(X86_FEATURE_XMM, c->x86_capability); |
| 233 | } |
| 234 | } |
| 235 | |
| 236 | /* It's been determined by AMD that Athlons since model 8 stepping 1 |
| 237 | * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx |
| 238 | * As per AMD technical note 27212 0.2 |
| 239 | */ |
| 240 | if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 8)) { |
| 241 | rdmsr(MSR_K7_CLK_CTL, l, h); |
| 242 | if ((l & 0xfff00000) != 0x20000000) { |
| 243 | printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l, |
| 244 | ((l & 0x000fffff)|0x20000000)); |
| 245 | wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); |
| 246 | } |
| 247 | } |
| 248 | break; |
| 249 | } |
| 250 | |
| 251 | switch (c->x86) { |
| 252 | case 15: |
Andi Kleen | 398cf2a | 2007-07-22 11:12:35 +0200 | [diff] [blame] | 253 | /* Use K8 tuning for Fam10h and Fam11h */ |
| 254 | case 0x10: |
| 255 | case 0x11: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 256 | set_bit(X86_FEATURE_K8, c->x86_capability); |
| 257 | break; |
| 258 | case 6: |
| 259 | set_bit(X86_FEATURE_K7, c->x86_capability); |
| 260 | break; |
| 261 | } |
Andi Kleen | 18bd057 | 2006-04-20 02:36:45 +0200 | [diff] [blame] | 262 | if (c->x86 >= 6) |
| 263 | set_bit(X86_FEATURE_FXSAVE_LEAK, c->x86_capability); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 264 | |
| 265 | display_cacheinfo(c); |
Andi Kleen | 3dd9d51 | 2005-04-16 15:25:15 -0700 | [diff] [blame] | 266 | |
| 267 | if (cpuid_eax(0x80000000) >= 0x80000008) { |
Siddha, Suresh B | 94605ef | 2005-11-05 17:25:54 +0100 | [diff] [blame] | 268 | c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1; |
Andi Kleen | 3dd9d51 | 2005-04-16 15:25:15 -0700 | [diff] [blame] | 269 | } |
| 270 | |
Andi Kleen | b41e293 | 2005-05-20 14:27:55 -0700 | [diff] [blame] | 271 | #ifdef CONFIG_X86_HT |
Andi Kleen | 6351864 | 2005-04-16 15:25:16 -0700 | [diff] [blame] | 272 | /* |
Andi Kleen | faee9a5 | 2006-06-26 13:56:10 +0200 | [diff] [blame] | 273 | * On a AMD multi core setup the lower bits of the APIC id |
Simon Arlott | 27b46d7 | 2007-10-20 01:13:56 +0200 | [diff] [blame] | 274 | * distinguish the cores. |
Andi Kleen | 6351864 | 2005-04-16 15:25:16 -0700 | [diff] [blame] | 275 | */ |
Siddha, Suresh B | 94605ef | 2005-11-05 17:25:54 +0100 | [diff] [blame] | 276 | if (c->x86_max_cores > 1) { |
Andi Kleen | a158608 | 2005-05-16 21:53:21 -0700 | [diff] [blame] | 277 | int cpu = smp_processor_id(); |
Andi Kleen | faee9a5 | 2006-06-26 13:56:10 +0200 | [diff] [blame] | 278 | unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf; |
| 279 | |
| 280 | if (bits == 0) { |
| 281 | while ((1 << bits) < c->x86_max_cores) |
| 282 | bits++; |
| 283 | } |
Rohit Seth | 4b89aff | 2006-06-27 02:53:46 -0700 | [diff] [blame] | 284 | c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1); |
| 285 | c->phys_proc_id >>= bits; |
Andi Kleen | 6351864 | 2005-04-16 15:25:16 -0700 | [diff] [blame] | 286 | printk(KERN_INFO "CPU %d(%d) -> Core %d\n", |
Rohit Seth | 4b89aff | 2006-06-27 02:53:46 -0700 | [diff] [blame] | 287 | cpu, c->x86_max_cores, c->cpu_core_id); |
Andi Kleen | 6351864 | 2005-04-16 15:25:16 -0700 | [diff] [blame] | 288 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 289 | #endif |
Andi Kleen | 39b3a79 | 2006-01-11 22:42:45 +0100 | [diff] [blame] | 290 | |
Andi Kleen | 67cddd9 | 2007-07-21 17:10:03 +0200 | [diff] [blame] | 291 | if (cpuid_eax(0x80000000) >= 0x80000006) { |
| 292 | if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000)) |
| 293 | num_cache_leaves = 4; |
| 294 | else |
| 295 | num_cache_leaves = 3; |
| 296 | } |
Andi Kleen | 3556ddf | 2007-04-02 12:14:12 +0200 | [diff] [blame] | 297 | |
Andi Kleen | d3f7eae | 2007-08-10 22:31:07 +0200 | [diff] [blame] | 298 | #ifdef CONFIG_X86_LOCAL_APIC |
Andi Kleen | 3556ddf | 2007-04-02 12:14:12 +0200 | [diff] [blame] | 299 | if (amd_apic_timer_broken()) |
Andi Kleen | d3f7eae | 2007-08-10 22:31:07 +0200 | [diff] [blame] | 300 | local_apic_timer_disabled = 1; |
| 301 | #endif |
Andi Kleen | f039b75 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 302 | |
| 303 | if (c->x86 == 0x10 && !force_mwait) |
| 304 | clear_bit(X86_FEATURE_MWAIT, c->x86_capability); |
Andi Kleen | c12ceb7 | 2007-05-21 14:31:47 +0200 | [diff] [blame] | 305 | |
| 306 | /* K6s reports MCEs but don't actually have all the MSRs */ |
| 307 | if (c->x86 < 6) |
| 308 | clear_bit(X86_FEATURE_MCE, c->x86_capability); |
Andi Kleen | de42186 | 2008-01-30 13:32:37 +0100 | [diff] [blame] | 309 | |
| 310 | if (cpu_has_xmm) |
| 311 | set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 312 | } |
| 313 | |
Magnus Damm | e9dff0e | 2006-09-26 10:52:36 +0200 | [diff] [blame] | 314 | static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 315 | { |
| 316 | /* AMD errata T13 (order #21922) */ |
| 317 | if ((c->x86 == 6)) { |
| 318 | if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */ |
| 319 | size = 64; |
| 320 | if (c->x86_model == 4 && |
| 321 | (c->x86_mask==0 || c->x86_mask==1)) /* Tbird rev A1/A2 */ |
| 322 | size = 256; |
| 323 | } |
| 324 | return size; |
| 325 | } |
| 326 | |
Magnus Damm | 9541493 | 2006-09-26 10:52:36 +0200 | [diff] [blame] | 327 | static struct cpu_dev amd_cpu_dev __cpuinitdata = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 328 | .c_vendor = "AMD", |
| 329 | .c_ident = { "AuthenticAMD" }, |
| 330 | .c_models = { |
| 331 | { .vendor = X86_VENDOR_AMD, .family = 4, .model_names = |
| 332 | { |
| 333 | [3] = "486 DX/2", |
| 334 | [7] = "486 DX/2-WB", |
| 335 | [8] = "486 DX/4", |
| 336 | [9] = "486 DX/4-WB", |
| 337 | [14] = "Am5x86-WT", |
| 338 | [15] = "Am5x86-WB" |
| 339 | } |
| 340 | }, |
| 341 | }, |
| 342 | .c_init = init_amd, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 343 | .c_size_cache = amd_size_cache, |
| 344 | }; |
| 345 | |
| 346 | int __init amd_init_cpu(void) |
| 347 | { |
| 348 | cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev; |
| 349 | return 0; |
| 350 | } |