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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 2a1ac5ba9080d4e86e597fb287f6992a9511b90c / . / drivers / clk / mediatek / clk-mt8195-vpp0.c
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Chun-Jie Chenf5bf0c12021-09-14 10:16:29 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
2//
3// Copyright (c) 2021 MediaTek Inc.
4// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
5
6#include "clk-gate.h"
7#include "clk-mtk.h"
8
9#include <dt-bindings/clock/mt8195-clk.h>
10#include <linux/clk-provider.h>
11#include <linux/platform_device.h>
12
13static const struct mtk_gate_regs vpp0_0_cg_regs = {
14 .set_ofs = 0x24,
15 .clr_ofs = 0x28,
16 .sta_ofs = 0x20,
17};
18
19static const struct mtk_gate_regs vpp0_1_cg_regs = {
20 .set_ofs = 0x30,
21 .clr_ofs = 0x34,
22 .sta_ofs = 0x2c,
23};
24
25static const struct mtk_gate_regs vpp0_2_cg_regs = {
26 .set_ofs = 0x3c,
27 .clr_ofs = 0x40,
28 .sta_ofs = 0x38,
29};
30
31#define GATE_VPP0_0(_id, _name, _parent, _shift) \
32 GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
33
34#define GATE_VPP0_1(_id, _name, _parent, _shift) \
35 GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
36
37#define GATE_VPP0_2(_id, _name, _parent, _shift) \
38 GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
39
40static const struct mtk_gate vpp0_clks[] = {
41 /* VPP0_0 */
42 GATE_VPP0_0(CLK_VPP0_MDP_FG, "vpp0_mdp_fg", "top_vpp", 1),
43 GATE_VPP0_0(CLK_VPP0_STITCH, "vpp0_stitch", "top_vpp", 2),
44 GATE_VPP0_0(CLK_VPP0_PADDING, "vpp0_padding", "top_vpp", 7),
45 GATE_VPP0_0(CLK_VPP0_MDP_TCC, "vpp0_mdp_tcc", "top_vpp", 8),
46 GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx", "top_vpp", 10),
47 GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx", "top_vpp", 11),
48 GATE_VPP0_0(CLK_VPP0_MUTEX, "vpp0_mutex", "top_vpp", 13),
49 GATE_VPP0_0(CLK_VPP0_VPP02VPP1_RELAY, "vpp0_vpp02vpp1_relay", "top_vpp", 14),
50 GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC, "vpp0_vpp12vpp0_async", "top_vpp", 15),
51 GATE_VPP0_0(CLK_VPP0_MMSYSRAM_TOP, "vpp0_mmsysram_top", "top_vpp", 16),
52 GATE_VPP0_0(CLK_VPP0_MDP_AAL, "vpp0_mdp_aal", "top_vpp", 17),
53 GATE_VPP0_0(CLK_VPP0_MDP_RSZ, "vpp0_mdp_rsz", "top_vpp", 18),
54 /* VPP0_1 */
55 GATE_VPP0_1(CLK_VPP0_SMI_COMMON, "vpp0_smi_common", "top_vpp", 0),
56 GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB0, "vpp0_gals_vdo0_larb0", "top_vpp", 1),
57 GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB1, "vpp0_gals_vdo0_larb1", "top_vpp", 2),
58 GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS, "vpp0_gals_vencsys", "top_vpp", 3),
59 GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_CORE1, "vpp0_gals_vencsys_core1", "top_vpp", 4),
60 GATE_VPP0_1(CLK_VPP0_GALS_INFRA, "vpp0_gals_infra", "top_vpp", 5),
61 GATE_VPP0_1(CLK_VPP0_GALS_CAMSYS, "vpp0_gals_camsys", "top_vpp", 6),
62 GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB5, "vpp0_gals_vpp1_larb5", "top_vpp", 7),
63 GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB6, "vpp0_gals_vpp1_larb6", "top_vpp", 8),
64 GATE_VPP0_1(CLK_VPP0_SMI_REORDER, "vpp0_smi_reorder", "top_vpp", 9),
65 GATE_VPP0_1(CLK_VPP0_SMI_IOMMU, "vpp0_smi_iommu", "top_vpp", 10),
66 GATE_VPP0_1(CLK_VPP0_GALS_IMGSYS_CAMSYS, "vpp0_gals_imgsys_camsys", "top_vpp", 11),
67 GATE_VPP0_1(CLK_VPP0_MDP_RDMA, "vpp0_mdp_rdma", "top_vpp", 12),
68 GATE_VPP0_1(CLK_VPP0_MDP_WROT, "vpp0_mdp_wrot", "top_vpp", 13),
69 GATE_VPP0_1(CLK_VPP0_GALS_EMI0_EMI1, "vpp0_gals_emi0_emi1", "top_vpp", 16),
70 GATE_VPP0_1(CLK_VPP0_SMI_SUB_COMMON_REORDER, "vpp0_smi_sub_common_reorder", "top_vpp", 17),
71 GATE_VPP0_1(CLK_VPP0_SMI_RSI, "vpp0_smi_rsi", "top_vpp", 18),
72 GATE_VPP0_1(CLK_VPP0_SMI_COMMON_LARB4, "vpp0_smi_common_larb4", "top_vpp", 19),
73 GATE_VPP0_1(CLK_VPP0_GALS_VDEC_VDEC_CORE1, "vpp0_gals_vdec_vdec_core1", "top_vpp", 20),
74 GATE_VPP0_1(CLK_VPP0_GALS_VPP1_WPE, "vpp0_gals_vpp1_wpe", "top_vpp", 21),
75 GATE_VPP0_1(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1, "vpp0_gals_vdo0_vdo1_vencsys_core1",
76 "top_vpp", 22),
77 GATE_VPP0_1(CLK_VPP0_FAKE_ENG, "vpp0_fake_eng", "top_vpp", 23),
78 GATE_VPP0_1(CLK_VPP0_MDP_HDR, "vpp0_mdp_hdr", "top_vpp", 24),
79 GATE_VPP0_1(CLK_VPP0_MDP_TDSHP, "vpp0_mdp_tdshp", "top_vpp", 25),
80 GATE_VPP0_1(CLK_VPP0_MDP_COLOR, "vpp0_mdp_color", "top_vpp", 26),
81 GATE_VPP0_1(CLK_VPP0_MDP_OVL, "vpp0_mdp_ovl", "top_vpp", 27),
82 /* VPP0_2 */
83 GATE_VPP0_2(CLK_VPP0_WARP0_RELAY, "vpp0_warp0_relay", "top_wpe_vpp", 0),
84 GATE_VPP0_2(CLK_VPP0_WARP0_MDP_DL_ASYNC, "vpp0_warp0_mdp_dl_async", "top_wpe_vpp", 1),
85 GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay", "top_wpe_vpp", 2),
86 GATE_VPP0_2(CLK_VPP0_WARP1_MDP_DL_ASYNC, "vpp0_warp1_mdp_dl_async", "top_wpe_vpp", 3),
87};
88
89static const struct mtk_clk_desc vpp0_desc = {
90 .clks = vpp0_clks,
91 .num_clks = ARRAY_SIZE(vpp0_clks),
92};
93
94static const struct of_device_id of_match_clk_mt8195_vpp0[] = {
95 {
96 .compatible = "mediatek,mt8195-vppsys0",
97 .data = &vpp0_desc,
98 }, {
99 /* sentinel */
100 }
101};
102
103static struct platform_driver clk_mt8195_vpp0_drv = {
104 .probe = mtk_clk_simple_probe,
105 .driver = {
106 .name = "clk-mt8195-vpp0",
107 .of_match_table = of_match_clk_mt8195_vpp0,
108 },
109};
110builtin_platform_driver(clk_mt8195_vpp0_drv);