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Leela Krishna Amudala5a213a52012-08-08 09:44:49 +09001/* include/video/samsung_fimd.h
Ben Dooks8f995cc2008-11-19 15:41:30 +00002 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
Leela Krishna Amudala5a213a52012-08-08 09:44:49 +09008 * S3C Platform - new-style fimd and framebuffer register definitions
Ben Dooks8f995cc2008-11-19 15:41:30 +00009 *
Leela Krishna Amudala5a213a52012-08-08 09:44:49 +090010 * This is the register set for the fimd and new style framebuffer interface
Jingoo Hanfe6863c2013-02-21 16:42:33 -080011 * found from the S3C2443 onwards into the S3C2416, S3C2450, the
12 * S3C64XX series such as the S3C6400 and S3C6410, and EXYNOS series.
Ben Dooks8f995cc2008-11-19 15:41:30 +000013 *
Ben Dooks8f995cc2008-11-19 15:41:30 +000014 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17*/
18
Ben Dooks8f995cc2008-11-19 15:41:30 +000019/* VIDCON0 */
20
Jingoo Hanfe6863c2013-02-21 16:42:33 -080021#define VIDCON0 0x00
YoungJun Cho3854fab2014-07-17 18:01:21 +090022#define VIDCON0_DSI_EN (1 << 30)
Ben Dooks8f995cc2008-11-19 15:41:30 +000023#define VIDCON0_INTERLACE (1 << 29)
Jingoo Hanb4da9c92012-09-25 16:19:03 +090024#define VIDCON0_VIDOUT_MASK (0x7 << 26)
Jingoo Hanfe6863c2013-02-21 16:42:33 -080025#define VIDCON0_VIDOUT_SHIFT 26
Ben Dooks8f995cc2008-11-19 15:41:30 +000026#define VIDCON0_VIDOUT_RGB (0x0 << 26)
27#define VIDCON0_VIDOUT_TV (0x1 << 26)
28#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
29#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
Jingoo Hanb4da9c92012-09-25 16:19:03 +090030#define VIDCON0_VIDOUT_WB_RGB (0x4 << 26)
31#define VIDCON0_VIDOUT_WB_I80_LDI0 (0x6 << 26)
32#define VIDCON0_VIDOUT_WB_I80_LDI1 (0x7 << 26)
Ben Dooks8f995cc2008-11-19 15:41:30 +000033
34#define VIDCON0_L1_DATA_MASK (0x7 << 23)
Jingoo Hanfe6863c2013-02-21 16:42:33 -080035#define VIDCON0_L1_DATA_SHIFT 23
Ben Dooks8f995cc2008-11-19 15:41:30 +000036#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
37#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
38#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
39#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
40#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
41#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
42
43#define VIDCON0_L0_DATA_MASK (0x7 << 20)
Jingoo Hanfe6863c2013-02-21 16:42:33 -080044#define VIDCON0_L0_DATA_SHIFT 20
Ben Dooks8f995cc2008-11-19 15:41:30 +000045#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
46#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
47#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
48#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
49#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
50#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
51
52#define VIDCON0_PNRMODE_MASK (0x3 << 17)
Jingoo Hanfe6863c2013-02-21 16:42:33 -080053#define VIDCON0_PNRMODE_SHIFT 17
Ben Dooks8f995cc2008-11-19 15:41:30 +000054#define VIDCON0_PNRMODE_RGB (0x0 << 17)
55#define VIDCON0_PNRMODE_BGR (0x1 << 17)
56#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
57#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
58
59#define VIDCON0_CLKVALUP (1 << 16)
60#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
Jingoo Hanfe6863c2013-02-21 16:42:33 -080061#define VIDCON0_CLKVAL_F_SHIFT 6
62#define VIDCON0_CLKVAL_F_LIMIT 0xff
Ben Dooks8f995cc2008-11-19 15:41:30 +000063#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
64#define VIDCON0_VLCKFREE (1 << 5)
65#define VIDCON0_CLKDIR (1 << 4)
66
67#define VIDCON0_CLKSEL_MASK (0x3 << 2)
Jingoo Hanfe6863c2013-02-21 16:42:33 -080068#define VIDCON0_CLKSEL_SHIFT 2
Ben Dooks8f995cc2008-11-19 15:41:30 +000069#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
70#define VIDCON0_CLKSEL_LCD (0x1 << 2)
71#define VIDCON0_CLKSEL_27M (0x3 << 2)
72
73#define VIDCON0_ENVID (1 << 1)
74#define VIDCON0_ENVID_F (1 << 0)
75
Jingoo Hanfe6863c2013-02-21 16:42:33 -080076#define VIDCON1 0x04
Ben Dooks8f995cc2008-11-19 15:41:30 +000077#define VIDCON1_LINECNT_MASK (0x7ff << 16)
Jingoo Hanfe6863c2013-02-21 16:42:33 -080078#define VIDCON1_LINECNT_SHIFT 16
Ben Dooks8f995cc2008-11-19 15:41:30 +000079#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
Jingoo Han31dd94f2012-09-25 17:30:36 +090080#define VIDCON1_FSTATUS_EVEN (1 << 15)
Ben Dooks8f995cc2008-11-19 15:41:30 +000081#define VIDCON1_VSTATUS_MASK (0x3 << 13)
Jingoo Hanfe6863c2013-02-21 16:42:33 -080082#define VIDCON1_VSTATUS_SHIFT 13
Ben Dooks8f995cc2008-11-19 15:41:30 +000083#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
84#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
85#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
Tomasz Figa678268e2013-02-21 16:42:36 -080086#define VIDCON1_VSTATUS_FRONTPORCH (0x3 << 13)
Jingoo Hand8b97db2012-01-27 14:47:55 +090087#define VIDCON1_VCLK_MASK (0x3 << 9)
88#define VIDCON1_VCLK_HOLD (0x0 << 9)
89#define VIDCON1_VCLK_RUN (0x1 << 9)
Ben Dooks8f995cc2008-11-19 15:41:30 +000090
91#define VIDCON1_INV_VCLK (1 << 7)
92#define VIDCON1_INV_HSYNC (1 << 6)
93#define VIDCON1_INV_VSYNC (1 << 5)
94#define VIDCON1_INV_VDEN (1 << 4)
95
96/* VIDCON2 */
97
Jingoo Hanfe6863c2013-02-21 16:42:33 -080098#define VIDCON2 0x08
Ben Dooks8f995cc2008-11-19 15:41:30 +000099#define VIDCON2_EN601 (1 << 23)
100#define VIDCON2_TVFMTSEL_SW (1 << 14)
101
102#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800103#define VIDCON2_TVFMTSEL1_SHIFT 12
Ben Dooks8f995cc2008-11-19 15:41:30 +0000104#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
105#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
106#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
107
108#define VIDCON2_ORGYCbCr (1 << 8)
109#define VIDCON2_YUVORDCrCb (1 << 7)
110
Kukjin Kimf86e0ad2014-07-02 07:53:17 +0900111/* PRTCON (S3C6410)
Pawel Osciak067b2262010-08-10 18:02:38 -0700112 * Might not be present in the S3C6410 documentation,
113 * but tests prove it's there almost for sure; shouldn't hurt in any case.
114 */
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800115#define PRTCON 0x0c
Pawel Osciak067b2262010-08-10 18:02:38 -0700116#define PRTCON_PROTECT (1 << 11)
117
Ben Dooks8f995cc2008-11-19 15:41:30 +0000118/* VIDTCON0 */
119
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800120#define VIDTCON0 0x10
Ben Dooks8f995cc2008-11-19 15:41:30 +0000121#define VIDTCON0_VBPDE_MASK (0xff << 24)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800122#define VIDTCON0_VBPDE_SHIFT 24
123#define VIDTCON0_VBPDE_LIMIT 0xff
Ben Dooks8f995cc2008-11-19 15:41:30 +0000124#define VIDTCON0_VBPDE(_x) ((_x) << 24)
125
126#define VIDTCON0_VBPD_MASK (0xff << 16)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800127#define VIDTCON0_VBPD_SHIFT 16
128#define VIDTCON0_VBPD_LIMIT 0xff
Ben Dooks8f995cc2008-11-19 15:41:30 +0000129#define VIDTCON0_VBPD(_x) ((_x) << 16)
130
131#define VIDTCON0_VFPD_MASK (0xff << 8)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800132#define VIDTCON0_VFPD_SHIFT 8
133#define VIDTCON0_VFPD_LIMIT 0xff
Ben Dooks8f995cc2008-11-19 15:41:30 +0000134#define VIDTCON0_VFPD(_x) ((_x) << 8)
135
136#define VIDTCON0_VSPW_MASK (0xff << 0)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800137#define VIDTCON0_VSPW_SHIFT 0
138#define VIDTCON0_VSPW_LIMIT 0xff
Ben Dooks8f995cc2008-11-19 15:41:30 +0000139#define VIDTCON0_VSPW(_x) ((_x) << 0)
140
141/* VIDTCON1 */
142
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800143#define VIDTCON1 0x14
Ben Dooks8f995cc2008-11-19 15:41:30 +0000144#define VIDTCON1_VFPDE_MASK (0xff << 24)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800145#define VIDTCON1_VFPDE_SHIFT 24
146#define VIDTCON1_VFPDE_LIMIT 0xff
Ben Dooks8f995cc2008-11-19 15:41:30 +0000147#define VIDTCON1_VFPDE(_x) ((_x) << 24)
148
149#define VIDTCON1_HBPD_MASK (0xff << 16)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800150#define VIDTCON1_HBPD_SHIFT 16
151#define VIDTCON1_HBPD_LIMIT 0xff
Ben Dooks8f995cc2008-11-19 15:41:30 +0000152#define VIDTCON1_HBPD(_x) ((_x) << 16)
153
154#define VIDTCON1_HFPD_MASK (0xff << 8)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800155#define VIDTCON1_HFPD_SHIFT 8
156#define VIDTCON1_HFPD_LIMIT 0xff
Ben Dooks8f995cc2008-11-19 15:41:30 +0000157#define VIDTCON1_HFPD(_x) ((_x) << 8)
158
159#define VIDTCON1_HSPW_MASK (0xff << 0)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800160#define VIDTCON1_HSPW_SHIFT 0
161#define VIDTCON1_HSPW_LIMIT 0xff
Ben Dooks8f995cc2008-11-19 15:41:30 +0000162#define VIDTCON1_HSPW(_x) ((_x) << 0)
163
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800164#define VIDTCON2 0x18
Jingoo Han5c447782012-03-06 15:53:41 +0900165#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000166#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800167#define VIDTCON2_LINEVAL_SHIFT 11
168#define VIDTCON2_LINEVAL_LIMIT 0x7ff
Jingoo Han5c447782012-03-06 15:53:41 +0900169#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000170
Jingoo Han5c447782012-03-06 15:53:41 +0900171#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000172#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800173#define VIDTCON2_HOZVAL_SHIFT 0
174#define VIDTCON2_HOZVAL_LIMIT 0x7ff
Jingoo Han5c447782012-03-06 15:53:41 +0900175#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000176
177/* WINCONx */
178
Jingoo Han36ff8d52012-09-25 15:37:45 +0900179#define WINCON(_win) (0x20 + ((_win) * 4))
Jingoo Han90dd0b02013-02-21 16:42:34 -0800180#define WINCONx_CSCCON_EQ601 (0x0 << 28)
181#define WINCONx_CSCCON_EQ709 (0x1 << 28)
Jingoo Han36ff8d52012-09-25 15:37:45 +0900182#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800183#define WINCONx_CSCWIDTH_SHIFT 26
Jingoo Han36ff8d52012-09-25 15:37:45 +0900184#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
185#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
186#define WINCONx_ENLOCAL (1 << 22)
187#define WINCONx_BUFSTATUS (1 << 21)
188#define WINCONx_BUFSEL (1 << 20)
189#define WINCONx_BUFAUTOEN (1 << 19)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000190#define WINCONx_BITSWP (1 << 18)
191#define WINCONx_BYTSWP (1 << 17)
192#define WINCONx_HAWSWP (1 << 16)
InKi Daedc8498c2010-08-10 18:02:32 -0700193#define WINCONx_WSWP (1 << 15)
Jingoo Han36ff8d52012-09-25 15:37:45 +0900194#define WINCONx_YCbCr (1 << 13)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000195#define WINCONx_BURSTLEN_MASK (0x3 << 9)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800196#define WINCONx_BURSTLEN_SHIFT 9
Ben Dooks8f995cc2008-11-19 15:41:30 +0000197#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
198#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
199#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000200#define WINCONx_ENWIN (1 << 0)
Christoph Manszewski3b5129b2018-10-25 17:23:50 +0200201#define WINCONx_BLEND_MODE_MASK (0xc2)
Jingoo Han36ff8d52012-09-25 15:37:45 +0900202
Ben Dooks8f995cc2008-11-19 15:41:30 +0000203#define WINCON0_BPPMODE_MASK (0xf << 2)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800204#define WINCON0_BPPMODE_SHIFT 2
Ben Dooks8f995cc2008-11-19 15:41:30 +0000205#define WINCON0_BPPMODE_1BPP (0x0 << 2)
206#define WINCON0_BPPMODE_2BPP (0x1 << 2)
207#define WINCON0_BPPMODE_4BPP (0x2 << 2)
208#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
209#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
210#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
211#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
212#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
213
Jingoo Han36ff8d52012-09-25 15:37:45 +0900214#define WINCON1_LOCALSEL_CAMIF (1 << 23)
Christoph Manszewski6f8ee5c2018-10-25 17:23:49 +0200215#define WINCON1_ALPHA_MUL (1 << 7)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000216#define WINCON1_BLD_PIX (1 << 6)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000217#define WINCON1_BPPMODE_MASK (0xf << 2)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800218#define WINCON1_BPPMODE_SHIFT 2
Ben Dooks8f995cc2008-11-19 15:41:30 +0000219#define WINCON1_BPPMODE_1BPP (0x0 << 2)
220#define WINCON1_BPPMODE_2BPP (0x1 << 2)
221#define WINCON1_BPPMODE_4BPP (0x2 << 2)
222#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
223#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
224#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
225#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
226#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
227#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
228#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
229#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
230#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
231#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
232#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
233#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
Jingoo Han36ff8d52012-09-25 15:37:45 +0900234#define WINCON1_ALPHA_SEL (1 << 1)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000235
Pawel Osciakf5ec5462010-08-10 18:02:40 -0700236/* S5PV210 */
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800237#define SHADOWCON 0x34
Pawel Osciakf5ec5462010-08-10 18:02:40 -0700238#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
Pawel Osciak04ab9ef2010-08-10 18:02:43 -0700239/* DMA channels (all windows) */
240#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))
241/* Local input channels (windows 0-2) */
242#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
Ben Dooks8f995cc2008-11-19 15:41:30 +0000243
Jingoo Han99a2c612012-09-25 16:43:16 +0900244/* VIDOSDx */
245
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800246#define VIDOSD_BASE 0x40
Jingoo Han5c447782012-03-06 15:53:41 +0900247#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000248#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800249#define VIDOSDxA_TOPLEFT_X_SHIFT 11
250#define VIDOSDxA_TOPLEFT_X_LIMIT 0x7ff
Jingoo Han5c447782012-03-06 15:53:41 +0900251#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000252
Jingoo Han5c447782012-03-06 15:53:41 +0900253#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000254#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800255#define VIDOSDxA_TOPLEFT_Y_SHIFT 0
256#define VIDOSDxA_TOPLEFT_Y_LIMIT 0x7ff
Jingoo Han5c447782012-03-06 15:53:41 +0900257#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000258
Jingoo Han5c447782012-03-06 15:53:41 +0900259#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000260#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800261#define VIDOSDxB_BOTRIGHT_X_SHIFT 11
262#define VIDOSDxB_BOTRIGHT_X_LIMIT 0x7ff
Jingoo Han5c447782012-03-06 15:53:41 +0900263#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000264
Jingoo Han5c447782012-03-06 15:53:41 +0900265#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000266#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800267#define VIDOSDxB_BOTRIGHT_Y_SHIFT 0
268#define VIDOSDxB_BOTRIGHT_Y_LIMIT 0x7ff
Jingoo Han5c447782012-03-06 15:53:41 +0900269#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000270
271/* For VIDOSD[1..4]C */
272#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
273#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800274#define VIDISD14C_ALPHA0_G_SHIFT 16
275#define VIDISD14C_ALPHA0_G_LIMIT 0xf
Ben Dooks8f995cc2008-11-19 15:41:30 +0000276#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
277#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800278#define VIDISD14C_ALPHA0_B_SHIFT 12
279#define VIDISD14C_ALPHA0_B_LIMIT 0xf
Ben Dooks8f995cc2008-11-19 15:41:30 +0000280#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
281#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800282#define VIDISD14C_ALPHA1_R_SHIFT 8
283#define VIDISD14C_ALPHA1_R_LIMIT 0xf
Ben Dooks8f995cc2008-11-19 15:41:30 +0000284#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
285#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800286#define VIDISD14C_ALPHA1_G_SHIFT 4
287#define VIDISD14C_ALPHA1_G_LIMIT 0xf
Ben Dooks8f995cc2008-11-19 15:41:30 +0000288#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
289#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800290#define VIDISD14C_ALPHA1_B_SHIFT 0
291#define VIDISD14C_ALPHA1_B_LIMIT 0xf
Ben Dooks8f995cc2008-11-19 15:41:30 +0000292#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
293
Gustavo Padovan453b44a2015-04-01 13:02:05 -0300294#define VIDW_ALPHA 0x021c
295#define VIDW_ALPHA_R(_x) ((_x) << 16)
296#define VIDW_ALPHA_G(_x) ((_x) << 8)
297#define VIDW_ALPHA_B(_x) ((_x) << 0)
298
Ben Dooks8f995cc2008-11-19 15:41:30 +0000299/* Video buffer addresses */
300#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
Gustavo Padovan44205082015-08-15 13:26:15 -0300301#define VIDW_BUF_START_S(_buff) (0x40A0 + ((_buff) * 8))
Ben Dooks8f995cc2008-11-19 15:41:30 +0000302#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
303#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
304#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
305#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
306
Jingoo Han5c447782012-03-06 15:53:41 +0900307#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000308#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800309#define VIDW_BUF_SIZE_OFFSET_SHIFT 13
310#define VIDW_BUF_SIZE_OFFSET_LIMIT 0x1fff
Jingoo Han5c447782012-03-06 15:53:41 +0900311#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000312
Jingoo Han5c447782012-03-06 15:53:41 +0900313#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000314#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800315#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT 0
316#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT 0x1fff
Jingoo Han5c447782012-03-06 15:53:41 +0900317#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000318
319/* Interrupt controls and status */
320
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800321#define VIDINTCON0 0x130
Ben Dooks8f995cc2008-11-19 15:41:30 +0000322#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800323#define VIDINTCON0_FIFOINTERVAL_SHIFT 20
324#define VIDINTCON0_FIFOINTERVAL_LIMIT 0x3f
Ben Dooks8f995cc2008-11-19 15:41:30 +0000325#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
326
327#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
328#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
329#define VIDINTCON0_INT_I80IFDONE (1 << 17)
330
331#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800332#define VIDINTCON0_FRAMESEL0_SHIFT 15
Ben Dooks8f995cc2008-11-19 15:41:30 +0000333#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
334#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
335#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
336#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
337
Pawel Osciak9fa424a2010-08-10 18:02:36 -0700338#define VIDINTCON0_FRAMESEL1 (1 << 13)
Pawel Osciakefdc8462010-08-10 18:02:38 -0700339#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)
Pawel Osciak9fa424a2010-08-10 18:02:36 -0700340#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)
341#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)
342#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)
343#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000344
345#define VIDINTCON0_INT_FRAME (1 << 12)
346#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800347#define VIDINTCON0_FIFIOSEL_SHIFT 5
Ben Dooks8f995cc2008-11-19 15:41:30 +0000348#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
349#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
Jingoo Han60eb8d82012-09-25 16:55:18 +0900350#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
351#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
352#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000353
354#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800355#define VIDINTCON0_FIFOLEVEL_SHIFT 2
Ben Dooks8f995cc2008-11-19 15:41:30 +0000356#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
357#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
358#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
359#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
360#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
361
362#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800363#define VIDINTCON0_INT_FIFO_SHIFT 0
Ben Dooks8f995cc2008-11-19 15:41:30 +0000364#define VIDINTCON0_INT_ENABLE (1 << 0)
365
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800366#define VIDINTCON1 0x134
YoungJun Cho3854fab2014-07-17 18:01:21 +0900367#define VIDINTCON1_INT_I80 (1 << 2)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000368#define VIDINTCON1_INT_FRAME (1 << 1)
369#define VIDINTCON1_INT_FIFO (1 << 0)
370
371/* Window colour-key control registers */
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800372#define WKEYCON 0x140
Ben Dooksc4bb6ff2010-08-10 18:02:34 -0700373
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800374#define WKEYCON0 0x00
375#define WKEYCON1 0x04
Ben Dooks8f995cc2008-11-19 15:41:30 +0000376
377#define WxKEYCON0_KEYBL_EN (1 << 26)
378#define WxKEYCON0_KEYEN_F (1 << 25)
379#define WxKEYCON0_DIRCON (1 << 24)
380#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800381#define WxKEYCON0_COMPKEY_SHIFT 0
382#define WxKEYCON0_COMPKEY_LIMIT 0xffffff
Ben Dooks8f995cc2008-11-19 15:41:30 +0000383#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
384#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800385#define WxKEYCON1_COLVAL_SHIFT 0
386#define WxKEYCON1_COLVAL_LIMIT 0xffffff
Ben Dooks8f995cc2008-11-19 15:41:30 +0000387#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
388
Jingoo Han31dd94f2012-09-25 17:30:36 +0900389/* Dithering control */
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800390#define DITHMODE 0x170
Jingoo Han31dd94f2012-09-25 17:30:36 +0900391#define DITHMODE_R_POS_MASK (0x3 << 5)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800392#define DITHMODE_R_POS_SHIFT 5
Jingoo Han31dd94f2012-09-25 17:30:36 +0900393#define DITHMODE_R_POS_8BIT (0x0 << 5)
394#define DITHMODE_R_POS_6BIT (0x1 << 5)
395#define DITHMODE_R_POS_5BIT (0x2 << 5)
396#define DITHMODE_G_POS_MASK (0x3 << 3)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800397#define DITHMODE_G_POS_SHIFT 3
Jingoo Han31dd94f2012-09-25 17:30:36 +0900398#define DITHMODE_G_POS_8BIT (0x0 << 3)
399#define DITHMODE_G_POS_6BIT (0x1 << 3)
400#define DITHMODE_G_POS_5BIT (0x2 << 3)
401#define DITHMODE_B_POS_MASK (0x3 << 1)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800402#define DITHMODE_B_POS_SHIFT 1
Jingoo Han31dd94f2012-09-25 17:30:36 +0900403#define DITHMODE_B_POS_8BIT (0x0 << 1)
404#define DITHMODE_B_POS_6BIT (0x1 << 1)
405#define DITHMODE_B_POS_5BIT (0x2 << 1)
406#define DITHMODE_DITH_EN (1 << 0)
407
Ben Dooks8f995cc2008-11-19 15:41:30 +0000408/* Window blanking (MAP) */
Jingoo Han22254542012-09-25 17:16:52 +0900409#define WINxMAP(_win) (0x180 + ((_win) * 4))
Ben Dooks8f995cc2008-11-19 15:41:30 +0000410#define WINxMAP_MAP (1 << 24)
411#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800412#define WINxMAP_MAP_COLOUR_SHIFT 0
413#define WINxMAP_MAP_COLOUR_LIMIT 0xffffff
Ben Dooks8f995cc2008-11-19 15:41:30 +0000414#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
415
Jingoo Han22254542012-09-25 17:16:52 +0900416/* Winodw palette control */
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800417#define WPALCON 0x1A0
Ben Dooks8f995cc2008-11-19 15:41:30 +0000418#define WPALCON_PAL_UPDATE (1 << 9)
Jingoo Han22254542012-09-25 17:16:52 +0900419#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
420#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
421#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000422#define WPALCON_W1PAL_MASK (0x7 << 3)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800423#define WPALCON_W1PAL_SHIFT 3
Ben Dooks8f995cc2008-11-19 15:41:30 +0000424#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
425#define WPALCON_W1PAL_24BPP (0x1 << 3)
426#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
427#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
428#define WPALCON_W1PAL_18BPP (0x4 << 3)
429#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
430#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
Ben Dooks8f995cc2008-11-19 15:41:30 +0000431#define WPALCON_W0PAL_MASK (0x7 << 0)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800432#define WPALCON_W0PAL_SHIFT 0
Ben Dooks8f995cc2008-11-19 15:41:30 +0000433#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
434#define WPALCON_W0PAL_24BPP (0x1 << 0)
435#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
436#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
437#define WPALCON_W0PAL_18BPP (0x4 << 0)
438#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
439#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
440
Jingoo Hanf7f31e52012-01-27 14:47:22 +0900441/* Blending equation control */
Christoph Manszewski3b5129b2018-10-25 17:23:50 +0200442#define BLENDEQx(_win) (0x244 + ((_win - 1) * 4))
443#define BLENDEQ_ZERO 0x0
444#define BLENDEQ_ONE 0x1
445#define BLENDEQ_ALPHA_A 0x2
446#define BLENDEQ_ONE_MINUS_ALPHA_A 0x3
447#define BLENDEQ_ALPHA0 0x6
448#define BLENDEQ_B_FUNC_F(_x) (_x << 6)
449#define BLENDEQ_A_FUNC_F(_x) (_x << 0)
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800450#define BLENDCON 0x260
Jingoo Hanf7f31e52012-01-27 14:47:22 +0900451#define BLENDCON_NEW_MASK (1 << 0)
452#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
453#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
454
Krzysztof Kozlowski1c363c72015-04-07 22:28:50 +0900455/* Display port clock control */
456#define DP_MIE_CLKCON 0x27c
457#define DP_MIE_CLK_DISABLE 0x0
458#define DP_MIE_CLK_DP_ENABLE 0x2
459#define DP_MIE_CLK_MIE_ENABLE 0x3
460
Leela Krishna Amudala5a213a52012-08-08 09:44:49 +0900461/* Notes on per-window bpp settings
462 *
463 * Value Win0 Win1 Win2 Win3 Win 4
464 * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
465 * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
466 * 0010 4(P) 4(P) 4(P) 4(P) -none-
467 * 0011 8(P) 8(P) -none- -none- -none-
468 * 0100 -none- 8(A232) 8(A232) -none- -none-
469 * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
470 * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
471 * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
472 * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
473 * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
474 * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
475 * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
476 * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
477 * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
478 * 1110 -none- -none- -none- -none- -none-
479 * 1111 -none- -none- -none- -none- -none-
480*/
Leela Krishna Amudalaa44cf752012-08-08 09:44:50 +0900481
482/* FIMD Version 8 register offset definitions */
Jingoo Hanfe6863c2013-02-21 16:42:33 -0800483#define FIMD_V8_VIDTCON0 0x20010
484#define FIMD_V8_VIDTCON1 0x20014
485#define FIMD_V8_VIDTCON2 0x20018
486#define FIMD_V8_VIDTCON3 0x2001C
487#define FIMD_V8_VIDCON1 0x20004