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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 26f71abef580537d978f6299330689f029ee1e6c / . / drivers / phy / qualcomm / phy-qcom-qmp.c
blob: 456a59d8c7d047ae17629107e6360f02d08cd888 [file] [log] [blame]
Manu Gautam3405bd72018-01-16 16:27:12 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/of_address.h>
17#include <linux/phy/phy.h>
18#include <linux/platform_device.h>
19#include <linux/regulator/consumer.h>
20#include <linux/reset.h>
21#include <linux/slab.h>
22
23#include <dt-bindings/phy/phy.h>
24
Manu Gautame2248612018-01-16 16:27:05 +0530[diff] [blame]25#include "phy-qcom-qmp.h"
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]26
27/* QPHY_SW_RESET bit */
28#define SW_RESET BIT(0)
29/* QPHY_POWER_DOWN_CONTROL */
30#define SW_PWRDN BIT(0)
31#define REFCLK_DRV_DSBL BIT(1)
32/* QPHY_START_CONTROL bits */
33#define SERDES_START BIT(0)
34#define PCS_START BIT(1)
35#define PLL_READY_GATE_EN BIT(3)
36/* QPHY_PCS_STATUS bit */
37#define PHYSTATUS BIT(6)
Manivannan Sadhasivambe0ddb52021-04-27 12:24:00 +0530[diff] [blame]38#define PHYSTATUS_4_20 BIT(7)
Bjorn Andersson14ced7e2019-08-05 17:42:56 -0700[diff] [blame]39/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]40#define PCS_READY BIT(0)
41
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]42/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
43/* DP PHY soft reset */
44#define SW_DPPHY_RESET BIT(0)
45/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
46#define SW_DPPHY_RESET_MUX BIT(1)
47/* USB3 PHY soft reset */
48#define SW_USB3PHY_RESET BIT(2)
49/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
50#define SW_USB3PHY_RESET_MUX BIT(3)
51
52/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
53#define USB3_MODE BIT(0) /* enables USB3 mode */
54#define DP_MODE BIT(1) /* enables DP mode */
55
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]56/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
57#define ARCVR_DTCT_EN BIT(0)
58#define ALFPS_DTCT_EN BIT(1)
59#define ARCVR_DTCT_EVENT_SEL BIT(4)
60
61/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
62#define IRQ_CLEAR BIT(0)
63
64/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
65#define RCVR_DETECT BIT(0)
66
67/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
68#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]69
Bjorn Anderssoncd217ee2019-12-20 15:47:15 +0530[diff] [blame]70#define PHY_INIT_COMPLETE_TIMEOUT 10000
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]71#define POWER_DOWN_DELAY_US_MIN 10
72#define POWER_DOWN_DELAY_US_MAX 11
73
74#define MAX_PROP_NAME 32
75
Evan Green5e17b952018-12-10 11:28:23 -0800[diff] [blame]76/* Define the assumed distance between lanes for underspecified device trees. */
77#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
78
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]79struct qmp_phy_init_tbl {
80 unsigned int offset;
81 unsigned int val;
82 /*
83 * register part of layout ?
84 * if yes, then offset gives index in the reg-layout
85 */
Jonathan Marek5dcbc712020-05-23 22:14:13 -0400[diff] [blame]86 bool in_layout;
87 /*
88 * mask of lanes for which this register is written
89 * for cases when second lane needs different values
90 */
91 u8 lane_mask;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]92};
93
94#define QMP_PHY_INIT_CFG(o, v) \
95 { \
96 .offset = o, \
97 .val = v, \
Jonathan Marek5dcbc712020-05-23 22:14:13 -0400[diff] [blame]98 .lane_mask = 0xff, \
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]99 }
100
101#define QMP_PHY_INIT_CFG_L(o, v) \
102 { \
103 .offset = o, \
104 .val = v, \
Jonathan Marek5dcbc712020-05-23 22:14:13 -0400[diff] [blame]105 .in_layout = true, \
106 .lane_mask = 0xff, \
107 }
108
109#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
110 { \
111 .offset = o, \
112 .val = v, \
113 .lane_mask = l, \
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]114 }
115
116/* set of registers with offsets different per-PHY */
117enum qphy_reg_layout {
118 /* Common block control registers */
119 QPHY_COM_SW_RESET,
120 QPHY_COM_POWER_DOWN_CONTROL,
121 QPHY_COM_START_CONTROL,
122 QPHY_COM_PCS_READY_STATUS,
123 /* PCS registers */
124 QPHY_PLL_LOCK_CHK_DLY_TIME,
125 QPHY_FLL_CNTRL1,
126 QPHY_FLL_CNTRL2,
127 QPHY_FLL_CNT_VAL_L,
128 QPHY_FLL_CNT_VAL_H_TOL,
129 QPHY_FLL_MAN_CODE,
130 QPHY_SW_RESET,
131 QPHY_START_CTRL,
132 QPHY_PCS_READY_STATUS,
Bjorn Andersson14ced7e2019-08-05 17:42:56 -0700[diff] [blame]133 QPHY_PCS_STATUS,
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]134 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
135 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
136 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
Wesley Chenge4d8b052020-05-04 16:54:26 -0700[diff] [blame]137 QPHY_PCS_POWER_DOWN_CONTROL,
Shawn Guo8abe5e72021-09-27 14:48:29 +0800[diff] [blame]138 /* PCS_MISC registers */
139 QPHY_PCS_MISC_TYPEC_CTRL,
Bjorn Andersson72f039d2020-05-14 18:36:43 -0700[diff] [blame]140 /* Keep last to ensure regs_layout arrays are properly initialized */
141 QPHY_LAYOUT_SIZE
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]142};
143
Bjorn Andersson72f039d2020-05-14 18:36:43 -0700[diff] [blame]144static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
Bjorn Andersson0347f0d2020-01-24 16:08:03 -0800[diff] [blame]145 [QPHY_START_CTRL] = 0x00,
146 [QPHY_PCS_READY_STATUS] = 0x168,
147};
148
Selvam Sathappan Periakaruppan520264d2021-05-05 12:18:31 +0300[diff] [blame]149static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
150 [QPHY_SW_RESET] = 0x00,
151 [QPHY_START_CTRL] = 0x44,
152 [QPHY_PCS_STATUS] = 0x14,
153 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
154};
155
Bjorn Andersson72f039d2020-05-14 18:36:43 -0700[diff] [blame]156static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]157 [QPHY_COM_SW_RESET] = 0x400,
158 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
159 [QPHY_COM_START_CONTROL] = 0x408,
160 [QPHY_COM_PCS_READY_STATUS] = 0x448,
161 [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
162 [QPHY_FLL_CNTRL1] = 0xc4,
163 [QPHY_FLL_CNTRL2] = 0xc8,
164 [QPHY_FLL_CNT_VAL_L] = 0xcc,
165 [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
166 [QPHY_FLL_MAN_CODE] = 0xd4,
167 [QPHY_SW_RESET] = 0x00,
168 [QPHY_START_CTRL] = 0x08,
Bjorn Andersson14ced7e2019-08-05 17:42:56 -0700[diff] [blame]169 [QPHY_PCS_STATUS] = 0x174,
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]170};
171
Bjorn Andersson72f039d2020-05-14 18:36:43 -0700[diff] [blame]172static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]173 [QPHY_FLL_CNTRL1] = 0xc0,
174 [QPHY_FLL_CNTRL2] = 0xc4,
175 [QPHY_FLL_CNT_VAL_L] = 0xc8,
176 [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
177 [QPHY_FLL_MAN_CODE] = 0xd0,
178 [QPHY_SW_RESET] = 0x00,
179 [QPHY_START_CTRL] = 0x08,
Bjorn Andersson14ced7e2019-08-05 17:42:56 -0700[diff] [blame]180 [QPHY_PCS_STATUS] = 0x17c,
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]181 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
182 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
183 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]184};
185
Bjorn Andersson72f039d2020-05-14 18:36:43 -0700[diff] [blame]186static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]187 [QPHY_SW_RESET] = 0x00,
188 [QPHY_START_CTRL] = 0x08,
Bjorn Andersson14ced7e2019-08-05 17:42:56 -0700[diff] [blame]189 [QPHY_PCS_STATUS] = 0x174,
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]190 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
191 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
192 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]193};
194
Bjorn Andersson72f039d2020-05-14 18:36:43 -0700[diff] [blame]195static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
Bjorn Andersson421c9a02020-01-06 00:18:20 -0800[diff] [blame]196 [QPHY_SW_RESET] = 0x00,
197 [QPHY_START_CTRL] = 0x08,
198 [QPHY_PCS_STATUS] = 0x174,
199};
200
Bjorn Andersson72f039d2020-05-14 18:36:43 -0700[diff] [blame]201static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
Bjorn Andersson909a5c72020-01-06 00:18:21 -0800[diff] [blame]202 [QPHY_SW_RESET] = 0x00,
203 [QPHY_START_CTRL] = 0x08,
204 [QPHY_PCS_STATUS] = 0x2ac,
205};
206
Bjorn Andersson72f039d2020-05-14 18:36:43 -0700[diff] [blame]207static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
Jack Pham9a24b922020-05-04 16:54:25 -0700[diff] [blame]208 [QPHY_SW_RESET] = 0x00,
209 [QPHY_START_CTRL] = 0x44,
210 [QPHY_PCS_STATUS] = 0x14,
Wesley Chenge4d8b052020-05-04 16:54:26 -0700[diff] [blame]211 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
Jonathan Marek7b675ba2020-05-23 22:14:14 -0400[diff] [blame]212 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
213 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
214};
215
216static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
217 [QPHY_SW_RESET] = 0x00,
218 [QPHY_START_CTRL] = 0x44,
219 [QPHY_PCS_STATUS] = 0x14,
220 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
221 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
222 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
Jack Pham9a24b922020-05-04 16:54:25 -0700[diff] [blame]223};
224
Jack Pham10c744d2021-01-15 09:47:21 -0800[diff] [blame]225static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
226 [QPHY_SW_RESET] = 0x00,
227 [QPHY_START_CTRL] = 0x44,
228 [QPHY_PCS_STATUS] = 0x14,
229 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
230 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
231 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
232};
233
Shawn Guo8abe5e72021-09-27 14:48:29 +0800[diff] [blame]234static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
235 [QPHY_SW_RESET] = 0x00,
236 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
237 [QPHY_START_CTRL] = 0x08,
238 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
239 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
240 [QPHY_PCS_STATUS] = 0x174,
241 [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
242};
243
Bjorn Andersson72f039d2020-05-14 18:36:43 -0700[diff] [blame]244static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
Can Guocc31cdb2018-09-20 21:27:56 -0700[diff] [blame]245 [QPHY_START_CTRL] = 0x00,
246 [QPHY_PCS_READY_STATUS] = 0x160,
247};
248
Iskren Chernev152a8102021-08-21 18:56:56 +0300[diff] [blame]249static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
250 [QPHY_START_CTRL] = 0x00,
251 [QPHY_PCS_READY_STATUS] = 0x168,
252};
253
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]254static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
255 [QPHY_SW_RESET] = 0x00,
256 [QPHY_START_CTRL] = 0x44,
257 [QPHY_PCS_STATUS] = 0x14,
258 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
259};
260
Bjorn Andersson72f039d2020-05-14 18:36:43 -0700[diff] [blame]261static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
Wesley Cheng78c2aac2020-05-04 16:54:27 -0700[diff] [blame]262 [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
263 [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
264 [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
Vinod Koula88c85e2019-10-24 13:18:02 +0530[diff] [blame]265};
266
Sivaprakash Murugesan507156f2020-06-08 19:41:17 +0530[diff] [blame]267static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
268 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
269 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
270 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
271 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
272 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
273 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
274 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
275 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
276 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
277 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
278 /* PLL and Loop filter settings */
279 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
280 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
281 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
282 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
283 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
284 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
285 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
286 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
287 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
288 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
289 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
290 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
291 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
292 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
293 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
294 /* SSC settings */
295 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
296 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
297 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
298 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
299 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
300 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
301 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
302};
303
304static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
305 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
306 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
307 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
308 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
309 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
310 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
311 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
312 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
313 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
314};
315
316static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
317 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
318 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
319 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
320 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
321 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
322 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
323 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
324 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
325 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
326 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
327 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
328 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
329 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
330 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
331 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
332 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
333 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
334 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
335 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
336 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
337 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
338 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
339 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
340};
341
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]342static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
343 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
344 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
345 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
346 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
347 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
348 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
349 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
350 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
351 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
352 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
353 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
354 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
355 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
356 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
357 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
358 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
359 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
360 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
361 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
362 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
363 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
364 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
365 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
366 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
367 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
368 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
369 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
370 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
371 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
372 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
373 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
374 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
375 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
376 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
377 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
378 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
379 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
380 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
381 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
382 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
383 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
384 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
385 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
386};
387
388static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
389 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
390 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
391};
392
393static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
394 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
395 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
396 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
397 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
398 QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
399 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
400 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
401 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
402 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
403 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
404};
405
406static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
407 QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
408 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
409 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
410
411 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
412
413 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
414 QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
415 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
416 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
417 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
418};
419
Marc Gonzalez73d7ec82019-04-09 14:48:22 +0200[diff] [blame]420static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
424 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
425 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
426 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
427 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
428 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
429 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
430 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
431 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
432 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
433 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
434 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
435 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
436 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
437 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
438 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
439 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
440 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
441 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
442 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
443 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
444 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
445 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
446 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
447 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
448 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
449 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
450 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
451 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
452 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
453 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
454 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
455 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
456 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
457 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
458 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
459 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
460 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
461 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
462 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
463};
464
465static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
466 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
467 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
468 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
469 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
470};
471
472static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
473 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
474 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
475 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
476 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
477 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
478 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
479 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
480 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
481 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
482 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
483 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
484 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
485 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
486 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
487};
488
489static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
490 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
491 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
492 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
493 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
494 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
495 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
496 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
497 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
498 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
499 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
500};
501
Bjorn Andersson0347f0d2020-01-24 16:08:03 -0800[diff] [blame]502static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
503 QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
504 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
505 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
506 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
507 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
508 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
509 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
510 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
511 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
512 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
513 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
514 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
515 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
516 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
517 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
518 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
519 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
520 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
521 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
522 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
523 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
524 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
525 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
526 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
527 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
528 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
529 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
530 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
531 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
532 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
533 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
534 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
535 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
536 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
537 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
538 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
539 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
540 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
541 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
542 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
543 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
544 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
545 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
546 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
547 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
548 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
549 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
550};
551
552static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
553 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
554 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
555};
556
557static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
558 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
559 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
560 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
561 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
562 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
563 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
564 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
565 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
566 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
567 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
568 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
569};
570
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]571static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
572 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
573 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
574 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
575 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
576 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
577 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
578 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
579 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
580 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
581 /* PLL and Loop filter settings */
582 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
583 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
584 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
585 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
586 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
587 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
588 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
589 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
590 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
591 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
592 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
593 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
594 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
595 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
596 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
597 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
598 /* SSC settings */
599 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
600 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
601 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
602 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
603 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
604 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
605 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
606};
607
608static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
609 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
610 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
611 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
612};
613
614static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
615 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
616 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
617 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
618 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
619 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
620 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
621 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
622 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
623 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
624 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
625};
626
627static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
628 /* FLL settings */
629 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
630 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
631 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
632 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
633 QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
634
635 /* Lock Det settings */
636 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
637 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
638 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
639 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
640};
641
Selvam Sathappan Periakaruppan520264d2021-05-05 12:18:31 +0300[diff] [blame]642static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
643 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
644 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
645 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
646 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
647 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
648 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
649 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
650 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
651 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
652 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
653 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
654 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
655 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
656 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
657 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
658 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
659 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
660 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
661 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
662 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
663 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
664 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
665 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
666 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
667 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
668 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
669 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
670 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
671 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
672 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
673 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
674 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
675 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
676 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
677 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
678 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
679 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
680 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
681 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
682 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
683 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
684 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
685 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
686 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
687 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
688 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
689};
690
691static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
692 QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
693 QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
694 QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
695};
696
697static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
698 QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
699 QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
700 QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
701 QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
702 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
703 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
704 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
705 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
706 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
707 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
708 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
709 QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
710 QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
711 QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
712 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
713 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
714 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
715 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
716 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
717 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
718 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
719 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
720 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
721 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
722 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
723 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
724 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
725 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
726 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
727 QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
728};
729
730static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
731 QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
732 QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
733 QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
734 QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
735 QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
736 QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
737 QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
738 QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
739 QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
740 QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
741 QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
742 QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
743 QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
744 QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
745 QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
746 QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
747};
748
Varadarajan Narayananeef243d2017-07-31 12:04:14 +0530[diff] [blame]749static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
750 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
751 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
752 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
753 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
754 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
Sivaprakash Murugesanafd55e62020-07-29 21:00:03 +0530[diff] [blame]755 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
756 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
Varadarajan Narayananeef243d2017-07-31 12:04:14 +0530[diff] [blame]757 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
758 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
759 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
760 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
761 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
762 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
763 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
764 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
765 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
766 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
767 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
768 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
769 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
770 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
771 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
772 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
773 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
774 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
775 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
776 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
777 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
778 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
779 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
780 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
781 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
Varadarajan Narayananeef243d2017-07-31 12:04:14 +0530[diff] [blame]782 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
783 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
784 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
785 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
786 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
787 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
788 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
789 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
Varadarajan Narayananeef243d2017-07-31 12:04:14 +0530[diff] [blame]790};
791
792static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
793 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
794 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
795 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
796 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
Sivaprakash Murugesanafd55e62020-07-29 21:00:03 +0530[diff] [blame]797 QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
798 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
Varadarajan Narayananeef243d2017-07-31 12:04:14 +0530[diff] [blame]799};
800
801static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
802 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
803 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
804 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
805 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
806 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
807 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
808 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
Varadarajan Narayananeef243d2017-07-31 12:04:14 +0530[diff] [blame]809};
810
811static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
812 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
813 QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
814 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
815 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
816 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
817 QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
818 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
819 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
820 QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
821 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
822 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
823 QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
824 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
825};
826
Bjorn Andersson421c9a02020-01-06 00:18:20 -0800[diff] [blame]827static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
828 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
829 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
830 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
831 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
832 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
833 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
834 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
835 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
836 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
837 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
838 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
839 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
840 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
841 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
842 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
843 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
844 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
845 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
846 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
847 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
848 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
849 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
850 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
851 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
852 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
853 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
854 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
855 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
856 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
857 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
858 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
859 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
860 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
861 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
862 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
863 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
864 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
865 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
866 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
867 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
868 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
869 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
870};
871
872static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
873 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
874 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
875 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
876 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
877};
878
879static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
880 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
881 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
882 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
883 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
884 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
885 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
886 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
887 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
888 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
889 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
890 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
891 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
892 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
893 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
894 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
895 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
896};
897
898static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
899 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
900
901 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
902 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
903 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
904 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
905 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
906
907 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
908 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
909 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
910 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
911 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
912 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
913 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
914
915 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
916 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
917 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
918
919 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
920};
921
922static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
923 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
924 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
925 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
926 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
927 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
928};
929
Bjorn Andersson909a5c72020-01-06 00:18:21 -0800[diff] [blame]930static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
931 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
932 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
933 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
934 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
935 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
936 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
937 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
938 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
939 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
940 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
941 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
942 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
943 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
944 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
945 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
946 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
947 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
948 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
949 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
950 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
951 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
952 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
953 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
954 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
955 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
956 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
957 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
958 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
959 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
960 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
961 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
962 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
963 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
964 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
965 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
966 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
967 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
968 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
969 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
970 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
971 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
972 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
973 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
974 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
975 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
976};
977
978static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
979 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
980 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
981 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
982 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
983 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
984 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
985 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
986 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
987 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
988 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
989 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
990 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
991 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
992 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
993 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
994 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
995 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
996 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
997 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
998 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
999 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
1000 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
1001 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
1002 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
1003 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
1004 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
1005 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
1006 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
1007 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
1008 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
1009 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
1010 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
1011 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
1012 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
1013 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
1014 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
1015 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
1016 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
1017 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
1018 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
1019 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
1020 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
1021 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
1022 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
1023 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
1024 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
1025 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
1026 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
1027 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
1028 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
1029 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
1030 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
1031 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
1032 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
1033 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
1034 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
1035};
1036
1037static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
1038};
1039
1040static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
1041 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
1042 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
1043 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
1044 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
1045 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
1046 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
1047 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
1048};
1049
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]1050static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
1051 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1052 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1053 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
1054 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1055 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1056 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1057 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
1058 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1059 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1060 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1061 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1062 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1063 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1064 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1065 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1066 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1067 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1068 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1069 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1070 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1071 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1072 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1073 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1074 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1075 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1076 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1077 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1078 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1079 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
1080 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1081 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1082 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1083 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1084 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1085 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1086 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1087};
1088
1089static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
1090 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1091 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1092 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1093 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
1094 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1095};
1096
Stephen Boyd7612f4e2020-09-16 16:12:00 -0700[diff] [blame]1097static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
1098 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1099 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
1100 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1101 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
1102 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
1103 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1104 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
1105 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
1106 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1107 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1108 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1109 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1110 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1111 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1112 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
1113 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
1114 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
1115 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1116 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1117 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1118 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1119};
1120
1121static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
1122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
1123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
1127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
1128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1129};
1130
1131static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
1132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
1133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
1137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
1138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1139};
1140
1141static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
1142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
1144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
1145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
1146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
1147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
1148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1149};
1150
1151static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
1152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
1153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1154 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1155 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1156 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
1157 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
1158 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
1159};
1160
1161static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
1162 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
1163 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
1164 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
1165 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
1166 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
1167 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
1168 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
1169 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1170 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
1171 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
1172 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
1173 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
1174 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
1175 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1176 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1177};
1178
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]1179static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
1180 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1181 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1182 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1183 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1184 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1185 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1186 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1187 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
1188 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1189};
1190
1191static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
1192 /* FLL settings */
1193 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1194 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1195 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1196 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1197 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1198
1199 /* Lock Det settings */
1200 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1201 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1202 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1203 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1204
1205 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
1206 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1207 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1208 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1209 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1210 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1211 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1212 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1213 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1214 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
1215 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1216 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1217 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1218 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1219 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
1220 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1221 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1222 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1223 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1224
1225 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1226 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1227 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1228 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1229 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1230 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1231 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1232 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1233 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1234 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1235 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1236};
1237
Manu Gautamf6721e52018-05-03 02:36:12 +0530[diff] [blame]1238static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
1239 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1240 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1241 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1242 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1243 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1244 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1245 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1246 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1247 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1248 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1249 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1250 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1251 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1252 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1253 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1254 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1255 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1256 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1257 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1258 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1259 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1260 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1261 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1262 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1263 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1264 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1265 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1266 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1267 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
1268 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1269 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1270 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1271 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1272 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1273 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1274 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1275};
1276
1277static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
1278 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1279 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1280 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
1281 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
1282 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1283};
1284
1285static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
1286 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
1287 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
1288 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1289 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1290 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1291 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1292 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1293 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1294 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1295 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1296 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1297};
1298
1299static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
1300 /* FLL settings */
1301 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1302 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1303 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1304 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1305 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1306
1307 /* Lock Det settings */
1308 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1309 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1310 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1311 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1312
1313 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
1314 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1315 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1316 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
1317 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
1318 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
1319 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
1320 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1321 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1322 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
1323 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1324 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1325 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1326 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1327 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
1328 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1329 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1330 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1331 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1332
1333 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1334 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1335 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1336 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1337 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1338 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1339 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1340 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1341 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1342 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1343 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1344
1345 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
1346 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
1347};
1348
Iskren Chernev152a8102021-08-21 18:56:56 +0300[diff] [blame]1349static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
1350 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
1351 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
1352 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
1353 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
1354 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
1355 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
1356 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
1357 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
1358 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
1359 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
1360 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
1361 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
1362 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
1363 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
1364 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
1365 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
1366 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
1367 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
1368 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
1369 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
1370 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
1371 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
1372 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
1373 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
1374 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
1375 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
1376 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1377 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
1378 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
1379 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
1380 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
1381 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
1382 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
1383 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
1384 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
1385 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
1386 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
1387 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
1388 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
1389 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
1390 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
1391 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
1392 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
1393 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
1394 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
1395 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
1396 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
1397 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
1398 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
1399 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
1400
1401 /* Rate B */
1402 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
1403};
1404
1405static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
1406 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
1407 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
1408};
1409
1410static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
1411 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
1412 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
1413 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
1414 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
1415 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
1416 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
1417 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
1418 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
1419 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
1420 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
1421 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
1422 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
1423 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
1424 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
1425 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
1426};
1427
1428static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
1429 QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
1430 QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
1431 QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
1432 QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
1433 QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
1434 QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
1435 QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
1436 QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
1437 QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
1438};
1439
Can Guocc31cdb2018-09-20 21:27:56 -0700[diff] [blame]1440static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
1441 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1442 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1443 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1444 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1445 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1446 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
1447 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
1448 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1449 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1450 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
1451 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
1452 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1453 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
1454 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
1455 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
1456 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
1457 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1458 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1459 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1460 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1461 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1462 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1463 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
1464 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1465 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
1466 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
1467 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
1468 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
1469 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
1470 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
1471 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
1472 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
1473 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
1474 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
1475 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
1476 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
1477
1478 /* Rate B */
1479 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
1480};
1481
1482static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
1483 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
1484 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
1485 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1486};
1487
1488static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
1489 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
1490 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
1491 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1492 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
1493 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1494 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
1495 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1496 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1497 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
1498 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
1499 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
1500 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
1501 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1502 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
1503 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1504 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
1505};
1506
1507static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
1508 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
1509 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1510 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
1511 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
1512 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
1513 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
1514 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
1515 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
1516};
Manu Gautamf6721e52018-05-03 02:36:12 +0530[diff] [blame]1517
Jeffrey Hugoa51969f2019-01-14 09:36:59 -0700[diff] [blame]1518static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
1519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
1523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1548 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
1549 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
1550 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1551 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1552 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1553 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1554 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1555 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1556 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1557};
1558
1559static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
1560 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1561 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1562 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1563 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
1564};
1565
1566static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
1567 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1568 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1569 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1570 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1571 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
1572 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1573 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
1574 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1575 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1576 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1577 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1578 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
1579 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
1580 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
1581 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1582 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
1583 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
1584};
1585
1586static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
1587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1588 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1591 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
1605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1609 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
1610 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1611 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1612 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1613 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1614 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1615 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1616 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1617 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1618 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1619 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1620 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1621 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
1622 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1623 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1624 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1625};
1626
Vinod Koula88c85e2019-10-24 13:18:02 +0530[diff] [blame]1627static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
Vinod Koula88c85e2019-10-24 13:18:02 +0530[diff] [blame]1628 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
1629 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
1630 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1631 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
1632 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1633 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1634 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
1635 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1636 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1637 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1638 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1639 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1640 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
1641 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
1642 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
1643 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1644 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
1645 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1646 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1647 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1648 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
1649 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
1650 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
1651 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
1652
1653 /* Rate B */
1654 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
1655};
1656
1657static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
1658 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
1659 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
1660 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
1661 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
1662 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
1663 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
1664};
1665
1666static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
1667 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
1668 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
1669 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1670 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
1671 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
1672 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1673 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
1674 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1675 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
1676 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1677 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1678 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
1679 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1680 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1681 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
1682 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
1683 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
1684 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1686 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
1687 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
1688 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
1689 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
1690 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
1691 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
1692 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
1693 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
1694 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1695 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
1696 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
1697 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
1698 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
1699 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1700 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
1701
1702};
1703
1704static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
Wesley Cheng78c2aac2020-05-04 16:54:27 -0700[diff] [blame]1705 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
1706 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1707 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
1708 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
1709 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
1710 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
1711 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
Vinod Koula88c85e2019-10-24 13:18:02 +0530[diff] [blame]1712};
Jeffrey Hugoa51969f2019-01-14 09:36:59 -0700[diff] [blame]1713
Jack Pham9a24b922020-05-04 16:54:25 -0700[diff] [blame]1714static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
1715 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1716 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1717 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1718 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1719 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1720 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1721 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1722 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1723 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1724 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1725 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1726 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1727 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1728 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1729 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1730 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1731 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1732 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1733 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1734 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1735 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1736 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1737 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1738 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1739 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1740 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1741 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1742 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1743 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1744 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1745 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1755};
1756
1757static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
1758 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
1759 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
1760 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1761 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1762 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1763};
1764
1765static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
1766 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
1767 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1768 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1769 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1770 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1771 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1772 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1773 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1774 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1775 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1776 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1777 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
1778 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1779 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1780 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1781 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1782 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1783 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1784 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1785 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1786 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1787 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
1788 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
1789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1790 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
1791 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1802};
1803
1804static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
1805 /* Lock Det settings */
1806 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1807 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1808 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1809
1810 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1811 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1812 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1813 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1814 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1815 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1816 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1817 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1818 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1819 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1820};
1821
Jonathan Marek7b675ba2020-05-23 22:14:14 -0400[diff] [blame]1822static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
1823 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1824 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1825 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1826 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1827 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1828 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1829 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1830 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1831 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1832 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1833 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1834 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1835 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1836 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1837 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1838 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1839 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1840 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1841 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1842 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1843 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1844 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1845 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1846 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1847 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1848 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1849 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1850 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1851 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1852 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1853 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1854 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1855 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1856 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1857 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1858 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1859 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1860 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1861 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1862 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1863};
1864
1865static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
1866 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1867 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
1868 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
1869 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
1870};
1871
1872static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
1873 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
1874 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1875 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
1876 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
1877 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
1878 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1879 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1880 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1881 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1882 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1883 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1884 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1885 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1886 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1887 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1888 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1889 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1890 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1891 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1892 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
1893 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1894 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1895 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1896 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1897 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1898 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1899 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1900 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1901 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1902 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1903 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1904 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1905 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1906 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
1907 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1908 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1909};
1910
1911static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
1912 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1913 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1914 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1915 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1916 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1917 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1918 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1919 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
1920 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1921 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
1922 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1923 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1924 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1925 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1926 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1927 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1928};
1929
Jonathan Marek90b65342020-05-23 22:14:15 -0400[diff] [blame]1930static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
1931 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
1932 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
1933 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1934 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
1935 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1936 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1937 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
1938 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
1939};
1940
1941static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
1942 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
1943 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1944 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1945 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1946 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1947 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1948 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1949 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1950 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1951 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1952 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1953 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1954 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1955 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1956 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1957 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1958 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1959 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1960 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1961 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1962 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
1963 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
1964 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
1965 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
1966 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
1967 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1968 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
1969 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1970 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1971 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1972 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
1973 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
1974 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1975 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1976 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1977 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1978 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1979 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1980};
1981
1982static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
1983 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1984 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1985 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1986 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1987 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1988 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
1989 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1990 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1991 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1992 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1993 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1994 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1995 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1996 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1997};
1998
1999static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
2000 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2001 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
2002 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
2003 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
2004 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
2005 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
2006};
2007
2008static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
2009 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
2010 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
2011 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
2012 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
2013 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
2014 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
2015 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
2016 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
2017 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
2018 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
2019 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
2020 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
2021 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
2022 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
2023 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
2024 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2025 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2026 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2027 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2028 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
2029 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
2030 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
2031 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2032 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2033 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2034 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2035 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2036 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2037 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
2038 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2039 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2040 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2041 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2042 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
2043 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2044 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
2045};
2046
2047static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
2048 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2049 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2050 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2051 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2052 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2053 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2054 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
2055 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2056 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
2057 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2058 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2059 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2060 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2061 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2062 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2063 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2064};
2065
Dmitry Baryshkovaff188f2021-03-31 18:16:12 +0300[diff] [blame]2066static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
2067 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
2068 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
2069 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
2070 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
2071 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
2072 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
2073 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2074 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
2075 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
2076 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
2077 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
2078 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
2079 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
2080 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
2081 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
2082 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
2083 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
2084 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
2085 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
2086 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
2087};
2088
2089static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
2090 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
2091 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
2092 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
2093 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
2094 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
2095 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
2096 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
2097};
2098
2099static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
2100 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
2101 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
2102 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
2103 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
2104 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
2105 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
2106 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
2107};
2108
2109static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
2110 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
2111 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
2112 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
2113 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
2114 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
2115 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
2116 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
2117};
2118
2119static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
2120 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
2121 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
2122 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
2123 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
2124 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
2125 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
2126 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
2127};
2128
2129static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
2130 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
2131 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
2132 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
2133 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
2134 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
2135 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
2136 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
2137 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
2138 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
2139 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
2140 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
2141 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
2142 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
2143 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
2144};
2145
Bjorn Anderssonf839f142021-06-28 17:45:09 -0700[diff] [blame]2146static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
2147 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
2148 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
2149 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
2150 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2151 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
2152 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
2153 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
2154 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
2155 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
2156 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2157 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
2158 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
2159 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
2160 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
2161 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
2162 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
2163 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
2164 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
2165 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
2166 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
2167 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
2168 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
2169 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
2170 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
2171 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
2172 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
2173 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
2174 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
2175 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
2176 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2177 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
2178 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
2179 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
2180 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
2181 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
2182 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
2183 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
2184 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2185 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2186 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
2187 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
2188 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
2189};
2190
2191static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
2192 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2193 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
2194};
2195
2196static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
2197 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
2198 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
2199 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
2200 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
2201 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
2202 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
2203 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
2204 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2205 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2206 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
2207 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
2208 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
2209 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
2210 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
2211 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
2212 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
2213 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
2214 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
2215 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
2216 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
2217 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
2218 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
2219 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
2220 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
2221 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
2222 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
2223 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
2224 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
2225 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2226 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2227 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
2228 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
2229 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2230 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
2231 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
2232 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
2233};
2234
2235static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
2236 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2237 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2238 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
2239 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
2240 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
2241};
2242
2243static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
2244 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2245 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2246 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2247 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
2248 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
2249 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
2250 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2251};
2252
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]2253static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
2254 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
2255 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
2256 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
2257 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2258 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
2259 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
2260 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
2261 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
2262 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
2263 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2264 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
2265 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
2266 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
2267 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
2268 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
2269 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
2270 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
2271 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
2272 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
2273 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
2274 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
2275 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
2276 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
2277 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
2278 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
2279 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
2280 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
2281 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
2282 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
2283 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2284 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
2285 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
2286 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
2287 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
2288 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
2289 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
2290 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2291 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2292 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
2293 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
2294 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
2295};
2296
2297static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
2298 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
2299};
2300
2301static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
2302 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2303 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
2304 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
2305};
2306
2307static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
2308 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
2309 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
2310 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
2311 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2312 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2313 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
2314 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
2315 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
2316 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2317 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
2318 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
2319 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2320 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
2321 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
2322 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
2323 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
2324 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
2325 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
2326 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
2327 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
2328 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
2329 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
2330 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
2331 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
2332 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
2333 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2334 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
2335 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
2336 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
2337 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
2338};
2339
2340static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
2341 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
2342 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
2343 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2344 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
2345 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
2346 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
2347};
2348
2349static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
2350 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2351 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
2352 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
2353};
2354
2355static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
2356 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
2357 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
2358};
2359
2360static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
2361 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2362 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2363 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2364 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
2365 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
2366 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
2367 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2368};
2369
2370static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
2371 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
2372 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
2373};
2374
2375static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
2376 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
2377};
2378
2379static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
2380 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
2381 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
2382 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
2383 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2384};
2385
2386static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
2387 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
2388 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
2389};
2390
2391static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
2392 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
2393 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
2394};
2395
Manivannan Sadhasivam86ef5a72021-01-11 17:00:10 +0530[diff] [blame]2396static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
2397 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2398 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
2399 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
2400 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
2401 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
2402};
2403
2404static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
2405 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
2406 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
2407 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
2408 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
2409 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
2410 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
2411 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
2412 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
2413 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
2414 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
2415 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
2416 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
2417 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
2418 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
2419 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
2420 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2421 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2422 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2423 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2424 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
2425 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
2426 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
2427 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2428 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2429 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2430 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2431 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2432 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2433 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
2434 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2435 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2436 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2437 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2438 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
2439 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2440 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
2441};
2442
Manivannan Sadhasivambe0ddb52021-04-27 12:24:00 +0530[diff] [blame]2443static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
2444 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
2445 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
2446 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
2447 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2448 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
2449 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
2450 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
2451 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
2452 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
2453 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
2454 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
2455 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
2456 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
2457 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
2458 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
2459 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
2460 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
2461 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
2462 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
2463 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
2464 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
2465 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
2466 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
2467 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
2468 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
2469 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
2470 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2471 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
2472 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
2473 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
2474 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
2475 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
2476 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
2477 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
2478 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
2479 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
2480 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
2481 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
2482 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
2483};
2484
2485static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
2486 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
2487 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
2488 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
2489 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
2490 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
2491};
2492
2493static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
2494 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
2495 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
2496 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
2497 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
2498 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
2499 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
2500 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
2501 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
2502 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
2503 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
2504 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
2505 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
2506 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
2507 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
2508 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
2509 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
2510 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
2511 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
2512 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
2513 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
2514 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
2515 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
2516 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
2517 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2518 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
2519};
2520
2521static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
2522 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
2523 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
2524 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
2525 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
2526};
2527
2528static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
2529 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
2530 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
2531 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
2532 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
2533 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
2534 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
2535 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
2536};
2537
Vinod Koul0e43fdb2021-02-04 22:28:05 +0530[diff] [blame]2538static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
2539 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
2540 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
2541 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2542 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
2543 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2544 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2545 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
2546 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2547 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2548 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
2549 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
2550 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
2551 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
2552 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
2553 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
2554 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2555 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
2556 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
2557 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
2558 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
2559 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
2560 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
2561 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
2562 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
2563
2564 /* Rate B */
2565 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
2566};
2567
2568static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
2569 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
2570 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
2571 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
2572 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
2573 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
2574 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2575 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
2576 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
2577 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
2578};
2579
2580static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
2581 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
2582 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
2583 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
2584 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
2585 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
2586 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
2587 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
2588 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
2589 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
2590 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
2591 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
2592 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
2593 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
2594 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
2595 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
2596 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
2597 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
2598 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
2599 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
2600 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2601 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2602 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
2603 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
2604 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
2605 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
2606 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
2607 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
2608 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
2609 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
2610 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
2611 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
2612 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
2613 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
2614 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
2615 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
2616 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
2617 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
2618};
2619
2620static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
2621 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
2622 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
2623 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
2624 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
2625 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
2626 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
2627 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
2628 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
2629 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
2630 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
2631 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
2632 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
2633 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
2634 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
2635 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
2636};
2637
Jack Pham10c744d2021-01-15 09:47:21 -0800[diff] [blame]2638static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
2639 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
2640 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
2641 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
2642 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
2643 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
2644 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2645 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
2646 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
2647 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
2648 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
2649};
2650
2651static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
2652 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
2653 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2654 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2655 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2656 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2657 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2658 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
2659 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2660 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2661 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
2662 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
2663 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
2664 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
2665 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2666 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2667 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2668 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2669 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2670 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2671 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
2672 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2673 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
2674 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
2675 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
2676 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
2677 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
2678 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
2679 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
2680 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
2681 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
2682 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
2683 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
2684 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
2685 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2686 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
2687 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
2688 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2689 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
2690};
2691
2692static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
2693 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
2694 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
2695 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2696 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2697 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2698 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2699 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2700 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2701 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2702 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2703 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2704 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2705 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2706 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2707 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2708 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2709 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2710 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
2711};
2712
2713static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
2714 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
2715 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
2716 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2717 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
2718 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
2719 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
2720 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
2721};
2722
2723static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
2724 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
2725 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
2726 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
2727 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
2728 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
2729 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
2730 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
2731 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
2732 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
2733 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
2734 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
2735 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2736 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2737 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
2738 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
2739 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2740 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2741 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2742 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
2743 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
2744 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
2745 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2746 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2747 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2748 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2749 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
2750 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2751 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2752 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2753 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2754 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
2755};
2756
2757static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
2758 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2759 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2760 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2761 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2762 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2763 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2764 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2765 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2766 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
2767 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2768 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2769 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2770 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2771 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2772 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2773 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2774};
2775
Shawn Guo8abe5e72021-09-27 14:48:29 +0800[diff] [blame]2776static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
2777 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
2778 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
2779 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
2780 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
2781 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
2782 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
2783 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
2784 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
2785 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
2786 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
2787 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
2788 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
2789 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
2790 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
2791 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
2792 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
2793 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
2794 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
2795 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
2796 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
2797 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
2798 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
2799 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
2800 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
2801 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
2802 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
2803 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
2804 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
2805 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
2806 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
2807 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
2808 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
2809 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
2810 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
2811 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
2812 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
2813 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
2814 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
2815};
2816
2817static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
2818 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
2819 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
2820 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
2821 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
2822 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
2823};
2824
2825static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
2826 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
2827 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
2828 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
2829 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
2830 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
2831 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
2832 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
2833 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
2834 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
2835 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
2836 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
2837 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2838 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
2839 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
2840 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
2841 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
2842 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
2843};
2844
2845static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
2846 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
2847 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
2848 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
2849 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
2850 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
2851 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
2852 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
2853 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
2854 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
2855 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
2856 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
2857 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
2858 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
2859 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
2860 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
2861 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
2862 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2863 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2864 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
2865 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
2866 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
2867};
2868
Dmitry Baryshkov5f0d28f2021-03-31 18:16:10 +0300[diff] [blame]2869struct qmp_phy;
2870
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]2871/* struct qmp_phy_cfg - per-PHY initialization config */
2872struct qmp_phy_cfg {
2873 /* phy-type - PCIE/UFS/USB */
2874 unsigned int type;
2875 /* number of lanes provided by phy */
2876 int nlanes;
2877
2878 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
2879 const struct qmp_phy_init_tbl *serdes_tbl;
2880 int serdes_tbl_num;
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]2881 const struct qmp_phy_init_tbl *serdes_tbl_sec;
2882 int serdes_tbl_num_sec;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]2883 const struct qmp_phy_init_tbl *tx_tbl;
2884 int tx_tbl_num;
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]2885 const struct qmp_phy_init_tbl *tx_tbl_sec;
2886 int tx_tbl_num_sec;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]2887 const struct qmp_phy_init_tbl *rx_tbl;
2888 int rx_tbl_num;
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]2889 const struct qmp_phy_init_tbl *rx_tbl_sec;
2890 int rx_tbl_num_sec;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]2891 const struct qmp_phy_init_tbl *pcs_tbl;
2892 int pcs_tbl_num;
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]2893 const struct qmp_phy_init_tbl *pcs_tbl_sec;
2894 int pcs_tbl_num_sec;
Bjorn Andersson421c9a02020-01-06 00:18:20 -0800[diff] [blame]2895 const struct qmp_phy_init_tbl *pcs_misc_tbl;
2896 int pcs_misc_tbl_num;
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]2897 const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
2898 int pcs_misc_tbl_num_sec;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]2899
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]2900 /* Init sequence for DP PHY block link rates */
2901 const struct qmp_phy_init_tbl *serdes_tbl_rbr;
2902 int serdes_tbl_rbr_num;
2903 const struct qmp_phy_init_tbl *serdes_tbl_hbr;
2904 int serdes_tbl_hbr_num;
2905 const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
2906 int serdes_tbl_hbr2_num;
2907 const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
2908 int serdes_tbl_hbr3_num;
2909
Dmitry Baryshkov5f0d28f2021-03-31 18:16:10 +0300[diff] [blame]2910 /* DP PHY callbacks */
2911 int (*configure_dp_phy)(struct qmp_phy *qphy);
2912 void (*configure_dp_tx)(struct qmp_phy *qphy);
2913 int (*calibrate_dp_phy)(struct qmp_phy *qphy);
2914 void (*dp_aux_init)(struct qmp_phy *qphy);
2915
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]2916 /* clock ids to be requested */
2917 const char * const *clk_list;
2918 int num_clks;
2919 /* resets to be requested */
2920 const char * const *reset_list;
2921 int num_resets;
2922 /* regulators to be requested */
2923 const char * const *vreg_list;
2924 int num_vregs;
2925
2926 /* array of registers with different offsets */
2927 const unsigned int *regs;
2928
2929 unsigned int start_ctrl;
2930 unsigned int pwrdn_ctrl;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]2931 unsigned int mask_com_pcs_ready;
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]2932 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
2933 unsigned int phy_status;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]2934
2935 /* true, if PHY has a separate PHY_COM control block */
2936 bool has_phy_com_ctrl;
2937 /* true, if PHY has a reset for individual lanes */
2938 bool has_lane_rst;
2939 /* true, if PHY needs delay after POWER_DOWN */
2940 bool has_pwrdn_delay;
2941 /* power_down delay in usec */
2942 int pwrdn_delay_min;
2943 int pwrdn_delay_max;
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]2944
2945 /* true, if PHY has a separate DP_COM control block */
2946 bool has_phy_dp_com_ctrl;
Can Guo6b045262018-09-20 21:27:55 -0700[diff] [blame]2947 /* true, if PHY has secondary tx/rx lanes to be configured */
2948 bool is_dual_lane_phy;
Can Guocc31cdb2018-09-20 21:27:56 -0700[diff] [blame]2949
2950 /* true, if PCS block has no separate SW_RESET register */
2951 bool no_pcs_sw_reset;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]2952};
2953
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]2954struct qmp_phy_combo_cfg {
2955 const struct qmp_phy_cfg *usb_cfg;
2956 const struct qmp_phy_cfg *dp_cfg;
2957};
2958
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]2959/**
2960 * struct qmp_phy - per-lane phy descriptor
2961 *
2962 * @phy: generic phy
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]2963 * @cfg: phy specific configuration
2964 * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]2965 * @tx: iomapped memory space for lane's tx
2966 * @rx: iomapped memory space for lane's rx
2967 * @pcs: iomapped memory space for lane's pcs
Evan Green5e17b952018-12-10 11:28:23 -0800[diff] [blame]2968 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
2969 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]2970 * @pcs_misc: iomapped memory space for lane's pcs_misc
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]2971 * @pipe_clk: pipe lock
2972 * @index: lane index
2973 * @qmp: QMP phy to which this lane belongs
2974 * @lane_rst: lane's reset controller
Stephen Boyddadcf992020-09-16 16:11:54 -0700[diff] [blame]2975 * @mode: current PHY mode
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]2976 */
2977struct qmp_phy {
2978 struct phy *phy;
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]2979 const struct qmp_phy_cfg *cfg;
2980 void __iomem *serdes;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]2981 void __iomem *tx;
2982 void __iomem *rx;
2983 void __iomem *pcs;
Evan Green5e17b952018-12-10 11:28:23 -0800[diff] [blame]2984 void __iomem *tx2;
2985 void __iomem *rx2;
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]2986 void __iomem *pcs_misc;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]2987 struct clk *pipe_clk;
2988 unsigned int index;
2989 struct qcom_qmp *qmp;
2990 struct reset_control *lane_rst;
Stephen Boyddadcf992020-09-16 16:11:54 -0700[diff] [blame]2991 enum phy_mode mode;
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]2992 unsigned int dp_aux_cfg;
2993 struct phy_configure_opts_dp dp_opts;
2994 struct qmp_phy_dp_clks *dp_clks;
2995};
2996
2997struct qmp_phy_dp_clks {
2998 struct qmp_phy *qphy;
2999 struct clk_hw dp_link_hw;
3000 struct clk_hw dp_pixel_hw;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]3001};
3002
3003/**
3004 * struct qcom_qmp - structure holding QMP phy block attributes
3005 *
3006 * @dev: device
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]3007 * @dp_com: iomapped memory space for phy's dp_com control block
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]3008 *
3009 * @clks: array of clocks required by phy
3010 * @resets: array of resets required by phy
3011 * @vregs: regulator supplies bulk data
3012 *
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]3013 * @phys: array of per-lane phy descriptors
3014 * @phy_mutex: mutex lock for PHY common block initialization
3015 * @init_count: phy common block initialization count
Evan Greenc9b58972019-03-21 10:17:59 -0700[diff] [blame]3016 * @ufs_reset: optional UFS PHY reset handle
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]3017 */
3018struct qcom_qmp {
3019 struct device *dev;
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]3020 void __iomem *dp_com;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]3021
Vivek Gautam10939b12018-01-16 16:26:57 +0530[diff] [blame]3022 struct clk_bulk_data *clks;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]3023 struct reset_control **resets;
3024 struct regulator_bulk_data *vregs;
3025
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]3026 struct qmp_phy **phys;
3027
3028 struct mutex phy_mutex;
3029 int init_count;
Evan Greenc9b58972019-03-21 10:17:59 -0700[diff] [blame]3030
3031 struct reset_control *ufs_reset;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]3032};
3033
Dmitry Baryshkov5f0d28f2021-03-31 18:16:10 +0300[diff] [blame]3034static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
3035static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
3036static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
3037static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
3038
Dmitry Baryshkovaff188f2021-03-31 18:16:12 +0300[diff] [blame]3039static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
3040static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
3041static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
3042static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
3043
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]3044static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
3045{
3046 u32 reg;
3047
3048 reg = readl(base + offset);
3049 reg |= val;
3050 writel(reg, base + offset);
3051
3052 /* ensure that above write is through */
3053 readl(base + offset);
3054}
3055
3056static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
3057{
3058 u32 reg;
3059
3060 reg = readl(base + offset);
3061 reg &= ~val;
3062 writel(reg, base + offset);
3063
3064 /* ensure that above write is through */
3065 readl(base + offset);
3066}
3067
3068/* list of clocks required by phy */
3069static const char * const msm8996_phy_clk_l[] = {
3070 "aux", "cfg_ahb", "ref",
3071};
3072
Bjorn Andersson0347f0d2020-01-24 16:08:03 -0800[diff] [blame]3073static const char * const msm8996_ufs_phy_clk_l[] = {
3074 "ref",
3075};
3076
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]3077static const char * const qmp_v3_phy_clk_l[] = {
3078 "aux", "cfg_ahb", "ref", "com_aux",
3079};
3080
Bjorn Andersson421c9a02020-01-06 00:18:20 -0800[diff] [blame]3081static const char * const sdm845_pciephy_clk_l[] = {
3082 "aux", "cfg_ahb", "ref", "refgen",
3083};
3084
Jack Pham9a24b922020-05-04 16:54:25 -0700[diff] [blame]3085static const char * const qmp_v4_phy_clk_l[] = {
3086 "aux", "ref_clk_src", "ref", "com_aux",
3087};
3088
Jonathan Marek90b65342020-05-23 22:14:15 -0400[diff] [blame]3089/* the primary usb3 phy on sm8250 doesn't have a ref clock */
3090static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
3091 "aux", "ref_clk_src", "com_aux"
3092};
3093
Can Guocc31cdb2018-09-20 21:27:56 -0700[diff] [blame]3094static const char * const sdm845_ufs_phy_clk_l[] = {
3095 "ref", "ref_aux",
3096};
3097
Manivannan Sadhasivam86ef5a72021-01-11 17:00:10 +0530[diff] [blame]3098/* usb3 phy on sdx55 doesn't have com_aux clock */
3099static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
3100 "aux", "cfg_ahb", "ref"
3101};
3102
Shawn Guo8abe5e72021-09-27 14:48:29 +0800[diff] [blame]3103static const char * const qcm2290_usb3phy_clk_l[] = {
3104 "cfg_ahb", "ref", "com_aux",
3105};
3106
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]3107/* list of resets */
3108static const char * const msm8996_pciephy_reset_l[] = {
3109 "phy", "common", "cfg",
3110};
3111
3112static const char * const msm8996_usb3phy_reset_l[] = {
3113 "phy", "common",
3114};
3115
Sandeep Maheswaramd30b16a2020-05-15 08:09:18 +0530[diff] [blame]3116static const char * const sc7180_usb3phy_reset_l[] = {
3117 "phy",
3118};
3119
Shawn Guo8abe5e72021-09-27 14:48:29 +0800[diff] [blame]3120static const char * const qcm2290_usb3phy_reset_l[] = {
3121 "phy_phy", "phy",
3122};
3123
Bjorn Andersson421c9a02020-01-06 00:18:20 -0800[diff] [blame]3124static const char * const sdm845_pciephy_reset_l[] = {
3125 "phy",
3126};
3127
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]3128/* list of regulators */
Can Guo6b045262018-09-20 21:27:55 -0700[diff] [blame]3129static const char * const qmp_phy_vreg_l[] = {
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]3130 "vdda-phy", "vdda-pll",
3131};
3132
Sivaprakash Murugesan507156f2020-06-08 19:41:17 +0530[diff] [blame]3133static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
3134 .type = PHY_TYPE_USB3,
3135 .nlanes = 1,
3136
3137 .serdes_tbl = ipq8074_usb3_serdes_tbl,
3138 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
3139 .tx_tbl = msm8996_usb3_tx_tbl,
3140 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
3141 .rx_tbl = ipq8074_usb3_rx_tbl,
3142 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
3143 .pcs_tbl = ipq8074_usb3_pcs_tbl,
3144 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
3145 .clk_list = msm8996_phy_clk_l,
3146 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
3147 .reset_list = msm8996_usb3phy_reset_l,
3148 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3149 .vreg_list = qmp_phy_vreg_l,
3150 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3151 .regs = usb3phy_regs_layout,
3152
3153 .start_ctrl = SERDES_START | PCS_START,
3154 .pwrdn_ctrl = SW_PWRDN,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3155 .phy_status = PHYSTATUS,
Sivaprakash Murugesan507156f2020-06-08 19:41:17 +0530[diff] [blame]3156};
3157
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]3158static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
3159 .type = PHY_TYPE_PCIE,
3160 .nlanes = 3,
3161
3162 .serdes_tbl = msm8996_pcie_serdes_tbl,
3163 .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
3164 .tx_tbl = msm8996_pcie_tx_tbl,
3165 .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
3166 .rx_tbl = msm8996_pcie_rx_tbl,
3167 .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
3168 .pcs_tbl = msm8996_pcie_pcs_tbl,
3169 .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
3170 .clk_list = msm8996_phy_clk_l,
3171 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
3172 .reset_list = msm8996_pciephy_reset_l,
3173 .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
Can Guo6b045262018-09-20 21:27:55 -0700[diff] [blame]3174 .vreg_list = qmp_phy_vreg_l,
3175 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]3176 .regs = pciephy_regs_layout,
3177
3178 .start_ctrl = PCS_START | PLL_READY_GATE_EN,
3179 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3180 .mask_com_pcs_ready = PCS_READY,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3181 .phy_status = PHYSTATUS,
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]3182
3183 .has_phy_com_ctrl = true,
3184 .has_lane_rst = true,
3185 .has_pwrdn_delay = true,
3186 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3187 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3188};
3189
Bjorn Andersson0347f0d2020-01-24 16:08:03 -0800[diff] [blame]3190static const struct qmp_phy_cfg msm8996_ufs_cfg = {
3191 .type = PHY_TYPE_UFS,
3192 .nlanes = 1,
3193
3194 .serdes_tbl = msm8996_ufs_serdes_tbl,
3195 .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
3196 .tx_tbl = msm8996_ufs_tx_tbl,
3197 .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
3198 .rx_tbl = msm8996_ufs_rx_tbl,
3199 .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
3200
3201 .clk_list = msm8996_ufs_phy_clk_l,
3202 .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
3203
3204 .vreg_list = qmp_phy_vreg_l,
3205 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3206
3207 .regs = msm8996_ufsphy_regs_layout,
3208
3209 .start_ctrl = SERDES_START,
3210 .pwrdn_ctrl = SW_PWRDN,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3211 .phy_status = PHYSTATUS,
Bjorn Andersson0347f0d2020-01-24 16:08:03 -0800[diff] [blame]3212
3213 .no_pcs_sw_reset = true,
3214};
3215
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]3216static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
3217 .type = PHY_TYPE_USB3,
3218 .nlanes = 1,
3219
3220 .serdes_tbl = msm8996_usb3_serdes_tbl,
3221 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
3222 .tx_tbl = msm8996_usb3_tx_tbl,
3223 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
3224 .rx_tbl = msm8996_usb3_rx_tbl,
3225 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
3226 .pcs_tbl = msm8996_usb3_pcs_tbl,
3227 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
3228 .clk_list = msm8996_phy_clk_l,
3229 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
3230 .reset_list = msm8996_usb3phy_reset_l,
3231 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
Can Guo6b045262018-09-20 21:27:55 -0700[diff] [blame]3232 .vreg_list = qmp_phy_vreg_l,
3233 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]3234 .regs = usb3phy_regs_layout,
3235
3236 .start_ctrl = SERDES_START | PCS_START,
3237 .pwrdn_ctrl = SW_PWRDN,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3238 .phy_status = PHYSTATUS,
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]3239};
3240
Sivaprakash Murugesanafd55e62020-07-29 21:00:03 +0530[diff] [blame]3241static const char * const ipq8074_pciephy_clk_l[] = {
3242 "aux", "cfg_ahb",
3243};
Varadarajan Narayananeef243d2017-07-31 12:04:14 +0530[diff] [blame]3244/* list of resets */
3245static const char * const ipq8074_pciephy_reset_l[] = {
3246 "phy", "common",
3247};
3248
3249static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
3250 .type = PHY_TYPE_PCIE,
3251 .nlanes = 1,
3252
3253 .serdes_tbl = ipq8074_pcie_serdes_tbl,
3254 .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
3255 .tx_tbl = ipq8074_pcie_tx_tbl,
3256 .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
3257 .rx_tbl = ipq8074_pcie_rx_tbl,
3258 .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
3259 .pcs_tbl = ipq8074_pcie_pcs_tbl,
3260 .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
Sivaprakash Murugesanafd55e62020-07-29 21:00:03 +0530[diff] [blame]3261 .clk_list = ipq8074_pciephy_clk_l,
3262 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
Varadarajan Narayananeef243d2017-07-31 12:04:14 +0530[diff] [blame]3263 .reset_list = ipq8074_pciephy_reset_l,
3264 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3265 .vreg_list = NULL,
3266 .num_vregs = 0,
3267 .regs = pciephy_regs_layout,
3268
3269 .start_ctrl = SERDES_START | PCS_START,
3270 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3271 .phy_status = PHYSTATUS,
Varadarajan Narayananeef243d2017-07-31 12:04:14 +0530[diff] [blame]3272
3273 .has_phy_com_ctrl = false,
3274 .has_lane_rst = false,
3275 .has_pwrdn_delay = true,
3276 .pwrdn_delay_min = 995, /* us */
3277 .pwrdn_delay_max = 1005, /* us */
3278};
3279
Selvam Sathappan Periakaruppan520264d2021-05-05 12:18:31 +0300[diff] [blame]3280static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
3281 .type = PHY_TYPE_PCIE,
3282 .nlanes = 1,
3283
3284 .serdes_tbl = ipq6018_pcie_serdes_tbl,
3285 .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
3286 .tx_tbl = ipq6018_pcie_tx_tbl,
3287 .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
3288 .rx_tbl = ipq6018_pcie_rx_tbl,
3289 .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
3290 .pcs_tbl = ipq6018_pcie_pcs_tbl,
3291 .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
3292 .clk_list = ipq8074_pciephy_clk_l,
3293 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
3294 .reset_list = ipq8074_pciephy_reset_l,
3295 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3296 .vreg_list = NULL,
3297 .num_vregs = 0,
3298 .regs = ipq_pciephy_gen3_regs_layout,
3299
3300 .start_ctrl = SERDES_START | PCS_START,
3301 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3302
3303 .has_phy_com_ctrl = false,
3304 .has_lane_rst = false,
3305 .has_pwrdn_delay = true,
3306 .pwrdn_delay_min = 995, /* us */
3307 .pwrdn_delay_max = 1005, /* us */
3308};
3309
Bjorn Andersson421c9a02020-01-06 00:18:20 -0800[diff] [blame]3310static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
3311 .type = PHY_TYPE_PCIE,
3312 .nlanes = 1,
3313
3314 .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
3315 .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
3316 .tx_tbl = sdm845_qmp_pcie_tx_tbl,
3317 .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
3318 .rx_tbl = sdm845_qmp_pcie_rx_tbl,
3319 .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
3320 .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
3321 .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
3322 .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
3323 .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
3324 .clk_list = sdm845_pciephy_clk_l,
3325 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
3326 .reset_list = sdm845_pciephy_reset_l,
3327 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3328 .vreg_list = qmp_phy_vreg_l,
3329 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3330 .regs = sdm845_qmp_pciephy_regs_layout,
3331
3332 .start_ctrl = PCS_START | SERDES_START,
3333 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3334 .phy_status = PHYSTATUS,
Bjorn Andersson421c9a02020-01-06 00:18:20 -0800[diff] [blame]3335
3336 .has_pwrdn_delay = true,
3337 .pwrdn_delay_min = 995, /* us */
3338 .pwrdn_delay_max = 1005, /* us */
3339};
3340
Bjorn Andersson909a5c72020-01-06 00:18:21 -0800[diff] [blame]3341static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
3342 .type = PHY_TYPE_PCIE,
3343 .nlanes = 1,
3344
3345 .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
3346 .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
3347 .tx_tbl = sdm845_qhp_pcie_tx_tbl,
3348 .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
3349 .rx_tbl = sdm845_qhp_pcie_rx_tbl,
3350 .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
3351 .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
3352 .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
3353 .clk_list = sdm845_pciephy_clk_l,
3354 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
3355 .reset_list = sdm845_pciephy_reset_l,
3356 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3357 .vreg_list = qmp_phy_vreg_l,
3358 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3359 .regs = sdm845_qhp_pciephy_regs_layout,
3360
3361 .start_ctrl = PCS_START | SERDES_START,
3362 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3363 .phy_status = PHYSTATUS,
Bjorn Andersson909a5c72020-01-06 00:18:21 -0800[diff] [blame]3364
3365 .has_pwrdn_delay = true,
3366 .pwrdn_delay_min = 995, /* us */
3367 .pwrdn_delay_max = 1005, /* us */
3368};
3369
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]3370static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
3371 .type = PHY_TYPE_PCIE,
3372 .nlanes = 1,
3373
3374 .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
3375 .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3376 .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
3377 .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
3378 .tx_tbl = sm8250_qmp_pcie_tx_tbl,
3379 .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
3380 .rx_tbl = sm8250_qmp_pcie_rx_tbl,
3381 .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
3382 .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
3383 .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
3384 .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
3385 .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
3386 .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
3387 .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
3388 .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
3389 .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
3390 .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
3391 .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
3392 .clk_list = sdm845_pciephy_clk_l,
3393 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
3394 .reset_list = sdm845_pciephy_reset_l,
3395 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3396 .vreg_list = qmp_phy_vreg_l,
3397 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3398 .regs = sm8250_pcie_regs_layout,
3399
3400 .start_ctrl = PCS_START | SERDES_START,
3401 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3402 .phy_status = PHYSTATUS,
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]3403
3404 .has_pwrdn_delay = true,
3405 .pwrdn_delay_min = 995, /* us */
3406 .pwrdn_delay_max = 1005, /* us */
3407};
3408
3409static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
3410 .type = PHY_TYPE_PCIE,
3411 .nlanes = 2,
3412
3413 .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
3414 .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3415 .tx_tbl = sm8250_qmp_pcie_tx_tbl,
3416 .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
3417 .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
3418 .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
3419 .rx_tbl = sm8250_qmp_pcie_rx_tbl,
3420 .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
3421 .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
3422 .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
3423 .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
3424 .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
3425 .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
3426 .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
3427 .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
3428 .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
3429 .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
3430 .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
3431 .clk_list = sdm845_pciephy_clk_l,
3432 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
3433 .reset_list = sdm845_pciephy_reset_l,
3434 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3435 .vreg_list = qmp_phy_vreg_l,
3436 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3437 .regs = sm8250_pcie_regs_layout,
3438
3439 .start_ctrl = PCS_START | SERDES_START,
3440 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3441 .phy_status = PHYSTATUS,
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]3442
3443 .is_dual_lane_phy = true,
3444 .has_pwrdn_delay = true,
3445 .pwrdn_delay_min = 995, /* us */
3446 .pwrdn_delay_max = 1005, /* us */
3447};
3448
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]3449static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
3450 .type = PHY_TYPE_USB3,
3451 .nlanes = 1,
3452
3453 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
3454 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
3455 .tx_tbl = qmp_v3_usb3_tx_tbl,
3456 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
3457 .rx_tbl = qmp_v3_usb3_rx_tbl,
3458 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
3459 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
3460 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
3461 .clk_list = qmp_v3_phy_clk_l,
3462 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
3463 .reset_list = msm8996_usb3phy_reset_l,
3464 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
Can Guo6b045262018-09-20 21:27:55 -0700[diff] [blame]3465 .vreg_list = qmp_phy_vreg_l,
3466 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]3467 .regs = qmp_v3_usb3phy_regs_layout,
3468
3469 .start_ctrl = SERDES_START | PCS_START,
3470 .pwrdn_ctrl = SW_PWRDN,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3471 .phy_status = PHYSTATUS,
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]3472
Manu Gautamf6721e52018-05-03 02:36:12 +0530[diff] [blame]3473 .has_pwrdn_delay = true,
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]3474 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3475 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3476
3477 .has_phy_dp_com_ctrl = true,
Can Guo6b045262018-09-20 21:27:55 -0700[diff] [blame]3478 .is_dual_lane_phy = true,
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]3479};
3480
Sandeep Maheswaramd30b16a2020-05-15 08:09:18 +0530[diff] [blame]3481static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
3482 .type = PHY_TYPE_USB3,
3483 .nlanes = 1,
3484
3485 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
3486 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
3487 .tx_tbl = qmp_v3_usb3_tx_tbl,
3488 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
3489 .rx_tbl = qmp_v3_usb3_rx_tbl,
3490 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
3491 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
3492 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
3493 .clk_list = qmp_v3_phy_clk_l,
3494 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
3495 .reset_list = sc7180_usb3phy_reset_l,
3496 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
3497 .vreg_list = qmp_phy_vreg_l,
3498 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3499 .regs = qmp_v3_usb3phy_regs_layout,
3500
3501 .start_ctrl = SERDES_START | PCS_START,
3502 .pwrdn_ctrl = SW_PWRDN,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3503 .phy_status = PHYSTATUS,
Sandeep Maheswaramd30b16a2020-05-15 08:09:18 +0530[diff] [blame]3504
3505 .has_pwrdn_delay = true,
3506 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3507 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3508
3509 .has_phy_dp_com_ctrl = true,
3510 .is_dual_lane_phy = true,
3511};
3512
Stephen Boyd7612f4e2020-09-16 16:12:00 -0700[diff] [blame]3513static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
3514 .type = PHY_TYPE_DP,
3515 .nlanes = 1,
3516
3517 .serdes_tbl = qmp_v3_dp_serdes_tbl,
3518 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
3519 .tx_tbl = qmp_v3_dp_tx_tbl,
3520 .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
3521
3522 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
3523 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
3524 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
3525 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
3526 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
3527 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
3528 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
3529 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
3530
3531 .clk_list = qmp_v3_phy_clk_l,
3532 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
3533 .reset_list = sc7180_usb3phy_reset_l,
3534 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
3535 .vreg_list = qmp_phy_vreg_l,
3536 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3537 .regs = qmp_v3_usb3phy_regs_layout,
3538
3539 .has_phy_dp_com_ctrl = true,
3540 .is_dual_lane_phy = true,
Dmitry Baryshkov5f0d28f2021-03-31 18:16:10 +0300[diff] [blame]3541
3542 .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
3543 .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
3544 .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
3545 .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
Stephen Boyd7612f4e2020-09-16 16:12:00 -0700[diff] [blame]3546};
3547
3548static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
3549 .usb_cfg = &sc7180_usb3phy_cfg,
3550 .dp_cfg = &sc7180_dpphy_cfg,
3551};
3552
Manu Gautamf6721e52018-05-03 02:36:12 +0530[diff] [blame]3553static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
3554 .type = PHY_TYPE_USB3,
3555 .nlanes = 1,
3556
3557 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
3558 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
3559 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
3560 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
3561 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
3562 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
3563 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
3564 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
3565 .clk_list = qmp_v3_phy_clk_l,
3566 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
3567 .reset_list = msm8996_usb3phy_reset_l,
3568 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
Can Guo6b045262018-09-20 21:27:55 -0700[diff] [blame]3569 .vreg_list = qmp_phy_vreg_l,
3570 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
Manu Gautamf6721e52018-05-03 02:36:12 +0530[diff] [blame]3571 .regs = qmp_v3_usb3phy_regs_layout,
3572
3573 .start_ctrl = SERDES_START | PCS_START,
3574 .pwrdn_ctrl = SW_PWRDN,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3575 .phy_status = PHYSTATUS,
Manu Gautamf6721e52018-05-03 02:36:12 +0530[diff] [blame]3576
3577 .has_pwrdn_delay = true,
3578 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3579 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3580};
3581
Can Guocc31cdb2018-09-20 21:27:56 -0700[diff] [blame]3582static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
3583 .type = PHY_TYPE_UFS,
3584 .nlanes = 2,
3585
3586 .serdes_tbl = sdm845_ufsphy_serdes_tbl,
3587 .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
3588 .tx_tbl = sdm845_ufsphy_tx_tbl,
3589 .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
3590 .rx_tbl = sdm845_ufsphy_rx_tbl,
3591 .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
3592 .pcs_tbl = sdm845_ufsphy_pcs_tbl,
3593 .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
3594 .clk_list = sdm845_ufs_phy_clk_l,
3595 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3596 .vreg_list = qmp_phy_vreg_l,
3597 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3598 .regs = sdm845_ufsphy_regs_layout,
3599
3600 .start_ctrl = SERDES_START,
3601 .pwrdn_ctrl = SW_PWRDN,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3602 .phy_status = PHYSTATUS,
Can Guocc31cdb2018-09-20 21:27:56 -0700[diff] [blame]3603
3604 .is_dual_lane_phy = true,
Can Guocc31cdb2018-09-20 21:27:56 -0700[diff] [blame]3605 .no_pcs_sw_reset = true,
3606};
3607
Iskren Chernev152a8102021-08-21 18:56:56 +0300[diff] [blame]3608static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
3609 .type = PHY_TYPE_UFS,
3610 .nlanes = 1,
3611
3612 .serdes_tbl = sm6115_ufsphy_serdes_tbl,
3613 .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
3614 .tx_tbl = sm6115_ufsphy_tx_tbl,
3615 .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
3616 .rx_tbl = sm6115_ufsphy_rx_tbl,
3617 .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
3618 .pcs_tbl = sm6115_ufsphy_pcs_tbl,
3619 .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
3620 .clk_list = sdm845_ufs_phy_clk_l,
3621 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3622 .vreg_list = qmp_phy_vreg_l,
3623 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3624 .regs = sm6115_ufsphy_regs_layout,
3625
3626 .start_ctrl = SERDES_START,
3627 .pwrdn_ctrl = SW_PWRDN,
3628
3629 .is_dual_lane_phy = false,
3630 .no_pcs_sw_reset = true,
3631};
3632
Marc Gonzalez73d7ec82019-04-09 14:48:22 +0200[diff] [blame]3633static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
3634 .type = PHY_TYPE_PCIE,
3635 .nlanes = 1,
3636
3637 .serdes_tbl = msm8998_pcie_serdes_tbl,
3638 .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
3639 .tx_tbl = msm8998_pcie_tx_tbl,
3640 .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
3641 .rx_tbl = msm8998_pcie_rx_tbl,
3642 .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
3643 .pcs_tbl = msm8998_pcie_pcs_tbl,
3644 .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
3645 .clk_list = msm8996_phy_clk_l,
3646 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
3647 .reset_list = ipq8074_pciephy_reset_l,
3648 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3649 .vreg_list = qmp_phy_vreg_l,
3650 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3651 .regs = pciephy_regs_layout,
3652
3653 .start_ctrl = SERDES_START | PCS_START,
3654 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3655 .phy_status = PHYSTATUS,
Marc Gonzalez73d7ec82019-04-09 14:48:22 +0200[diff] [blame]3656};
3657
Jeffrey Hugoa51969f2019-01-14 09:36:59 -0700[diff] [blame]3658static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
3659 .type = PHY_TYPE_USB3,
3660 .nlanes = 1,
3661
3662 .serdes_tbl = msm8998_usb3_serdes_tbl,
3663 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
3664 .tx_tbl = msm8998_usb3_tx_tbl,
3665 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
3666 .rx_tbl = msm8998_usb3_rx_tbl,
3667 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
3668 .pcs_tbl = msm8998_usb3_pcs_tbl,
3669 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
3670 .clk_list = msm8996_phy_clk_l,
3671 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
3672 .reset_list = msm8996_usb3phy_reset_l,
3673 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3674 .vreg_list = qmp_phy_vreg_l,
3675 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3676 .regs = qmp_v3_usb3phy_regs_layout,
3677
3678 .start_ctrl = SERDES_START | PCS_START,
3679 .pwrdn_ctrl = SW_PWRDN,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3680 .phy_status = PHYSTATUS,
Jeffrey Hugoa51969f2019-01-14 09:36:59 -0700[diff] [blame]3681
3682 .is_dual_lane_phy = true,
3683};
3684
Vinod Koula88c85e2019-10-24 13:18:02 +0530[diff] [blame]3685static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
3686 .type = PHY_TYPE_UFS,
3687 .nlanes = 2,
3688
3689 .serdes_tbl = sm8150_ufsphy_serdes_tbl,
3690 .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
3691 .tx_tbl = sm8150_ufsphy_tx_tbl,
3692 .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
3693 .rx_tbl = sm8150_ufsphy_rx_tbl,
3694 .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
3695 .pcs_tbl = sm8150_ufsphy_pcs_tbl,
3696 .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
3697 .clk_list = sdm845_ufs_phy_clk_l,
3698 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3699 .vreg_list = qmp_phy_vreg_l,
3700 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3701 .regs = sm8150_ufsphy_regs_layout,
3702
3703 .start_ctrl = SERDES_START,
3704 .pwrdn_ctrl = SW_PWRDN,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3705 .phy_status = PHYSTATUS,
Vinod Koula88c85e2019-10-24 13:18:02 +0530[diff] [blame]3706
3707 .is_dual_lane_phy = true,
Vinod Koula88c85e2019-10-24 13:18:02 +0530[diff] [blame]3708};
3709
Jack Pham9a24b922020-05-04 16:54:25 -0700[diff] [blame]3710static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
3711 .type = PHY_TYPE_USB3,
3712 .nlanes = 1,
3713
3714 .serdes_tbl = sm8150_usb3_serdes_tbl,
3715 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
3716 .tx_tbl = sm8150_usb3_tx_tbl,
3717 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
3718 .rx_tbl = sm8150_usb3_rx_tbl,
3719 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
3720 .pcs_tbl = sm8150_usb3_pcs_tbl,
3721 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
3722 .clk_list = qmp_v4_phy_clk_l,
3723 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
3724 .reset_list = msm8996_usb3phy_reset_l,
3725 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3726 .vreg_list = qmp_phy_vreg_l,
3727 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3728 .regs = qmp_v4_usb3phy_regs_layout,
3729
3730 .start_ctrl = SERDES_START | PCS_START,
3731 .pwrdn_ctrl = SW_PWRDN,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3732 .phy_status = PHYSTATUS,
3733
Jack Pham9a24b922020-05-04 16:54:25 -0700[diff] [blame]3734
3735 .has_pwrdn_delay = true,
3736 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3737 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3738
3739 .has_phy_dp_com_ctrl = true,
3740 .is_dual_lane_phy = true,
3741};
3742
Bjorn Anderssonf839f142021-06-28 17:45:09 -0700[diff] [blame]3743static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
3744 .type = PHY_TYPE_PCIE,
3745 .nlanes = 1,
3746
Bjorn Anderssonbfccd9a2021-07-21 09:30:29 -0700[diff] [blame]3747 .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
Dmitry Baryshkov26f71ab2021-10-20 18:56:04 +0300[diff] [blame^]3748 .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
Bjorn Anderssonf839f142021-06-28 17:45:09 -0700[diff] [blame]3749 .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
3750 .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
3751 .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
3752 .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
3753 .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
3754 .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
3755 .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
3756 .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
3757 .clk_list = sdm845_pciephy_clk_l,
3758 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
3759 .reset_list = sdm845_pciephy_reset_l,
3760 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3761 .vreg_list = qmp_phy_vreg_l,
3762 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3763 .regs = sm8250_pcie_regs_layout,
3764
3765 .start_ctrl = PCS_START | SERDES_START,
3766 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3767
3768 .has_pwrdn_delay = true,
3769 .pwrdn_delay_min = 995, /* us */
3770 .pwrdn_delay_max = 1005, /* us */
3771};
3772
Bjorn Andersson16338022021-07-21 15:56:30 -0700[diff] [blame]3773static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
3774 .type = PHY_TYPE_DP,
3775 .nlanes = 1,
3776
3777 .serdes_tbl = qmp_v4_dp_serdes_tbl,
3778 .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
3779 .tx_tbl = qmp_v4_dp_tx_tbl,
3780 .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
3781
3782 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
3783 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
3784 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
3785 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
3786 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
3787 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
3788 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
3789 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
3790
3791 .clk_list = qmp_v3_phy_clk_l,
3792 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
3793 .reset_list = sc7180_usb3phy_reset_l,
3794 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
3795 .vreg_list = qmp_phy_vreg_l,
3796 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3797 .regs = qmp_v3_usb3phy_regs_layout,
3798
3799 .has_phy_dp_com_ctrl = true,
3800 .is_dual_lane_phy = true,
3801
3802 .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
3803 .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
3804 .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
3805 .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
3806};
3807
3808static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
3809 .usb_cfg = &sm8150_usb3phy_cfg,
3810 .dp_cfg = &sc8180x_dpphy_cfg,
3811};
3812
Jonathan Marek7b675ba2020-05-23 22:14:14 -0400[diff] [blame]3813static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
3814 .type = PHY_TYPE_USB3,
3815 .nlanes = 1,
3816
3817 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
3818 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
3819 .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
3820 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
3821 .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
3822 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
3823 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
3824 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
3825 .clk_list = qmp_v4_phy_clk_l,
3826 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
3827 .reset_list = msm8996_usb3phy_reset_l,
3828 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3829 .vreg_list = qmp_phy_vreg_l,
3830 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3831 .regs = qmp_v4_usb3_uniphy_regs_layout,
3832
3833 .start_ctrl = SERDES_START | PCS_START,
3834 .pwrdn_ctrl = SW_PWRDN,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3835 .phy_status = PHYSTATUS,
Jonathan Marek7b675ba2020-05-23 22:14:14 -0400[diff] [blame]3836
3837 .has_pwrdn_delay = true,
3838 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3839 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3840};
3841
Jonathan Marek90b65342020-05-23 22:14:15 -0400[diff] [blame]3842static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
3843 .type = PHY_TYPE_USB3,
3844 .nlanes = 1,
3845
3846 .serdes_tbl = sm8150_usb3_serdes_tbl,
3847 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
3848 .tx_tbl = sm8250_usb3_tx_tbl,
3849 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
3850 .rx_tbl = sm8250_usb3_rx_tbl,
3851 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
3852 .pcs_tbl = sm8250_usb3_pcs_tbl,
3853 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
3854 .clk_list = qmp_v4_sm8250_usbphy_clk_l,
3855 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
3856 .reset_list = msm8996_usb3phy_reset_l,
3857 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3858 .vreg_list = qmp_phy_vreg_l,
3859 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3860 .regs = qmp_v4_usb3phy_regs_layout,
3861
3862 .start_ctrl = SERDES_START | PCS_START,
3863 .pwrdn_ctrl = SW_PWRDN,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3864 .phy_status = PHYSTATUS,
Jonathan Marek90b65342020-05-23 22:14:15 -0400[diff] [blame]3865
3866 .has_pwrdn_delay = true,
3867 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3868 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3869
3870 .has_phy_dp_com_ctrl = true,
3871 .is_dual_lane_phy = true,
3872};
3873
3874static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
3875 .type = PHY_TYPE_USB3,
3876 .nlanes = 1,
3877
3878 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
3879 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
3880 .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
3881 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
3882 .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
3883 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
3884 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
3885 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
3886 .clk_list = qmp_v4_phy_clk_l,
3887 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
3888 .reset_list = msm8996_usb3phy_reset_l,
3889 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3890 .vreg_list = qmp_phy_vreg_l,
3891 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3892 .regs = qmp_v4_usb3_uniphy_regs_layout,
3893
3894 .start_ctrl = SERDES_START | PCS_START,
3895 .pwrdn_ctrl = SW_PWRDN,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3896 .phy_status = PHYSTATUS,
Jonathan Marek90b65342020-05-23 22:14:15 -0400[diff] [blame]3897
3898 .has_pwrdn_delay = true,
3899 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3900 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3901};
3902
Dmitry Baryshkovaff188f2021-03-31 18:16:12 +0300[diff] [blame]3903static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
3904 .type = PHY_TYPE_DP,
3905 .nlanes = 1,
3906
3907 .serdes_tbl = qmp_v4_dp_serdes_tbl,
3908 .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
3909 .tx_tbl = qmp_v4_dp_tx_tbl,
3910 .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
3911
3912 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
3913 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
3914 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
3915 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
3916 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
3917 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
3918 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
3919 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
3920
3921 .clk_list = qmp_v4_phy_clk_l,
3922 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
3923 .reset_list = msm8996_usb3phy_reset_l,
3924 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3925 .vreg_list = qmp_phy_vreg_l,
3926 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3927 .regs = qmp_v4_usb3phy_regs_layout,
3928
3929 .has_phy_dp_com_ctrl = true,
3930 .is_dual_lane_phy = true,
3931
3932 .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
3933 .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
3934 .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
3935 .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
3936};
3937
3938static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
3939 .usb_cfg = &sm8250_usb3phy_cfg,
3940 .dp_cfg = &sm8250_dpphy_cfg,
3941};
3942
Manivannan Sadhasivam86ef5a72021-01-11 17:00:10 +0530[diff] [blame]3943static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
3944 .type = PHY_TYPE_USB3,
3945 .nlanes = 1,
3946
3947 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
3948 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
3949 .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
3950 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
3951 .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
3952 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
3953 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
3954 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
3955 .clk_list = qmp_v4_sdx55_usbphy_clk_l,
3956 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
3957 .reset_list = msm8996_usb3phy_reset_l,
3958 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3959 .vreg_list = qmp_phy_vreg_l,
3960 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3961 .regs = qmp_v4_usb3_uniphy_regs_layout,
3962
3963 .start_ctrl = SERDES_START | PCS_START,
3964 .pwrdn_ctrl = SW_PWRDN,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]3965 .phy_status = PHYSTATUS,
Manivannan Sadhasivam86ef5a72021-01-11 17:00:10 +0530[diff] [blame]3966
3967 .has_pwrdn_delay = true,
3968 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3969 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3970};
3971
Manivannan Sadhasivambe0ddb52021-04-27 12:24:00 +0530[diff] [blame]3972static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
3973 .type = PHY_TYPE_PCIE,
3974 .nlanes = 2,
3975
3976 .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
3977 .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
3978 .tx_tbl = sdx55_qmp_pcie_tx_tbl,
3979 .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
3980 .rx_tbl = sdx55_qmp_pcie_rx_tbl,
3981 .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
3982 .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
3983 .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
3984 .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
3985 .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
3986 .clk_list = sdm845_pciephy_clk_l,
3987 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
3988 .reset_list = sdm845_pciephy_reset_l,
3989 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3990 .vreg_list = qmp_phy_vreg_l,
3991 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3992 .regs = sm8250_pcie_regs_layout,
3993
3994 .start_ctrl = PCS_START | SERDES_START,
3995 .pwrdn_ctrl = SW_PWRDN,
3996 .phy_status = PHYSTATUS_4_20,
3997
3998 .is_dual_lane_phy = true,
3999 .has_pwrdn_delay = true,
4000 .pwrdn_delay_min = 995, /* us */
4001 .pwrdn_delay_max = 1005, /* us */
4002};
4003
Vinod Koul0e43fdb2021-02-04 22:28:05 +0530[diff] [blame]4004static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
4005 .type = PHY_TYPE_UFS,
4006 .nlanes = 2,
4007
4008 .serdes_tbl = sm8350_ufsphy_serdes_tbl,
4009 .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
4010 .tx_tbl = sm8350_ufsphy_tx_tbl,
4011 .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
4012 .rx_tbl = sm8350_ufsphy_rx_tbl,
4013 .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
4014 .pcs_tbl = sm8350_ufsphy_pcs_tbl,
4015 .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
4016 .clk_list = sdm845_ufs_phy_clk_l,
4017 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
4018 .vreg_list = qmp_phy_vreg_l,
4019 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4020 .regs = sm8150_ufsphy_regs_layout,
4021
4022 .start_ctrl = SERDES_START,
4023 .pwrdn_ctrl = SW_PWRDN,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]4024 .phy_status = PHYSTATUS,
Vinod Koul0e43fdb2021-02-04 22:28:05 +0530[diff] [blame]4025
4026 .is_dual_lane_phy = true,
4027};
4028
Jack Pham10c744d2021-01-15 09:47:21 -0800[diff] [blame]4029static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
4030 .type = PHY_TYPE_USB3,
4031 .nlanes = 1,
4032
4033 .serdes_tbl = sm8150_usb3_serdes_tbl,
4034 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
4035 .tx_tbl = sm8350_usb3_tx_tbl,
4036 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
4037 .rx_tbl = sm8350_usb3_rx_tbl,
4038 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
4039 .pcs_tbl = sm8350_usb3_pcs_tbl,
4040 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
4041 .clk_list = qmp_v4_sm8250_usbphy_clk_l,
4042 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
4043 .reset_list = msm8996_usb3phy_reset_l,
4044 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4045 .vreg_list = qmp_phy_vreg_l,
4046 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4047 .regs = qmp_v4_usb3phy_regs_layout,
4048
4049 .start_ctrl = SERDES_START | PCS_START,
4050 .pwrdn_ctrl = SW_PWRDN,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]4051 .phy_status = PHYSTATUS,
Jack Pham10c744d2021-01-15 09:47:21 -0800[diff] [blame]4052
4053 .has_pwrdn_delay = true,
4054 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
4055 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
4056
4057 .has_phy_dp_com_ctrl = true,
4058 .is_dual_lane_phy = true,
4059};
4060
4061static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
4062 .type = PHY_TYPE_USB3,
4063 .nlanes = 1,
4064
4065 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
4066 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
4067 .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
4068 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
4069 .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
4070 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
4071 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
4072 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
4073 .clk_list = qmp_v4_phy_clk_l,
4074 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
4075 .reset_list = msm8996_usb3phy_reset_l,
4076 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4077 .vreg_list = qmp_phy_vreg_l,
4078 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4079 .regs = sm8350_usb3_uniphy_regs_layout,
4080
4081 .start_ctrl = SERDES_START | PCS_START,
4082 .pwrdn_ctrl = SW_PWRDN,
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]4083 .phy_status = PHYSTATUS,
Jack Pham10c744d2021-01-15 09:47:21 -0800[diff] [blame]4084
4085 .has_pwrdn_delay = true,
4086 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
4087 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
4088};
4089
Shawn Guo8abe5e72021-09-27 14:48:29 +0800[diff] [blame]4090static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
4091 .type = PHY_TYPE_USB3,
4092 .nlanes = 1,
4093
4094 .serdes_tbl = qcm2290_usb3_serdes_tbl,
4095 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
4096 .tx_tbl = qcm2290_usb3_tx_tbl,
4097 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
4098 .rx_tbl = qcm2290_usb3_rx_tbl,
4099 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
4100 .pcs_tbl = qcm2290_usb3_pcs_tbl,
4101 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
4102 .clk_list = qcm2290_usb3phy_clk_l,
4103 .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
4104 .reset_list = qcm2290_usb3phy_reset_l,
4105 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
4106 .vreg_list = qmp_phy_vreg_l,
4107 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4108 .regs = qcm2290_usb3phy_regs_layout,
4109
4110 .start_ctrl = SERDES_START | PCS_START,
4111 .pwrdn_ctrl = SW_PWRDN,
4112 .phy_status = PHYSTATUS,
4113
4114 .is_dual_lane_phy = true,
4115};
4116
Jonathan Marek5dcbc712020-05-23 22:14:13 -0400[diff] [blame]4117static void qcom_qmp_phy_configure_lane(void __iomem *base,
4118 const unsigned int *regs,
4119 const struct qmp_phy_init_tbl tbl[],
4120 int num,
4121 u8 lane_mask)
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4122{
4123 int i;
4124 const struct qmp_phy_init_tbl *t = tbl;
4125
4126 if (!t)
4127 return;
4128
4129 for (i = 0; i < num; i++, t++) {
Jonathan Marek5dcbc712020-05-23 22:14:13 -0400[diff] [blame]4130 if (!(t->lane_mask & lane_mask))
4131 continue;
4132
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4133 if (t->in_layout)
4134 writel(t->val, base + regs[t->offset]);
4135 else
4136 writel(t->val, base + t->offset);
4137 }
4138}
4139
Jonathan Marek5dcbc712020-05-23 22:14:13 -0400[diff] [blame]4140static void qcom_qmp_phy_configure(void __iomem *base,
4141 const unsigned int *regs,
4142 const struct qmp_phy_init_tbl tbl[],
4143 int num)
4144{
4145 qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
4146}
4147
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4148static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
4149{
4150 struct qcom_qmp *qmp = qphy->qmp;
4151 const struct qmp_phy_cfg *cfg = qphy->cfg;
4152 void __iomem *serdes = qphy->serdes;
4153 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4154 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
4155 int serdes_tbl_num = cfg->serdes_tbl_num;
4156 int ret;
4157
4158 qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]4159 if (cfg->serdes_tbl_sec)
4160 qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
4161 cfg->serdes_tbl_num_sec);
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4162
4163 if (cfg->type == PHY_TYPE_DP) {
4164 switch (dp_opts->link_rate) {
4165 case 1620:
4166 qcom_qmp_phy_configure(serdes, cfg->regs,
4167 cfg->serdes_tbl_rbr,
4168 cfg->serdes_tbl_rbr_num);
4169 break;
4170 case 2700:
4171 qcom_qmp_phy_configure(serdes, cfg->regs,
4172 cfg->serdes_tbl_hbr,
4173 cfg->serdes_tbl_hbr_num);
4174 break;
4175 case 5400:
4176 qcom_qmp_phy_configure(serdes, cfg->regs,
4177 cfg->serdes_tbl_hbr2,
4178 cfg->serdes_tbl_hbr2_num);
4179 break;
4180 case 8100:
4181 qcom_qmp_phy_configure(serdes, cfg->regs,
4182 cfg->serdes_tbl_hbr3,
4183 cfg->serdes_tbl_hbr3_num);
4184 break;
4185 default:
4186 /* Other link rates aren't supported */
4187 return -EINVAL;
4188 }
4189 }
4190
4191
4192 if (cfg->has_phy_com_ctrl) {
4193 void __iomem *status;
4194 unsigned int mask, val;
4195
4196 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
4197 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
4198 SERDES_START | PCS_START);
4199
4200 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
4201 mask = cfg->mask_com_pcs_ready;
4202
4203 ret = readl_poll_timeout(status, val, (val & mask), 10,
4204 PHY_INIT_COMPLETE_TIMEOUT);
4205 if (ret) {
4206 dev_err(qmp->dev,
4207 "phy common block init timed-out\n");
4208 return ret;
4209 }
4210 }
4211
4212 return 0;
4213}
4214
Dmitry Baryshkov5f0d28f2021-03-31 18:16:10 +0300[diff] [blame]4215static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4216{
4217 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4218 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
Dmitry Baryshkov5c393912021-03-31 18:16:11 +0300[diff] [blame]4219 qphy->pcs + QSERDES_DP_PHY_PD_CTL);
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4220
4221 /* Turn on BIAS current for PHY/PLL */
4222 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
4223 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
4224 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
4225
Dmitry Baryshkov5c393912021-03-31 18:16:11 +0300[diff] [blame]4226 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4227
4228 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4229 DP_PHY_PD_CTL_LANE_0_1_PWRDN |
4230 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
4231 DP_PHY_PD_CTL_DP_CLAMP_EN,
Dmitry Baryshkov5c393912021-03-31 18:16:11 +0300[diff] [blame]4232 qphy->pcs + QSERDES_DP_PHY_PD_CTL);
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4233
4234 writel(QSERDES_V3_COM_BIAS_EN |
4235 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
4236 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
4237 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
4238 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
4239
Dmitry Baryshkov5c393912021-03-31 18:16:11 +0300[diff] [blame]4240 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
4241 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4242 writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4243 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
4244 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
4245 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
4246 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
4247 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
4248 writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
4249 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4250 qphy->dp_aux_cfg = 0;
4251
4252 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
4253 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
4254 PHY_AUX_REQ_ERR_MASK,
4255 qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
4256}
4257
Kuogee Hsieh3f2ec772021-03-16 10:12:41 -0700[diff] [blame]4258static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
4259 { 0x00, 0x0c, 0x15, 0x1a },
4260 { 0x02, 0x0e, 0x16, 0xff },
4261 { 0x02, 0x11, 0xff, 0xff },
4262 { 0x04, 0xff, 0xff, 0xff }
4263};
4264
4265static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
4266 { 0x02, 0x12, 0x16, 0x1a },
4267 { 0x09, 0x19, 0x1f, 0xff },
4268 { 0x10, 0x1f, 0xff, 0xff },
4269 { 0x1f, 0xff, 0xff, 0xff }
4270};
4271
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4272static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
4273 { 0x00, 0x0c, 0x14, 0x19 },
4274 { 0x00, 0x0b, 0x12, 0xff },
4275 { 0x00, 0x0b, 0xff, 0xff },
4276 { 0x04, 0xff, 0xff, 0xff }
4277};
4278
4279static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
4280 { 0x08, 0x0f, 0x16, 0x1f },
4281 { 0x11, 0x1e, 0x1f, 0xff },
4282 { 0x19, 0x1f, 0xff, 0xff },
4283 { 0x1f, 0xff, 0xff, 0xff }
4284};
4285
Dmitry Baryshkovaff188f2021-03-31 18:16:12 +0300[diff] [blame]4286static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
4287 unsigned int drv_lvl_reg, unsigned int emp_post_reg)
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4288{
4289 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4290 unsigned int v_level = 0, p_level = 0;
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4291 u8 voltage_swing_cfg, pre_emphasis_cfg;
4292 int i;
4293
4294 for (i = 0; i < dp_opts->lanes; i++) {
4295 v_level = max(v_level, dp_opts->voltage[i]);
4296 p_level = max(p_level, dp_opts->pre[i]);
4297 }
4298
Kuogee Hsieh3f2ec772021-03-16 10:12:41 -0700[diff] [blame]4299 if (dp_opts->link_rate <= 2700) {
4300 voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
4301 pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
4302 } else {
4303 voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
4304 pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
4305 }
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4306
4307 /* TODO: Move check to config check */
4308 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
Dmitry Baryshkovaff188f2021-03-31 18:16:12 +0300[diff] [blame]4309 return -EINVAL;
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4310
4311 /* Enable MUX to use Cursor values from these registers */
4312 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
4313 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
4314
Dmitry Baryshkovaff188f2021-03-31 18:16:12 +0300[diff] [blame]4315 writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
4316 writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
4317 writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
4318 writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
4319
4320 return 0;
4321}
4322
4323static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
4324{
4325 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4326 u32 bias_en, drvr_en;
4327
4328 if (qcom_qmp_phy_configure_dp_swing(qphy,
4329 QSERDES_V3_TX_TX_DRV_LVL,
4330 QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
4331 return;
4332
4333 if (dp_opts->lanes == 1) {
4334 bias_en = 0x3e;
4335 drvr_en = 0x13;
4336 } else {
4337 bias_en = 0x3f;
4338 drvr_en = 0x10;
4339 }
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4340
4341 writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
4342 writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
4343 writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
4344 writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
4345}
4346
Dmitry Baryshkovaff188f2021-03-31 18:16:12 +0300[diff] [blame]4347static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4348{
Dmitry Baryshkovaff188f2021-03-31 18:16:12 +0300[diff] [blame]4349 u32 val;
4350 bool reverse = false;
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4351
4352 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4353 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
4354
4355 /*
4356 * TODO: Assume orientation is CC1 for now and two lanes, need to
4357 * use type-c connector to understand orientation and lanes.
4358 *
4359 * Otherwise val changes to be like below if this code understood
4360 * the orientation of the type-c cable.
4361 *
4362 * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
4363 * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
4364 * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
4365 * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
4366 * if (orientation == ORIENTATION_CC2)
4367 * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
4368 */
4369 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
Dmitry Baryshkov5c393912021-03-31 18:16:11 +0300[diff] [blame]4370 writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4371
Dmitry Baryshkov5c393912021-03-31 18:16:11 +0300[diff] [blame]4372 writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
Dmitry Baryshkovaff188f2021-03-31 18:16:12 +0300[diff] [blame]4373
4374 return reverse;
4375}
4376
4377static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
4378{
4379 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
4380 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4381 u32 phy_vco_div, status;
4382 unsigned long pixel_freq;
4383
4384 qcom_qmp_phy_configure_dp_mode(qphy);
4385
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4386 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
4387 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
4388
4389 switch (dp_opts->link_rate) {
4390 case 1620:
4391 phy_vco_div = 0x1;
4392 pixel_freq = 1620000000UL / 2;
4393 break;
4394 case 2700:
4395 phy_vco_div = 0x1;
4396 pixel_freq = 2700000000UL / 2;
4397 break;
4398 case 5400:
4399 phy_vco_div = 0x2;
4400 pixel_freq = 5400000000UL / 4;
4401 break;
4402 case 8100:
4403 phy_vco_div = 0x0;
4404 pixel_freq = 8100000000UL / 6;
4405 break;
4406 default:
4407 /* Other link rates aren't supported */
4408 return -EINVAL;
4409 }
4410 writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
4411
4412 clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
4413 clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
4414
Dmitry Baryshkov5c393912021-03-31 18:16:11 +0300[diff] [blame]4415 writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4416 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4417 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
4418 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4419 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4420
4421 writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
4422
4423 if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
4424 status,
4425 ((status & BIT(0)) > 0),
4426 500,
4427 10000))
4428 return -ETIMEDOUT;
4429
Dmitry Baryshkov5c393912021-03-31 18:16:11 +0300[diff] [blame]4430 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4431
4432 if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
4433 status,
4434 ((status & BIT(1)) > 0),
4435 500,
4436 10000))
4437 return -ETIMEDOUT;
4438
Dmitry Baryshkov5c393912021-03-31 18:16:11 +0300[diff] [blame]4439 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4440 udelay(2000);
Dmitry Baryshkov5c393912021-03-31 18:16:11 +0300[diff] [blame]4441 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4442
4443 return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
4444 status,
4445 ((status & BIT(1)) > 0),
4446 500,
4447 10000);
4448}
4449
4450/*
4451 * We need to calibrate the aux setting here as many times
4452 * as the caller tries
4453 */
Dmitry Baryshkov5f0d28f2021-03-31 18:16:10 +0300[diff] [blame]4454static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4455{
Colin Ian King43851902021-02-04 18:03:13 +0000[diff] [blame]4456 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4457 u8 val;
4458
4459 qphy->dp_aux_cfg++;
4460 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
4461 val = cfg1_settings[qphy->dp_aux_cfg];
4462
Dmitry Baryshkov5c393912021-03-31 18:16:11 +0300[diff] [blame]4463 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4464
4465 return 0;
4466}
4467
Dmitry Baryshkovaff188f2021-03-31 18:16:12 +0300[diff] [blame]4468static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
4469{
4470 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4471 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
4472 qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4473
4474 /* Turn on BIAS current for PHY/PLL */
4475 writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
4476
4477 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
4478 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4479 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4480 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
4481 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
4482 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
4483 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
4484 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
4485 writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
4486 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
4487 qphy->dp_aux_cfg = 0;
4488
4489 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
4490 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
4491 PHY_AUX_REQ_ERR_MASK,
4492 qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
4493}
4494
4495static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
4496{
4497 /* Program default values before writing proper values */
4498 writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
4499 writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
4500
4501 writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4502 writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4503
4504 qcom_qmp_phy_configure_dp_swing(qphy,
4505 QSERDES_V4_TX_TX_DRV_LVL,
4506 QSERDES_V4_TX_TX_EMP_POST1_LVL);
4507}
4508
4509static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
4510{
4511 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
4512 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4513 u32 phy_vco_div, status;
4514 unsigned long pixel_freq;
4515 u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
4516 bool reverse;
4517
4518 writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
4519
4520 reverse = qcom_qmp_phy_configure_dp_mode(qphy);
4521
4522 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4523 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4524
4525 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
4526 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
4527
4528 switch (dp_opts->link_rate) {
4529 case 1620:
4530 phy_vco_div = 0x1;
4531 pixel_freq = 1620000000UL / 2;
4532 break;
4533 case 2700:
4534 phy_vco_div = 0x1;
4535 pixel_freq = 2700000000UL / 2;
4536 break;
4537 case 5400:
4538 phy_vco_div = 0x2;
4539 pixel_freq = 5400000000UL / 4;
4540 break;
4541 case 8100:
4542 phy_vco_div = 0x0;
4543 pixel_freq = 8100000000UL / 6;
4544 break;
4545 default:
4546 /* Other link rates aren't supported */
4547 return -EINVAL;
4548 }
4549 writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
4550
4551 clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
4552 clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
4553
4554 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4555 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
4556 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4557 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
4558
4559 writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
4560
4561 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
4562 status,
4563 ((status & BIT(0)) > 0),
4564 500,
4565 10000))
4566 return -ETIMEDOUT;
4567
4568 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
4569 status,
4570 ((status & BIT(0)) > 0),
4571 500,
4572 10000))
4573 return -ETIMEDOUT;
4574
4575 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
4576 status,
4577 ((status & BIT(1)) > 0),
4578 500,
4579 10000))
4580 return -ETIMEDOUT;
4581
4582 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4583
4584 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
4585 status,
4586 ((status & BIT(0)) > 0),
4587 500,
4588 10000))
4589 return -ETIMEDOUT;
4590
4591 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
4592 status,
4593 ((status & BIT(1)) > 0),
4594 500,
4595 10000))
4596 return -ETIMEDOUT;
4597
4598 /*
4599 * At least for 7nm DP PHY this has to be done after enabling link
4600 * clock.
4601 */
4602
4603 if (dp_opts->lanes == 1) {
4604 bias0_en = reverse ? 0x3e : 0x15;
4605 bias1_en = reverse ? 0x15 : 0x3e;
4606 drvr0_en = reverse ? 0x13 : 0x10;
4607 drvr1_en = reverse ? 0x10 : 0x13;
4608 } else if (dp_opts->lanes == 2) {
4609 bias0_en = reverse ? 0x3f : 0x15;
4610 bias1_en = reverse ? 0x15 : 0x3f;
4611 drvr0_en = 0x10;
4612 drvr1_en = 0x10;
4613 } else {
4614 bias0_en = 0x3f;
4615 bias1_en = 0x3f;
4616 drvr0_en = 0x10;
4617 drvr1_en = 0x10;
4618 }
4619
4620 writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
4621 writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
4622 writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
4623 writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
4624
4625 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
4626 udelay(2000);
4627 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4628
4629 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
4630 status,
4631 ((status & BIT(1)) > 0),
4632 500,
4633 10000))
4634 return -ETIMEDOUT;
4635
4636 writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
4637 writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
4638
4639 writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
4640 writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
4641
4642 writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4643 writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4644
4645 return 0;
4646}
4647
4648/*
4649 * We need to calibrate the aux setting here as many times
4650 * as the caller tries
4651 */
4652static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
4653{
4654 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
4655 u8 val;
4656
4657 qphy->dp_aux_cfg++;
4658 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
4659 val = cfg1_settings[qphy->dp_aux_cfg];
4660
4661 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4662
4663 return 0;
4664}
4665
Dmitry Baryshkov5f0d28f2021-03-31 18:16:10 +0300[diff] [blame]4666static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
4667{
4668 const struct phy_configure_opts_dp *dp_opts = &opts->dp;
4669 struct qmp_phy *qphy = phy_get_drvdata(phy);
4670 const struct qmp_phy_cfg *cfg = qphy->cfg;
4671
4672 memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
4673 if (qphy->dp_opts.set_voltages) {
4674 cfg->configure_dp_tx(qphy);
4675 qphy->dp_opts.set_voltages = 0;
4676 }
4677
4678 return 0;
4679}
4680
4681static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
4682{
4683 struct qmp_phy *qphy = phy_get_drvdata(phy);
4684 const struct qmp_phy_cfg *cfg = qphy->cfg;
4685
4686 if (cfg->calibrate_dp_phy)
4687 return cfg->calibrate_dp_phy(qphy);
4688
4689 return 0;
4690}
4691
Can Guo0d582802018-09-20 21:27:54 -0700[diff] [blame]4692static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4693{
Can Guo0d582802018-09-20 21:27:54 -0700[diff] [blame]4694 struct qcom_qmp *qmp = qphy->qmp;
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]4695 const struct qmp_phy_cfg *cfg = qphy->cfg;
4696 void __iomem *serdes = qphy->serdes;
Can Guo0d582802018-09-20 21:27:54 -0700[diff] [blame]4697 void __iomem *pcs = qphy->pcs;
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]4698 void __iomem *dp_com = qmp->dp_com;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4699 int ret, i;
4700
4701 mutex_lock(&qmp->phy_mutex);
4702 if (qmp->init_count++) {
4703 mutex_unlock(&qmp->phy_mutex);
4704 return 0;
4705 }
4706
Manu Gautam717dab92018-01-16 16:26:58 +0530[diff] [blame]4707 /* turn on regulator supplies */
4708 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
4709 if (ret) {
4710 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
4711 goto err_reg_enable;
4712 }
4713
Manu Gautamc6549f02018-01-16 16:27:00 +0530[diff] [blame]4714 for (i = 0; i < cfg->num_resets; i++) {
4715 ret = reset_control_assert(qmp->resets[i]);
4716 if (ret) {
4717 dev_err(qmp->dev, "%s reset assert failed\n",
4718 cfg->reset_list[i]);
4719 goto err_rst_assert;
4720 }
Manu Gautam717dab92018-01-16 16:26:58 +0530[diff] [blame]4721 }
4722
Manu Gautamc6549f02018-01-16 16:27:00 +0530[diff] [blame]4723 for (i = cfg->num_resets - 1; i >= 0; i--) {
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4724 ret = reset_control_deassert(qmp->resets[i]);
4725 if (ret) {
4726 dev_err(qmp->dev, "%s reset deassert failed\n",
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]4727 qphy->cfg->reset_list[i]);
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4728 goto err_rst;
4729 }
4730 }
4731
Manu Gautamc6549f02018-01-16 16:27:00 +0530[diff] [blame]4732 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
Chunfeng Yun4bbe33f2021-05-17 13:37:21 +0800[diff] [blame]4733 if (ret)
Manu Gautamc6549f02018-01-16 16:27:00 +0530[diff] [blame]4734 goto err_rst;
Manu Gautamc6549f02018-01-16 16:27:00 +0530[diff] [blame]4735
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]4736 if (cfg->has_phy_dp_com_ctrl) {
4737 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
4738 SW_PWRDN);
4739 /* override hardware control for reset of qmp phy */
4740 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
4741 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
4742 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
4743
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4744 /* Default type-c orientation, i.e CC1 */
4745 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
4746
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]4747 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
4748 USB3_MODE | DP_MODE);
4749
4750 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
4751 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
4752 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
4753 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4754
4755 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
4756 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]4757 }
4758
Wesley Chenge4d8b052020-05-04 16:54:26 -0700[diff] [blame]4759 if (cfg->has_phy_com_ctrl) {
Can Guo0d582802018-09-20 21:27:54 -0700[diff] [blame]4760 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
4761 SW_PWRDN);
Wesley Chenge4d8b052020-05-04 16:54:26 -0700[diff] [blame]4762 } else {
4763 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
4764 qphy_setbits(pcs,
4765 cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
4766 cfg->pwrdn_ctrl);
4767 else
4768 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
4769 cfg->pwrdn_ctrl);
4770 }
Can Guo0d582802018-09-20 21:27:54 -0700[diff] [blame]4771
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4772 mutex_unlock(&qmp->phy_mutex);
4773
4774 return 0;
4775
Manu Gautamc6549f02018-01-16 16:27:00 +0530[diff] [blame]4776err_rst:
4777 while (++i < cfg->num_resets)
4778 reset_control_assert(qmp->resets[i]);
4779err_rst_assert:
Manu Gautam717dab92018-01-16 16:26:58 +0530[diff] [blame]4780 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
4781err_reg_enable:
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4782 mutex_unlock(&qmp->phy_mutex);
Vivek Gautam8387c572017-06-20 11:27:18 +0530[diff] [blame]4783
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4784 return ret;
4785}
4786
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]4787static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4788{
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]4789 struct qcom_qmp *qmp = qphy->qmp;
4790 const struct qmp_phy_cfg *cfg = qphy->cfg;
4791 void __iomem *serdes = qphy->serdes;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4792 int i = cfg->num_resets;
4793
4794 mutex_lock(&qmp->phy_mutex);
4795 if (--qmp->init_count) {
4796 mutex_unlock(&qmp->phy_mutex);
4797 return 0;
4798 }
4799
Evan Greenc9b58972019-03-21 10:17:59 -0700[diff] [blame]4800 reset_control_assert(qmp->ufs_reset);
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4801 if (cfg->has_phy_com_ctrl) {
4802 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
4803 SERDES_START | PCS_START);
4804 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
4805 SW_RESET);
4806 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
4807 SW_PWRDN);
4808 }
4809
4810 while (--i >= 0)
4811 reset_control_assert(qmp->resets[i]);
4812
Manu Gautam717dab92018-01-16 16:26:58 +0530[diff] [blame]4813 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
4814
4815 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
4816
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4817 mutex_unlock(&qmp->phy_mutex);
4818
4819 return 0;
4820}
4821
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4822static int qcom_qmp_phy_init(struct phy *phy)
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4823{
4824 struct qmp_phy *qphy = phy_get_drvdata(phy);
4825 struct qcom_qmp *qmp = qphy->qmp;
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]4826 const struct qmp_phy_cfg *cfg = qphy->cfg;
Vivek Gautam10939b12018-01-16 16:26:57 +0530[diff] [blame]4827 int ret;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4828 dev_vdbg(qmp->dev, "Initializing QMP phy\n");
4829
Evan Greenc9b58972019-03-21 10:17:59 -0700[diff] [blame]4830 if (cfg->no_pcs_sw_reset) {
4831 /*
4832 * Get UFS reset, which is delayed until now to avoid a
4833 * circular dependency where UFS needs its PHY, but the PHY
4834 * needs this UFS reset.
4835 */
4836 if (!qmp->ufs_reset) {
4837 qmp->ufs_reset =
4838 devm_reset_control_get_exclusive(qmp->dev,
4839 "ufsphy");
4840
4841 if (IS_ERR(qmp->ufs_reset)) {
4842 ret = PTR_ERR(qmp->ufs_reset);
4843 dev_err(qmp->dev,
4844 "failed to get UFS reset: %d\n",
4845 ret);
4846
4847 qmp->ufs_reset = NULL;
4848 return ret;
4849 }
4850 }
4851
4852 ret = reset_control_assert(qmp->ufs_reset);
4853 if (ret)
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4854 return ret;
Evan Greenc9b58972019-03-21 10:17:59 -0700[diff] [blame]4855 }
4856
Can Guo0d582802018-09-20 21:27:54 -0700[diff] [blame]4857 ret = qcom_qmp_phy_com_init(qphy);
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4858 if (ret)
Manu Gautam717dab92018-01-16 16:26:58 +0530[diff] [blame]4859 return ret;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4860
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4861 if (cfg->type == PHY_TYPE_DP)
Dmitry Baryshkov5f0d28f2021-03-31 18:16:10 +0300[diff] [blame]4862 cfg->dp_aux_init(qphy);
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4863
4864 return 0;
4865}
4866
4867static int qcom_qmp_phy_power_on(struct phy *phy)
4868{
4869 struct qmp_phy *qphy = phy_get_drvdata(phy);
4870 struct qcom_qmp *qmp = qphy->qmp;
4871 const struct qmp_phy_cfg *cfg = qphy->cfg;
4872 void __iomem *tx = qphy->tx;
4873 void __iomem *rx = qphy->rx;
4874 void __iomem *pcs = qphy->pcs;
4875 void __iomem *pcs_misc = qphy->pcs_misc;
4876 void __iomem *status;
4877 unsigned int mask, val, ready;
4878 int ret;
4879
4880 qcom_qmp_phy_serdes_init(qphy);
4881
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4882 if (cfg->has_lane_rst) {
4883 ret = reset_control_deassert(qphy->lane_rst);
4884 if (ret) {
4885 dev_err(qmp->dev, "lane%d reset deassert failed\n",
4886 qphy->index);
4887 goto err_lane_rst;
4888 }
4889 }
4890
Manu Gautamfdf37e12018-05-03 02:36:09 +0530[diff] [blame]4891 ret = clk_prepare_enable(qphy->pipe_clk);
4892 if (ret) {
4893 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
4894 goto err_clk_enable;
4895 }
4896
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4897 /* Tx, Rx, and PCS configurations */
Jonathan Marek5dcbc712020-05-23 22:14:13 -0400[diff] [blame]4898 qcom_qmp_phy_configure_lane(tx, cfg->regs,
4899 cfg->tx_tbl, cfg->tx_tbl_num, 1);
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]4900 if (cfg->tx_tbl_sec)
4901 qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
4902 cfg->tx_tbl_num_sec, 1);
4903
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]4904 /* Configuration for other LANE for USB-DP combo PHY */
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]4905 if (cfg->is_dual_lane_phy) {
Jonathan Marek5dcbc712020-05-23 22:14:13 -0400[diff] [blame]4906 qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
4907 cfg->tx_tbl, cfg->tx_tbl_num, 2);
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]4908 if (cfg->tx_tbl_sec)
4909 qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
4910 cfg->tx_tbl_sec,
4911 cfg->tx_tbl_num_sec, 2);
4912 }
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]4913
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4914 /* Configure special DP tx tunings */
4915 if (cfg->type == PHY_TYPE_DP)
Dmitry Baryshkov5f0d28f2021-03-31 18:16:10 +0300[diff] [blame]4916 cfg->configure_dp_tx(qphy);
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4917
Jonathan Marek5dcbc712020-05-23 22:14:13 -0400[diff] [blame]4918 qcom_qmp_phy_configure_lane(rx, cfg->regs,
4919 cfg->rx_tbl, cfg->rx_tbl_num, 1);
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]4920 if (cfg->rx_tbl_sec)
4921 qcom_qmp_phy_configure_lane(rx, cfg->regs,
4922 cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4923
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]4924 if (cfg->is_dual_lane_phy) {
Jonathan Marek5dcbc712020-05-23 22:14:13 -0400[diff] [blame]4925 qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
4926 cfg->rx_tbl, cfg->rx_tbl_num, 2);
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]4927 if (cfg->rx_tbl_sec)
4928 qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
4929 cfg->rx_tbl_sec,
4930 cfg->rx_tbl_num_sec, 2);
4931 }
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]4932
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4933 /* Configure link rate, swing, etc. */
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]4934 if (cfg->type == PHY_TYPE_DP) {
Dmitry Baryshkov5f0d28f2021-03-31 18:16:10 +0300[diff] [blame]4935 cfg->configure_dp_phy(qphy);
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]4936 } else {
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4937 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]4938 if (cfg->pcs_tbl_sec)
4939 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
4940 cfg->pcs_tbl_num_sec);
4941 }
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4942
Evan Greenc9b58972019-03-21 10:17:59 -0700[diff] [blame]4943 ret = reset_control_deassert(qmp->ufs_reset);
4944 if (ret)
4945 goto err_lane_rst;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4946
Bjorn Andersson421c9a02020-01-06 00:18:20 -0800[diff] [blame]4947 qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
4948 cfg->pcs_misc_tbl_num);
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]4949 if (cfg->pcs_misc_tbl_sec)
4950 qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
4951 cfg->pcs_misc_tbl_num_sec);
Bjorn Andersson421c9a02020-01-06 00:18:20 -0800[diff] [blame]4952
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4953 /*
4954 * Pull out PHY from POWER DOWN state.
4955 * This is active low enable signal to power-down PHY.
4956 */
Can Guo0d582802018-09-20 21:27:54 -0700[diff] [blame]4957 if(cfg->type == PHY_TYPE_PCIE)
4958 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4959
4960 if (cfg->has_pwrdn_delay)
4961 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
4962
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4963 if (cfg->type != PHY_TYPE_DP) {
4964 /* Pull PHY out of reset state */
4965 if (!cfg->no_pcs_sw_reset)
4966 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
4967 /* start SerDes and Phy-Coding-Sublayer */
4968 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
Evan Green3f6d1762019-03-21 10:18:00 -0700[diff] [blame]4969
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4970 if (cfg->type == PHY_TYPE_UFS) {
4971 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
4972 mask = PCS_READY;
4973 ready = PCS_READY;
4974 } else {
4975 status = pcs + cfg->regs[QPHY_PCS_STATUS];
Manivannan Sadhasivam952b7022021-04-27 12:23:59 +0530[diff] [blame]4976 mask = cfg->phy_status;
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4977 ready = 0;
4978 }
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4979
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4980 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
4981 PHY_INIT_COMPLETE_TIMEOUT);
4982 if (ret) {
4983 dev_err(qmp->dev, "phy initialization timed-out\n");
4984 goto err_pcs_ready;
4985 }
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4986 }
Evan Green3f6d1762019-03-21 10:18:00 -0700[diff] [blame]4987 return 0;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4988
4989err_pcs_ready:
Manu Gautamfdf37e12018-05-03 02:36:09 +0530[diff] [blame]4990 clk_disable_unprepare(qphy->pipe_clk);
4991err_clk_enable:
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4992 if (cfg->has_lane_rst)
4993 reset_control_assert(qphy->lane_rst);
4994err_lane_rst:
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4995 return ret;
4996}
4997
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]4998static int qcom_qmp_phy_power_off(struct phy *phy)
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]4999{
5000 struct qmp_phy *qphy = phy_get_drvdata(phy);
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5001 const struct qmp_phy_cfg *cfg = qphy->cfg;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5002
Vivek Gautamf8ba22a32018-01-16 16:26:56 +0530[diff] [blame]5003 clk_disable_unprepare(qphy->pipe_clk);
5004
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5005 if (cfg->type == PHY_TYPE_DP) {
5006 /* Assert DP PHY power down */
Dmitry Baryshkov5c393912021-03-31 18:16:11 +0300[diff] [blame]5007 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
Wesley Chenge4d8b052020-05-04 16:54:26 -0700[diff] [blame]5008 } else {
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5009 /* PHY reset */
5010 if (!cfg->no_pcs_sw_reset)
5011 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
5012
5013 /* stop SerDes and Phy-Coding-Sublayer */
5014 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
5015
5016 /* Put PHY into POWER DOWN state: active low */
5017 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
5018 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
5019 cfg->pwrdn_ctrl);
5020 } else {
5021 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
5022 cfg->pwrdn_ctrl);
5023 }
Wesley Chenge4d8b052020-05-04 16:54:26 -0700[diff] [blame]5024 }
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5025
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5026 return 0;
5027}
5028
5029static int qcom_qmp_phy_exit(struct phy *phy)
5030{
5031 struct qmp_phy *qphy = phy_get_drvdata(phy);
5032 const struct qmp_phy_cfg *cfg = qphy->cfg;
5033
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5034 if (cfg->has_lane_rst)
5035 reset_control_assert(qphy->lane_rst);
5036
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5037 qcom_qmp_phy_com_exit(qphy);
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5038
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5039 return 0;
5040}
5041
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5042static int qcom_qmp_phy_enable(struct phy *phy)
5043{
5044 int ret;
5045
5046 ret = qcom_qmp_phy_init(phy);
5047 if (ret)
5048 return ret;
5049
5050 ret = qcom_qmp_phy_power_on(phy);
5051 if (ret)
5052 qcom_qmp_phy_exit(phy);
5053
5054 return ret;
5055}
5056
5057static int qcom_qmp_phy_disable(struct phy *phy)
5058{
5059 int ret;
5060
5061 ret = qcom_qmp_phy_power_off(phy);
5062 if (ret)
5063 return ret;
5064 return qcom_qmp_phy_exit(phy);
5065}
5066
Grygorii Strashko79a5a182018-11-19 19:24:20 -0600[diff] [blame]5067static int qcom_qmp_phy_set_mode(struct phy *phy,
5068 enum phy_mode mode, int submode)
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5069{
5070 struct qmp_phy *qphy = phy_get_drvdata(phy);
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5071
Stephen Boyddadcf992020-09-16 16:11:54 -0700[diff] [blame]5072 qphy->mode = mode;
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5073
5074 return 0;
5075}
5076
5077static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
5078{
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5079 const struct qmp_phy_cfg *cfg = qphy->cfg;
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5080 void __iomem *pcs = qphy->pcs;
5081 void __iomem *pcs_misc = qphy->pcs_misc;
5082 u32 intr_mask;
5083
Stephen Boyddadcf992020-09-16 16:11:54 -0700[diff] [blame]5084 if (qphy->mode == PHY_MODE_USB_HOST_SS ||
5085 qphy->mode == PHY_MODE_USB_DEVICE_SS)
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5086 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
5087 else
5088 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
5089
5090 /* Clear any pending interrupts status */
5091 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
5092 /* Writing 1 followed by 0 clears the interrupt */
5093 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
5094
5095 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
5096 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
5097
5098 /* Enable required PHY autonomous mode interrupts */
5099 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
5100
5101 /* Enable i/o clamp_n for autonomous mode */
5102 if (pcs_misc)
5103 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
5104}
5105
5106static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
5107{
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5108 const struct qmp_phy_cfg *cfg = qphy->cfg;
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5109 void __iomem *pcs = qphy->pcs;
5110 void __iomem *pcs_misc = qphy->pcs_misc;
5111
5112 /* Disable i/o clamp_n on resume for normal mode */
5113 if (pcs_misc)
5114 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
5115
5116 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
5117 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
5118
5119 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
5120 /* Writing 1 followed by 0 clears the interrupt */
5121 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
5122}
5123
5124static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
5125{
5126 struct qcom_qmp *qmp = dev_get_drvdata(dev);
5127 struct qmp_phy *qphy = qmp->phys[0];
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5128 const struct qmp_phy_cfg *cfg = qphy->cfg;
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5129
Stephen Boyddadcf992020-09-16 16:11:54 -0700[diff] [blame]5130 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5131
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5132 /* Supported only for USB3 PHY and luckily USB3 is the first phy */
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5133 if (cfg->type != PHY_TYPE_USB3)
5134 return 0;
5135
Stephen Boyde4bc7de2020-09-16 16:11:55 -0700[diff] [blame]5136 if (!qmp->init_count) {
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5137 dev_vdbg(dev, "PHY not initialized, bailing out\n");
5138 return 0;
5139 }
5140
5141 qcom_qmp_phy_enable_autonomous_mode(qphy);
5142
5143 clk_disable_unprepare(qphy->pipe_clk);
5144 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
5145
5146 return 0;
5147}
5148
5149static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
5150{
5151 struct qcom_qmp *qmp = dev_get_drvdata(dev);
5152 struct qmp_phy *qphy = qmp->phys[0];
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5153 const struct qmp_phy_cfg *cfg = qphy->cfg;
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5154 int ret = 0;
5155
Stephen Boyddadcf992020-09-16 16:11:54 -0700[diff] [blame]5156 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5157
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5158 /* Supported only for USB3 PHY and luckily USB3 is the first phy */
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5159 if (cfg->type != PHY_TYPE_USB3)
5160 return 0;
5161
Stephen Boyde4bc7de2020-09-16 16:11:55 -0700[diff] [blame]5162 if (!qmp->init_count) {
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5163 dev_vdbg(dev, "PHY not initialized, bailing out\n");
5164 return 0;
5165 }
5166
5167 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
Chunfeng Yun4bbe33f2021-05-17 13:37:21 +0800[diff] [blame]5168 if (ret)
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5169 return ret;
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5170
5171 ret = clk_prepare_enable(qphy->pipe_clk);
5172 if (ret) {
5173 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
5174 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
5175 return ret;
5176 }
5177
5178 qcom_qmp_phy_disable_autonomous_mode(qphy);
5179
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5180 return 0;
5181}
5182
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5183static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5184{
5185 struct qcom_qmp *qmp = dev_get_drvdata(dev);
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5186 int num = cfg->num_vregs;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5187 int i;
5188
Fengguang Wu9605bc42017-05-16 20:41:45 +0800[diff] [blame]5189 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5190 if (!qmp->vregs)
5191 return -ENOMEM;
5192
5193 for (i = 0; i < num; i++)
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5194 qmp->vregs[i].supply = cfg->vreg_list[i];
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5195
5196 return devm_regulator_bulk_get(dev, num, qmp->vregs);
5197}
5198
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5199static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5200{
5201 struct qcom_qmp *qmp = dev_get_drvdata(dev);
5202 int i;
5203
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5204 qmp->resets = devm_kcalloc(dev, cfg->num_resets,
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5205 sizeof(*qmp->resets), GFP_KERNEL);
5206 if (!qmp->resets)
5207 return -ENOMEM;
5208
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5209 for (i = 0; i < cfg->num_resets; i++) {
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5210 struct reset_control *rst;
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5211 const char *name = cfg->reset_list[i];
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5212
5213 rst = devm_reset_control_get(dev, name);
5214 if (IS_ERR(rst)) {
5215 dev_err(dev, "failed to get %s reset\n", name);
5216 return PTR_ERR(rst);
5217 }
5218 qmp->resets[i] = rst;
5219 }
5220
5221 return 0;
5222}
5223
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5224static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5225{
5226 struct qcom_qmp *qmp = dev_get_drvdata(dev);
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5227 int num = cfg->num_clks;
Vivek Gautam10939b12018-01-16 16:26:57 +0530[diff] [blame]5228 int i;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5229
Vivek Gautam10939b12018-01-16 16:26:57 +0530[diff] [blame]5230 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5231 if (!qmp->clks)
5232 return -ENOMEM;
5233
Vivek Gautam10939b12018-01-16 16:26:57 +0530[diff] [blame]5234 for (i = 0; i < num; i++)
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5235 qmp->clks[i].id = cfg->clk_list[i];
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5236
Vivek Gautam10939b12018-01-16 16:26:57 +0530[diff] [blame]5237 return devm_clk_bulk_get(dev, num, qmp->clks);
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5238}
5239
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5240static void phy_clk_release_provider(void *res)
Evan Green2e38c2e2018-12-10 11:32:07 -0800[diff] [blame]5241{
5242 of_clk_del_provider(res);
5243}
5244
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5245/*
5246 * Register a fixed rate pipe clock.
5247 *
5248 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
5249 * controls it. The <s>_pipe_clk coming out of the GCC is requested
5250 * by the PHY driver for its operations.
5251 * We register the <s>_pipe_clksrc here. The gcc driver takes care
5252 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
5253 * Below picture shows this relationship.
5254 *
5255 * +---------------+
5256 * | PHY block |<<---------------------------------------+
5257 * | | |
5258 * | +-------+ | +-----+ |
5259 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
5260 * clk | +-------+ | +-----+
5261 * +---------------+
5262 */
Varadarajan Narayanan2a9316b2017-07-31 12:04:13 +0530[diff] [blame]5263static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5264{
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5265 struct clk_fixed_rate *fixed;
5266 struct clk_init_data init = { };
Varadarajan Narayanan2a9316b2017-07-31 12:04:13 +0530[diff] [blame]5267 int ret;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5268
Varadarajan Narayanan2a9316b2017-07-31 12:04:13 +0530[diff] [blame]5269 ret = of_property_read_string(np, "clock-output-names", &init.name);
5270 if (ret) {
Rob Herringac9ba7d2018-08-27 20:52:40 -0500[diff] [blame]5271 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
Varadarajan Narayanan2a9316b2017-07-31 12:04:13 +0530[diff] [blame]5272 return ret;
5273 }
5274
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5275 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
5276 if (!fixed)
5277 return -ENOMEM;
5278
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5279 init.ops = &clk_fixed_rate_ops;
5280
5281 /* controllers using QMP phys use 125MHz pipe clock interface */
5282 fixed->fixed_rate = 125000000;
5283 fixed->hw.init = &init;
5284
Evan Green2e38c2e2018-12-10 11:32:07 -0800[diff] [blame]5285 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
5286 if (ret)
5287 return ret;
5288
5289 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
5290 if (ret)
5291 return ret;
5292
5293 /*
5294 * Roll a devm action because the clock provider is the child node, but
5295 * the child node is not actually a device.
5296 */
Cai Huoqing6ae69422021-09-22 21:00:16 +0800[diff] [blame]5297 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5298}
5299
5300/*
5301 * Display Port PLL driver block diagram for branch clocks
5302 *
5303 * +------------------------------+
5304 * | DP_VCO_CLK |
5305 * | |
5306 * | +-------------------+ |
5307 * | | (DP PLL/VCO) | |
5308 * | +---------+---------+ |
5309 * | v |
5310 * | +----------+-----------+ |
5311 * | | hsclk_divsel_clk_src | |
5312 * | +----------+-----------+ |
5313 * +------------------------------+
5314 * |
5315 * +---------<---------v------------>----------+
5316 * | |
5317 * +--------v----------------+ |
5318 * | dp_phy_pll_link_clk | |
5319 * | link_clk | |
5320 * +--------+----------------+ |
5321 * | |
5322 * | |
5323 * v v
5324 * Input to DISPCC block |
5325 * for link clk, crypto clk |
5326 * and interface clock |
5327 * |
5328 * |
5329 * +--------<------------+-----------------+---<---+
5330 * | | |
5331 * +----v---------+ +--------v-----+ +--------v------+
5332 * | vco_divided | | vco_divided | | vco_divided |
5333 * | _clk_src | | _clk_src | | _clk_src |
5334 * | | | | | |
5335 * |divsel_six | | divsel_two | | divsel_four |
5336 * +-------+------+ +-----+--------+ +--------+------+
5337 * | | |
5338 * v---->----------v-------------<------v
5339 * |
5340 * +----------+-----------------+
5341 * | dp_phy_pll_vco_div_clk |
5342 * +---------+------------------+
5343 * |
5344 * v
5345 * Input to DISPCC block
5346 * for DP pixel clock
5347 *
5348 */
5349static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
5350 struct clk_rate_request *req)
5351{
5352 switch (req->rate) {
5353 case 1620000000UL / 2:
5354 case 2700000000UL / 2:
5355 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
5356 return 0;
5357 default:
5358 return -EINVAL;
5359 }
5360}
5361
5362static unsigned long
5363qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
5364{
5365 const struct qmp_phy_dp_clks *dp_clks;
5366 const struct qmp_phy *qphy;
5367 const struct phy_configure_opts_dp *dp_opts;
5368
5369 dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
5370 qphy = dp_clks->qphy;
5371 dp_opts = &qphy->dp_opts;
5372
5373 switch (dp_opts->link_rate) {
5374 case 1620:
5375 return 1620000000UL / 2;
5376 case 2700:
5377 return 2700000000UL / 2;
5378 case 5400:
5379 return 5400000000UL / 4;
5380 case 8100:
5381 return 8100000000UL / 6;
5382 default:
5383 return 0;
5384 }
5385}
5386
5387static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
5388 .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
5389 .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
5390};
5391
5392static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
5393 struct clk_rate_request *req)
5394{
5395 switch (req->rate) {
5396 case 162000000:
5397 case 270000000:
5398 case 540000000:
5399 case 810000000:
5400 return 0;
5401 default:
5402 return -EINVAL;
5403 }
5404}
5405
5406static unsigned long
5407qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
5408{
5409 const struct qmp_phy_dp_clks *dp_clks;
5410 const struct qmp_phy *qphy;
5411 const struct phy_configure_opts_dp *dp_opts;
5412
5413 dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
5414 qphy = dp_clks->qphy;
5415 dp_opts = &qphy->dp_opts;
5416
5417 switch (dp_opts->link_rate) {
5418 case 1620:
5419 case 2700:
5420 case 5400:
5421 case 8100:
5422 return dp_opts->link_rate * 100000;
5423 default:
5424 return 0;
5425 }
5426}
5427
5428static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
5429 .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
5430 .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
5431};
5432
5433static struct clk_hw *
5434qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
5435{
5436 struct qmp_phy_dp_clks *dp_clks = data;
5437 unsigned int idx = clkspec->args[0];
5438
5439 if (idx >= 2) {
5440 pr_err("%s: invalid index %u\n", __func__, idx);
5441 return ERR_PTR(-EINVAL);
5442 }
5443
5444 if (idx == 0)
5445 return &dp_clks->dp_link_hw;
5446
5447 return &dp_clks->dp_pixel_hw;
5448}
5449
5450static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
5451 struct device_node *np)
5452{
5453 struct clk_init_data init = { };
5454 struct qmp_phy_dp_clks *dp_clks;
Bjorn Andersson34633212021-07-21 20:07:38 -0700[diff] [blame]5455 char name[64];
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5456 int ret;
5457
5458 dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
5459 if (!dp_clks)
5460 return -ENOMEM;
5461
5462 dp_clks->qphy = qphy;
5463 qphy->dp_clks = dp_clks;
5464
Bjorn Andersson34633212021-07-21 20:07:38 -0700[diff] [blame]5465 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5466 init.ops = &qcom_qmp_dp_link_clk_ops;
Bjorn Andersson34633212021-07-21 20:07:38 -0700[diff] [blame]5467 init.name = name;
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5468 dp_clks->dp_link_hw.init = &init;
5469 ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
5470 if (ret)
5471 return ret;
5472
Bjorn Andersson34633212021-07-21 20:07:38 -0700[diff] [blame]5473 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5474 init.ops = &qcom_qmp_dp_pixel_clk_ops;
Bjorn Andersson34633212021-07-21 20:07:38 -0700[diff] [blame]5475 init.name = name;
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5476 dp_clks->dp_pixel_hw.init = &init;
5477 ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
5478 if (ret)
5479 return ret;
5480
5481 ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
5482 if (ret)
5483 return ret;
5484
5485 /*
5486 * Roll a devm action because the clock provider is the child node, but
5487 * the child node is not actually a device.
5488 */
Cai Huoqing6ae69422021-09-22 21:00:16 +0800[diff] [blame]5489 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5490}
5491
5492static const struct phy_ops qcom_qmp_phy_gen_ops = {
Evan Green3f6d1762019-03-21 10:18:00 -0700[diff] [blame]5493 .init = qcom_qmp_phy_enable,
5494 .exit = qcom_qmp_phy_disable,
5495 .set_mode = qcom_qmp_phy_set_mode,
5496 .owner = THIS_MODULE,
5497};
5498
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5499static const struct phy_ops qcom_qmp_phy_dp_ops = {
5500 .init = qcom_qmp_phy_init,
5501 .configure = qcom_qmp_dp_phy_configure,
5502 .power_on = qcom_qmp_phy_power_on,
5503 .calibrate = qcom_qmp_dp_phy_calibrate,
5504 .power_off = qcom_qmp_phy_power_off,
5505 .exit = qcom_qmp_phy_exit,
5506 .set_mode = qcom_qmp_phy_set_mode,
5507 .owner = THIS_MODULE,
5508};
5509
Bjorn Anderssoncc1e06f2020-01-06 00:11:42 -0800[diff] [blame]5510static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
Evan Green3f6d1762019-03-21 10:18:00 -0700[diff] [blame]5511 .power_on = qcom_qmp_phy_enable,
5512 .power_off = qcom_qmp_phy_disable,
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5513 .set_mode = qcom_qmp_phy_set_mode,
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5514 .owner = THIS_MODULE,
5515};
5516
5517static
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5518int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
5519 void __iomem *serdes, const struct qmp_phy_cfg *cfg)
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5520{
5521 struct qcom_qmp *qmp = dev_get_drvdata(dev);
5522 struct phy *generic_phy;
5523 struct qmp_phy *qphy;
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5524 const struct phy_ops *ops;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5525 char prop_name[MAX_PROP_NAME];
5526 int ret;
5527
5528 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
5529 if (!qphy)
5530 return -ENOMEM;
5531
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5532 qphy->cfg = cfg;
5533 qphy->serdes = serdes;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5534 /*
5535 * Get memory resources for each phy lane:
Evan Green5e17b952018-12-10 11:28:23 -0800[diff] [blame]5536 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
5537 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
5538 * For single lane PHYs: pcs_misc (optional) -> 3.
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5539 */
5540 qphy->tx = of_iomap(np, 0);
Wei Yongjun53bf9592017-04-25 03:14:54 +0000[diff] [blame]5541 if (!qphy->tx)
5542 return -ENOMEM;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5543
5544 qphy->rx = of_iomap(np, 1);
Wei Yongjun53bf9592017-04-25 03:14:54 +0000[diff] [blame]5545 if (!qphy->rx)
5546 return -ENOMEM;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5547
5548 qphy->pcs = of_iomap(np, 2);
Wei Yongjun53bf9592017-04-25 03:14:54 +0000[diff] [blame]5549 if (!qphy->pcs)
5550 return -ENOMEM;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5551
Evan Green5e17b952018-12-10 11:28:23 -0800[diff] [blame]5552 /*
5553 * If this is a dual-lane PHY, then there should be registers for the
5554 * second lane. Some old device trees did not specify this, so fall
5555 * back to old legacy behavior of assuming they can be reached at an
5556 * offset from the first lane.
5557 */
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5558 if (cfg->is_dual_lane_phy) {
Evan Green5e17b952018-12-10 11:28:23 -0800[diff] [blame]5559 qphy->tx2 = of_iomap(np, 3);
5560 qphy->rx2 = of_iomap(np, 4);
5561 if (!qphy->tx2 || !qphy->rx2) {
5562 dev_warn(dev,
5563 "Underspecified device tree, falling back to legacy register regions\n");
5564
5565 /* In the old version, pcs_misc is at index 3. */
5566 qphy->pcs_misc = qphy->tx2;
5567 qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
5568 qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
5569
5570 } else {
5571 qphy->pcs_misc = of_iomap(np, 5);
5572 }
5573
5574 } else {
5575 qphy->pcs_misc = of_iomap(np, 3);
5576 }
5577
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5578 if (!qphy->pcs_misc)
5579 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
5580
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5581 /*
5582 * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
5583 * based phys, so they essentially have pipe clock. So,
5584 * we return error in case phy is USB3 or PIPE type.
5585 * Otherwise, we initialize pipe clock to NULL for
5586 * all phys that don't need this.
5587 */
5588 snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
5589 qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
5590 if (IS_ERR(qphy->pipe_clk)) {
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5591 if (cfg->type == PHY_TYPE_PCIE ||
5592 cfg->type == PHY_TYPE_USB3) {
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5593 ret = PTR_ERR(qphy->pipe_clk);
5594 if (ret != -EPROBE_DEFER)
5595 dev_err(dev,
5596 "failed to get lane%d pipe_clk, %d\n",
5597 id, ret);
5598 return ret;
5599 }
5600 qphy->pipe_clk = NULL;
5601 }
5602
5603 /* Get lane reset, if any */
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5604 if (cfg->has_lane_rst) {
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5605 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
5606 qphy->lane_rst = of_reset_control_get(np, prop_name);
5607 if (IS_ERR(qphy->lane_rst)) {
5608 dev_err(dev, "failed to get lane%d reset\n", id);
5609 return PTR_ERR(qphy->lane_rst);
5610 }
5611 }
5612
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5613 if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
Bjorn Anderssoncc1e06f2020-01-06 00:11:42 -0800[diff] [blame]5614 ops = &qcom_qmp_pcie_ufs_ops;
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5615 else if (cfg->type == PHY_TYPE_DP)
5616 ops = &qcom_qmp_phy_dp_ops;
5617 else
5618 ops = &qcom_qmp_phy_gen_ops;
Evan Green3f6d1762019-03-21 10:18:00 -0700[diff] [blame]5619
5620 generic_phy = devm_phy_create(dev, np, ops);
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5621 if (IS_ERR(generic_phy)) {
5622 ret = PTR_ERR(generic_phy);
5623 dev_err(dev, "failed to create qphy %d\n", ret);
5624 return ret;
5625 }
5626
5627 qphy->phy = generic_phy;
5628 qphy->index = id;
5629 qphy->qmp = qmp;
5630 qmp->phys[id] = qphy;
5631 phy_set_drvdata(generic_phy, qphy);
5632
5633 return 0;
5634}
5635
5636static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
5637 {
Sivaprakash Murugesan507156f2020-06-08 19:41:17 +0530[diff] [blame]5638 .compatible = "qcom,ipq8074-qmp-usb3-phy",
5639 .data = &ipq8074_usb3phy_cfg,
5640 }, {
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5641 .compatible = "qcom,msm8996-qmp-pcie-phy",
5642 .data = &msm8996_pciephy_cfg,
5643 }, {
Bjorn Andersson0347f0d2020-01-24 16:08:03 -0800[diff] [blame]5644 .compatible = "qcom,msm8996-qmp-ufs-phy",
5645 .data = &msm8996_ufs_cfg,
5646 }, {
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5647 .compatible = "qcom,msm8996-qmp-usb3-phy",
5648 .data = &msm8996_usb3phy_cfg,
Varadarajan Narayananeef243d2017-07-31 12:04:14 +0530[diff] [blame]5649 }, {
Marc Gonzalez73d7ec82019-04-09 14:48:22 +0200[diff] [blame]5650 .compatible = "qcom,msm8998-qmp-pcie-phy",
5651 .data = &msm8998_pciephy_cfg,
5652 }, {
Marc Gonzalez203d9b12019-02-08 23:14:30 +0100[diff] [blame]5653 .compatible = "qcom,msm8998-qmp-ufs-phy",
5654 .data = &sdm845_ufsphy_cfg,
5655 }, {
Varadarajan Narayananeef243d2017-07-31 12:04:14 +0530[diff] [blame]5656 .compatible = "qcom,ipq8074-qmp-pcie-phy",
5657 .data = &ipq8074_pciephy_cfg,
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]5658 }, {
Selvam Sathappan Periakaruppan520264d2021-05-05 12:18:31 +0300[diff] [blame]5659 .compatible = "qcom,ipq6018-qmp-pcie-phy",
5660 .data = &ipq6018_pciephy_cfg,
5661 }, {
Baruch Siach23fd6792021-08-04 17:05:06 +0300[diff] [blame]5662 .compatible = "qcom,ipq6018-qmp-usb3-phy",
5663 .data = &ipq8074_usb3phy_cfg,
5664 }, {
Sandeep Maheswaramd30b16a2020-05-15 08:09:18 +0530[diff] [blame]5665 .compatible = "qcom,sc7180-qmp-usb3-phy",
5666 .data = &sc7180_usb3phy_cfg,
5667 }, {
Stephen Boyd7612f4e2020-09-16 16:12:00 -0700[diff] [blame]5668 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
5669 /* It's a combo phy */
5670 }, {
Bjorn Anderssonf839f142021-06-28 17:45:09 -0700[diff] [blame]5671 .compatible = "qcom,sc8180x-qmp-pcie-phy",
5672 .data = &sc8180x_pciephy_cfg,
5673 }, {
Bjorn Anderssona5a621a2021-01-20 14:45:31 -0800[diff] [blame]5674 .compatible = "qcom,sc8180x-qmp-ufs-phy",
5675 .data = &sm8150_ufsphy_cfg,
5676 }, {
Bjorn Andersson4d1a6402021-01-20 17:43:39 -0800[diff] [blame]5677 .compatible = "qcom,sc8180x-qmp-usb3-phy",
5678 .data = &sm8150_usb3phy_cfg,
5679 }, {
Bjorn Andersson16338022021-07-21 15:56:30 -0700[diff] [blame]5680 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
5681 /* It's a combo phy */
5682 }, {
Bjorn Andersson909a5c72020-01-06 00:18:21 -0800[diff] [blame]5683 .compatible = "qcom,sdm845-qhp-pcie-phy",
5684 .data = &sdm845_qhp_pciephy_cfg,
5685 }, {
Bjorn Andersson421c9a02020-01-06 00:18:20 -0800[diff] [blame]5686 .compatible = "qcom,sdm845-qmp-pcie-phy",
5687 .data = &sdm845_qmp_pciephy_cfg,
5688 }, {
Manu Gautamf6721e52018-05-03 02:36:12 +0530[diff] [blame]5689 .compatible = "qcom,sdm845-qmp-usb3-phy",
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]5690 .data = &qmp_v3_usb3phy_cfg,
Manu Gautamf6721e52018-05-03 02:36:12 +0530[diff] [blame]5691 }, {
5692 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
5693 .data = &qmp_v3_usb3_uniphy_cfg,
Can Guocc31cdb2018-09-20 21:27:56 -0700[diff] [blame]5694 }, {
5695 .compatible = "qcom,sdm845-qmp-ufs-phy",
5696 .data = &sdm845_ufsphy_cfg,
Jeffrey Hugoa51969f2019-01-14 09:36:59 -0700[diff] [blame]5697 }, {
5698 .compatible = "qcom,msm8998-qmp-usb3-phy",
5699 .data = &msm8998_usb3phy_cfg,
Vinod Koula88c85e2019-10-24 13:18:02 +0530[diff] [blame]5700 }, {
Iskren Chernev152a8102021-08-21 18:56:56 +0300[diff] [blame]5701 .compatible = "qcom,sm6115-qmp-ufs-phy",
5702 .data = &sm6115_ufsphy_cfg,
5703 }, {
Vinod Koula88c85e2019-10-24 13:18:02 +0530[diff] [blame]5704 .compatible = "qcom,sm8150-qmp-ufs-phy",
5705 .data = &sm8150_ufsphy_cfg,
Bjorn Andersson2f292982020-04-14 23:07:45 -0700[diff] [blame]5706 }, {
5707 .compatible = "qcom,sm8250-qmp-ufs-phy",
5708 .data = &sm8150_ufsphy_cfg,
Jack Pham9a24b922020-05-04 16:54:25 -0700[diff] [blame]5709 }, {
5710 .compatible = "qcom,sm8150-qmp-usb3-phy",
5711 .data = &sm8150_usb3phy_cfg,
Jonathan Marek7b675ba2020-05-23 22:14:14 -0400[diff] [blame]5712 }, {
5713 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
5714 .data = &sm8150_usb3_uniphy_cfg,
Jonathan Marek90b65342020-05-23 22:14:15 -0400[diff] [blame]5715 }, {
5716 .compatible = "qcom,sm8250-qmp-usb3-phy",
5717 .data = &sm8250_usb3phy_cfg,
5718 }, {
Dmitry Baryshkovaff188f2021-03-31 18:16:12 +0300[diff] [blame]5719 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
5720 /* It's a combo phy */
5721 }, {
Jonathan Marek90b65342020-05-23 22:14:15 -0400[diff] [blame]5722 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
5723 .data = &sm8250_usb3_uniphy_cfg,
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]5724 }, {
5725 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
5726 .data = &sm8250_qmp_gen3x1_pciephy_cfg,
5727 }, {
5728 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
5729 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
5730 }, {
Vinod Koul0e43fdb2021-02-04 22:28:05 +0530[diff] [blame]5731 .compatible = "qcom,sm8350-qmp-ufs-phy",
5732 .data = &sm8350_ufsphy_cfg,
5733 }, {
Manivannan Sadhasivam6edf7702020-10-27 22:30:30 +0530[diff] [blame]5734 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
5735 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
Manivannan Sadhasivam86ef5a72021-01-11 17:00:10 +0530[diff] [blame]5736 }, {
Manivannan Sadhasivambe0ddb52021-04-27 12:24:00 +0530[diff] [blame]5737 .compatible = "qcom,sdx55-qmp-pcie-phy",
5738 .data = &sdx55_qmp_pciephy_cfg,
5739 }, {
Manivannan Sadhasivam86ef5a72021-01-11 17:00:10 +0530[diff] [blame]5740 .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
5741 .data = &sdx55_usb3_uniphy_cfg,
Jack Pham10c744d2021-01-15 09:47:21 -0800[diff] [blame]5742 }, {
5743 .compatible = "qcom,sm8350-qmp-usb3-phy",
5744 .data = &sm8350_usb3phy_cfg,
5745 }, {
5746 .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
5747 .data = &sm8350_usb3_uniphy_cfg,
Shawn Guo8abe5e72021-09-27 14:48:29 +0800[diff] [blame]5748 }, {
5749 .compatible = "qcom,qcm2290-qmp-usb3-phy",
5750 .data = &qcm2290_usb3phy_cfg,
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5751 },
5752 { },
5753};
5754MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
5755
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5756static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
Stephen Boyd7612f4e2020-09-16 16:12:00 -0700[diff] [blame]5757 {
5758 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
5759 .data = &sc7180_usb3dpphy_cfg,
5760 },
Dmitry Baryshkovaff188f2021-03-31 18:16:12 +0300[diff] [blame]5761 {
5762 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
5763 .data = &sm8250_usb3dpphy_cfg,
5764 },
Bjorn Andersson16338022021-07-21 15:56:30 -0700[diff] [blame]5765 {
5766 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
5767 .data = &sc8180x_usb3dpphy_cfg,
5768 },
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5769 { }
5770};
5771
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5772static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
5773 SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
5774 qcom_qmp_phy_runtime_resume, NULL)
5775};
5776
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5777static int qcom_qmp_phy_probe(struct platform_device *pdev)
5778{
5779 struct qcom_qmp *qmp;
5780 struct device *dev = &pdev->dev;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5781 struct device_node *child;
5782 struct phy_provider *phy_provider;
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5783 void __iomem *serdes;
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5784 void __iomem *usb_serdes;
Stephen Boydfcea94a2020-10-26 13:59:42 -0700[diff] [blame]5785 void __iomem *dp_serdes = NULL;
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5786 const struct qmp_phy_combo_cfg *combo_cfg = NULL;
Vinod Koul60f5a242020-10-01 12:39:11 +0530[diff] [blame]5787 const struct qmp_phy_cfg *cfg = NULL;
5788 const struct qmp_phy_cfg *usb_cfg = NULL;
5789 const struct qmp_phy_cfg *dp_cfg = NULL;
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5790 int num, id, expected_phys;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5791 int ret;
5792
5793 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
5794 if (!qmp)
5795 return -ENOMEM;
5796
5797 qmp->dev = dev;
5798 dev_set_drvdata(dev, qmp);
5799
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]5800 /* Get the specific init parameters of QMP phy */
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5801 cfg = of_device_get_match_data(dev);
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5802 if (!cfg) {
5803 const struct of_device_id *match;
5804
5805 match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
5806 if (!match)
5807 return -EINVAL;
5808
5809 combo_cfg = match->data;
5810 if (!combo_cfg)
5811 return -EINVAL;
5812
5813 usb_cfg = combo_cfg->usb_cfg;
5814 cfg = usb_cfg; /* Setup clks and regulators */
5815 }
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]5816
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5817 /* per PHY serdes; usually located at base address */
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5818 usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
Stephen Boydf385b732020-09-16 16:11:58 -0700[diff] [blame]5819 if (IS_ERR(serdes))
5820 return PTR_ERR(serdes);
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5821
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]5822 /* per PHY dp_com; if PHY has dp_com control block */
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5823 if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
Stephen Boyddab7b102020-09-16 16:11:57 -0700[diff] [blame]5824 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
5825 if (IS_ERR(qmp->dp_com))
5826 return PTR_ERR(qmp->dp_com);
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]5827 }
5828
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5829 if (combo_cfg) {
5830 /* Only two serdes for combo PHY */
5831 dp_serdes = devm_platform_ioremap_resource(pdev, 2);
5832 if (IS_ERR(dp_serdes))
5833 return PTR_ERR(dp_serdes);
5834
5835 dp_cfg = combo_cfg->dp_cfg;
5836 expected_phys = 2;
5837 } else {
5838 expected_phys = cfg->nlanes;
5839 }
5840
Manu Gautamefb05a52018-01-16 16:27:08 +0530[diff] [blame]5841 mutex_init(&qmp->phy_mutex);
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5842
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5843 ret = qcom_qmp_phy_clk_init(dev, cfg);
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5844 if (ret)
5845 return ret;
5846
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5847 ret = qcom_qmp_phy_reset_init(dev, cfg);
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5848 if (ret)
5849 return ret;
5850
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5851 ret = qcom_qmp_phy_vreg_init(dev, cfg);
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5852 if (ret) {
Douglas Anderson22fa10e2018-05-14 15:42:21 -0700[diff] [blame]5853 if (ret != -EPROBE_DEFER)
5854 dev_err(dev, "failed to get regulator supplies: %d\n",
5855 ret);
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5856 return ret;
5857 }
5858
5859 num = of_get_available_child_count(dev->of_node);
5860 /* do we have a rogue child node ? */
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5861 if (num > expected_phys)
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5862 return -EINVAL;
5863
5864 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
5865 if (!qmp->phys)
5866 return -ENOMEM;
5867
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5868 pm_runtime_set_active(dev);
5869 pm_runtime_enable(dev);
5870 /*
5871 * Prevent runtime pm from being ON by default. Users can enable
5872 * it using power/control in sysfs.
5873 */
5874 pm_runtime_forbid(dev);
5875
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5876 id = 0;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5877 for_each_available_child_of_node(dev->of_node, child) {
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5878 if (of_node_name_eq(child, "dp-phy")) {
5879 cfg = dp_cfg;
5880 serdes = dp_serdes;
5881 } else if (of_node_name_eq(child, "usb3-phy")) {
5882 cfg = usb_cfg;
5883 serdes = usb_serdes;
5884 }
5885
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5886 /* Create per-lane phy */
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5887 ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5888 if (ret) {
5889 dev_err(dev, "failed to create lane%d phy, %d\n",
5890 id, ret);
Nishka Dasguptabe0345b2019-08-08 12:59:37 +0530[diff] [blame]5891 goto err_node_put;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5892 }
5893
5894 /*
5895 * Register the pipe clock provided by phy.
5896 * See function description to see details of this pipe clock.
5897 */
Stephen Boydaa968cb2020-09-16 16:11:56 -0700[diff] [blame]5898 if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
5899 ret = phy_pipe_clk_register(qmp, child);
5900 if (ret) {
5901 dev_err(qmp->dev,
5902 "failed to register pipe clock source\n");
5903 goto err_node_put;
5904 }
Stephen Boyd52e013d2020-09-16 16:11:59 -0700[diff] [blame]5905 } else if (cfg->type == PHY_TYPE_DP) {
5906 ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
5907 if (ret) {
5908 dev_err(qmp->dev,
5909 "failed to register DP clock source\n");
5910 goto err_node_put;
5911 }
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5912 }
5913 id++;
5914 }
5915
5916 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
5917 if (!IS_ERR(phy_provider))
5918 dev_info(dev, "Registered Qcom-QMP phy\n");
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5919 else
5920 pm_runtime_disable(dev);
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5921
5922 return PTR_ERR_OR_ZERO(phy_provider);
Nishka Dasguptabe0345b2019-08-08 12:59:37 +0530[diff] [blame]5923
5924err_node_put:
5925 pm_runtime_disable(dev);
5926 of_node_put(child);
5927 return ret;
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5928}
5929
5930static struct platform_driver qcom_qmp_phy_driver = {
5931 .probe = qcom_qmp_phy_probe,
5932 .driver = {
5933 .name = "qcom-qmp-phy",
Manu Gautamac0d2392018-01-16 16:27:11 +0530[diff] [blame]5934 .pm = &qcom_qmp_phy_pm_ops,
Vivek Gautame78f3d152017-04-06 11:21:25 +0530[diff] [blame]5935 .of_match_table = qcom_qmp_phy_of_match_table,
5936 },
5937};
5938
5939module_platform_driver(qcom_qmp_phy_driver);
5940
5941MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
5942MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
5943MODULE_LICENSE("GPL v2");