| Punit Agrawal | 0c09d48 | 2018-10-08 11:03:55 +0100 | [diff] [blame] | 1 | HugeTLBpage on ARM64 |
| 2 | ==================== |
| 3 | |
| 4 | Hugepage relies on making efficient use of TLBs to improve performance of |
| 5 | address translations. The benefit depends on both - |
| 6 | |
| 7 | - the size of hugepages |
| 8 | - size of entries supported by the TLBs |
| 9 | |
| 10 | The ARM64 port supports two flavours of hugepages. |
| 11 | |
| 12 | 1) Block mappings at the pud/pmd level |
| 13 | -------------------------------------- |
| 14 | |
| 15 | These are regular hugepages where a pmd or a pud page table entry points to a |
| 16 | block of memory. Regardless of the supported size of entries in TLB, block |
| 17 | mappings reduce the depth of page table walk needed to translate hugepage |
| 18 | addresses. |
| 19 | |
| 20 | 2) Using the Contiguous bit |
| 21 | --------------------------- |
| 22 | |
| 23 | The architecture provides a contiguous bit in the translation table entries |
| 24 | (D4.5.3, ARM DDI 0487C.a) that hints to the MMU to indicate that it is one of a |
| 25 | contiguous set of entries that can be cached in a single TLB entry. |
| 26 | |
| 27 | The contiguous bit is used in Linux to increase the mapping size at the pmd and |
| 28 | pte (last) level. The number of supported contiguous entries varies by page size |
| 29 | and level of the page table. |
| 30 | |
| 31 | |
| 32 | The following hugepage sizes are supported - |
| 33 | |
| 34 | CONT PTE PMD CONT PMD PUD |
| 35 | -------- --- -------- --- |
| 36 | 4K: 64K 2M 32M 1G |
| 37 | 16K: 2M 32M 1G |
| 38 | 64K: 2M 512M 16G |