| Enric Balletbo i Serra | 86a378b | 2020-10-30 12:36:16 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (c) 2020 MediaTek Inc. |
| 4 | * Author: Weiyi Lu <weiyi.lu@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef _DT_BINDINGS_POWER_MT8183_POWER_H |
| 8 | #define _DT_BINDINGS_POWER_MT8183_POWER_H |
| 9 | |
| 10 | #define MT8183_POWER_DOMAIN_AUDIO 0 |
| 11 | #define MT8183_POWER_DOMAIN_CONN 1 |
| 12 | #define MT8183_POWER_DOMAIN_MFG_ASYNC 2 |
| 13 | #define MT8183_POWER_DOMAIN_MFG 3 |
| 14 | #define MT8183_POWER_DOMAIN_MFG_CORE0 4 |
| 15 | #define MT8183_POWER_DOMAIN_MFG_CORE1 5 |
| 16 | #define MT8183_POWER_DOMAIN_MFG_2D 6 |
| 17 | #define MT8183_POWER_DOMAIN_DISP 7 |
| 18 | #define MT8183_POWER_DOMAIN_CAM 8 |
| 19 | #define MT8183_POWER_DOMAIN_ISP 9 |
| 20 | #define MT8183_POWER_DOMAIN_VDEC 10 |
| 21 | #define MT8183_POWER_DOMAIN_VENC 11 |
| 22 | #define MT8183_POWER_DOMAIN_VPU_TOP 12 |
| 23 | #define MT8183_POWER_DOMAIN_VPU_CORE0 13 |
| 24 | #define MT8183_POWER_DOMAIN_VPU_CORE1 14 |
| 25 | |
| 26 | #endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */ |