blob: 3318544366b894801a0a2344bc21195ccf4e694b [file] [log] [blame]
Marcus Folkesson2e62c492018-03-16 16:14:11 +01001// SPDX-License-Identifier: GPL-2.0+
Alejandro Cabrerae9659e62011-06-02 22:13:11 +01002/*
Michal Simek9419c072013-05-31 07:56:33 +02003 * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt
4 *
Michal Simekd14fd962014-02-12 14:34:32 +01005 * (C) Copyright 2013 - 2014 Xilinx, Inc.
Michal Simek9419c072013-05-31 07:56:33 +02006 * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>)
Michal Simek9419c072013-05-31 07:56:33 +02007 */
Alejandro Cabrerae9659e62011-06-02 22:13:11 +01008
Srinivas Goud73ec9442021-03-29 21:49:36 +05309#include <linux/bits.h>
Shubhrajyoti Datta9d6b4ef2016-08-12 12:17:01 +053010#include <linux/clk.h>
Michal Simekf06cdfd2014-02-12 14:34:34 +010011#include <linux/err.h>
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010012#include <linux/module.h>
13#include <linux/types.h>
14#include <linux/kernel.h>
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010015#include <linux/ioport.h>
16#include <linux/watchdog.h>
17#include <linux/io.h>
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010018#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/of_address.h>
21
22/* Register offsets for the Wdt device */
23#define XWT_TWCSR0_OFFSET 0x0 /* Control/Status Register0 */
24#define XWT_TWCSR1_OFFSET 0x4 /* Control/Status Register1 */
25#define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */
26
27/* Control/Status Register Masks */
Srinivas Goud73ec9442021-03-29 21:49:36 +053028#define XWT_CSR0_WRS_MASK BIT(3) /* Reset status */
29#define XWT_CSR0_WDS_MASK BIT(2) /* Timer state */
30#define XWT_CSR0_EWDT1_MASK BIT(1) /* Enable bit 1 */
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010031
32/* Control/Status Register 0/1 bits */
Srinivas Goud73ec9442021-03-29 21:49:36 +053033#define XWT_CSRX_EWDT2_MASK BIT(0) /* Enable bit 2 */
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010034
35/* SelfTest constants */
36#define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000
37#define XWT_TIMER_FAILED 0xFFFFFFFF
38
39#define WATCHDOG_NAME "Xilinx Watchdog"
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010040
41struct xwdt_device {
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010042 void __iomem *base;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010043 u32 wdt_interval;
Srinivas Goudb2802e72021-03-29 21:49:35 +053044 spinlock_t spinlock; /* spinlock for register handling */
Michal Simek90663172014-02-12 14:41:19 +010045 struct watchdog_device xilinx_wdt_wdd;
Shubhrajyoti Datta9d6b4ef2016-08-12 12:17:01 +053046 struct clk *clk;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010047};
48
Michal Simekd14fd962014-02-12 14:34:32 +010049static int xilinx_wdt_start(struct watchdog_device *wdd)
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010050{
Maulik Jodhanib6bc4162017-08-07 13:24:22 +020051 int ret;
Michal Simek5cf4e692014-02-12 14:34:33 +010052 u32 control_status_reg;
Michal Simek90663172014-02-12 14:41:19 +010053 struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
Michal Simek5cf4e692014-02-12 14:34:33 +010054
Maulik Jodhanib6bc4162017-08-07 13:24:22 +020055 ret = clk_enable(xdev->clk);
56 if (ret) {
57 dev_err(wdd->parent, "Failed to enable clock\n");
58 return ret;
59 }
60
Michal Simek90663172014-02-12 14:41:19 +010061 spin_lock(&xdev->spinlock);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010062
63 /* Clean previous status and enable the watchdog timer */
Michal Simek90663172014-02-12 14:41:19 +010064 control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010065 control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
66
67 iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK),
Michal Simek90663172014-02-12 14:41:19 +010068 xdev->base + XWT_TWCSR0_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010069
Michal Simek90663172014-02-12 14:41:19 +010070 iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010071
Michal Simek90663172014-02-12 14:41:19 +010072 spin_unlock(&xdev->spinlock);
Michal Simekd14fd962014-02-12 14:34:32 +010073
Srinivas Gouda40b2c32021-03-29 21:49:37 +053074 dev_dbg(wdd->parent, "Watchdog Started!\n");
75
Michal Simekd14fd962014-02-12 14:34:32 +010076 return 0;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010077}
78
Michal Simekd14fd962014-02-12 14:34:32 +010079static int xilinx_wdt_stop(struct watchdog_device *wdd)
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010080{
Michal Simek5cf4e692014-02-12 14:34:33 +010081 u32 control_status_reg;
Michal Simek90663172014-02-12 14:41:19 +010082 struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
Michal Simek5cf4e692014-02-12 14:34:33 +010083
Michal Simek90663172014-02-12 14:41:19 +010084 spin_lock(&xdev->spinlock);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010085
Michal Simek90663172014-02-12 14:41:19 +010086 control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010087
88 iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK),
Michal Simek90663172014-02-12 14:41:19 +010089 xdev->base + XWT_TWCSR0_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010090
Michal Simek90663172014-02-12 14:41:19 +010091 iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +010092
Michal Simek90663172014-02-12 14:41:19 +010093 spin_unlock(&xdev->spinlock);
Maulik Jodhanib6bc4162017-08-07 13:24:22 +020094
95 clk_disable(xdev->clk);
96
Srinivas Gouda40b2c32021-03-29 21:49:37 +053097 dev_dbg(wdd->parent, "Watchdog Stopped!\n");
Michal Simekd14fd962014-02-12 14:34:32 +010098
99 return 0;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100100}
101
Michal Simekd14fd962014-02-12 14:34:32 +0100102static int xilinx_wdt_keepalive(struct watchdog_device *wdd)
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100103{
Michal Simek5cf4e692014-02-12 14:34:33 +0100104 u32 control_status_reg;
Michal Simek90663172014-02-12 14:41:19 +0100105 struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
Michal Simek5cf4e692014-02-12 14:34:33 +0100106
Michal Simek90663172014-02-12 14:41:19 +0100107 spin_lock(&xdev->spinlock);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100108
Michal Simek90663172014-02-12 14:41:19 +0100109 control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100110 control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
Michal Simek90663172014-02-12 14:41:19 +0100111 iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100112
Michal Simek90663172014-02-12 14:41:19 +0100113 spin_unlock(&xdev->spinlock);
Michal Simekd14fd962014-02-12 14:34:32 +0100114
115 return 0;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100116}
117
Michal Simekd14fd962014-02-12 14:34:32 +0100118static const struct watchdog_info xilinx_wdt_ident = {
119 .options = WDIOF_MAGICCLOSE |
120 WDIOF_KEEPALIVEPING,
121 .firmware_version = 1,
122 .identity = WATCHDOG_NAME,
123};
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100124
Michal Simekd14fd962014-02-12 14:34:32 +0100125static const struct watchdog_ops xilinx_wdt_ops = {
126 .owner = THIS_MODULE,
127 .start = xilinx_wdt_start,
128 .stop = xilinx_wdt_stop,
129 .ping = xilinx_wdt_keepalive,
130};
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100131
Michal Simek90663172014-02-12 14:41:19 +0100132static u32 xwdt_selftest(struct xwdt_device *xdev)
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100133{
134 int i;
135 u32 timer_value1;
136 u32 timer_value2;
137
Michal Simek90663172014-02-12 14:41:19 +0100138 spin_lock(&xdev->spinlock);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100139
Michal Simek90663172014-02-12 14:41:19 +0100140 timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET);
141 timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100142
143 for (i = 0;
144 ((i <= XWT_MAX_SELFTEST_LOOP_COUNT) &&
145 (timer_value2 == timer_value1)); i++) {
Michal Simek90663172014-02-12 14:41:19 +0100146 timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100147 }
148
Michal Simek90663172014-02-12 14:41:19 +0100149 spin_unlock(&xdev->spinlock);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100150
151 if (timer_value2 != timer_value1)
152 return ~XWT_TIMER_FAILED;
153 else
154 return XWT_TIMER_FAILED;
155}
156
Guenter Roeck801cdffe2019-04-09 10:23:48 -0700157static void xwdt_clk_disable_unprepare(void *data)
158{
159 clk_disable_unprepare(data);
160}
161
Bill Pemberton2d991a12012-11-19 13:21:41 -0500162static int xwdt_probe(struct platform_device *pdev)
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100163{
Guenter Roeck801cdffe2019-04-09 10:23:48 -0700164 struct device *dev = &pdev->dev;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100165 int rc;
Michal Simek8d6a1402014-02-12 14:41:25 +0100166 u32 pfreq = 0, enable_once = 0;
Michal Simek90663172014-02-12 14:41:19 +0100167 struct xwdt_device *xdev;
Michal Simek90663172014-02-12 14:41:19 +0100168 struct watchdog_device *xilinx_wdt_wdd;
169
Guenter Roeck801cdffe2019-04-09 10:23:48 -0700170 xdev = devm_kzalloc(dev, sizeof(*xdev), GFP_KERNEL);
Michal Simek90663172014-02-12 14:41:19 +0100171 if (!xdev)
172 return -ENOMEM;
173
174 xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd;
175 xilinx_wdt_wdd->info = &xilinx_wdt_ident;
176 xilinx_wdt_wdd->ops = &xilinx_wdt_ops;
Guenter Roeck801cdffe2019-04-09 10:23:48 -0700177 xilinx_wdt_wdd->parent = dev;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100178
Guenter Roeck0f0a6a22019-04-02 12:01:53 -0700179 xdev->base = devm_platform_ioremap_resource(pdev, 0);
Michal Simek90663172014-02-12 14:41:19 +0100180 if (IS_ERR(xdev->base))
181 return PTR_ERR(xdev->base);
Michal Simekf06cdfd2014-02-12 14:34:34 +0100182
Guenter Roeck801cdffe2019-04-09 10:23:48 -0700183 rc = of_property_read_u32(dev->of_node, "xlnx,wdt-interval",
Michal Simek2e79a362014-02-12 14:41:21 +0100184 &xdev->wdt_interval);
Michal Simek8d6a1402014-02-12 14:41:25 +0100185 if (rc)
Guenter Roeck801cdffe2019-04-09 10:23:48 -0700186 dev_warn(dev, "Parameter \"xlnx,wdt-interval\" not found\n");
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100187
Guenter Roeck801cdffe2019-04-09 10:23:48 -0700188 rc = of_property_read_u32(dev->of_node, "xlnx,wdt-enable-once",
Michal Simek2e79a362014-02-12 14:41:21 +0100189 &enable_once);
190 if (rc)
Guenter Roeck801cdffe2019-04-09 10:23:48 -0700191 dev_warn(dev,
Michal Simek4c7fbbc2014-02-12 14:41:20 +0100192 "Parameter \"xlnx,wdt-enable-once\" not found\n");
Michal Simek2e79a362014-02-12 14:41:21 +0100193
194 watchdog_set_nowayout(xilinx_wdt_wdd, enable_once);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100195
Guenter Roeck801cdffe2019-04-09 10:23:48 -0700196 xdev->clk = devm_clk_get(dev, NULL);
Maulik Jodhanib6bc4162017-08-07 13:24:22 +0200197 if (IS_ERR(xdev->clk)) {
198 if (PTR_ERR(xdev->clk) != -ENOENT)
199 return PTR_ERR(xdev->clk);
200
201 /*
202 * Clock framework support is optional, continue on
203 * anyways if we don't find a matching clock.
204 */
205 xdev->clk = NULL;
206
Guenter Roeck801cdffe2019-04-09 10:23:48 -0700207 rc = of_property_read_u32(dev->of_node, "clock-frequency",
Maulik Jodhanib6bc4162017-08-07 13:24:22 +0200208 &pfreq);
209 if (rc)
Guenter Roeck801cdffe2019-04-09 10:23:48 -0700210 dev_warn(dev,
Maulik Jodhanib6bc4162017-08-07 13:24:22 +0200211 "The watchdog clock freq cannot be obtained\n");
212 } else {
213 pfreq = clk_get_rate(xdev->clk);
Srinivas Neelif185de222021-03-29 21:49:38 +0530214 rc = clk_prepare_enable(xdev->clk);
215 if (rc) {
216 dev_err(dev, "unable to enable clock\n");
217 return rc;
218 }
219 rc = devm_add_action_or_reset(dev, xwdt_clk_disable_unprepare,
220 xdev->clk);
221 if (rc)
222 return rc;
Maulik Jodhanib6bc4162017-08-07 13:24:22 +0200223 }
224
Michal Simek75b3c5a2014-02-12 14:41:22 +0100225 /*
226 * Twice of the 2^wdt_interval / freq because the first wdt overflow is
227 * ignored (interrupt), reset is only generated at second wdt overflow
228 */
Michal Simek8d6a1402014-02-12 14:41:25 +0100229 if (pfreq && xdev->wdt_interval)
Michal Simek90663172014-02-12 14:41:19 +0100230 xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) /
Michal Simek2e79a362014-02-12 14:41:21 +0100231 pfreq);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100232
Michal Simek90663172014-02-12 14:41:19 +0100233 spin_lock_init(&xdev->spinlock);
234 watchdog_set_drvdata(xilinx_wdt_wdd, xdev);
235
236 rc = xwdt_selftest(xdev);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100237 if (rc == XWT_TIMER_FAILED) {
Guenter Roeck801cdffe2019-04-09 10:23:48 -0700238 dev_err(dev, "SelfTest routine error\n");
239 return rc;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100240 }
241
Guenter Roeck801cdffe2019-04-09 10:23:48 -0700242 rc = devm_watchdog_register_device(dev, xilinx_wdt_wdd);
Wolfram Sang0fa6cf72019-05-18 23:27:44 +0200243 if (rc)
Guenter Roeck801cdffe2019-04-09 10:23:48 -0700244 return rc;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100245
Maulik Jodhanib6bc4162017-08-07 13:24:22 +0200246 clk_disable(xdev->clk);
247
Srinivas Neeli48027d02021-03-29 21:49:39 +0530248 dev_info(dev, "Xilinx Watchdog Timer with timeout %ds\n",
249 xilinx_wdt_wdd->timeout);
Michal Simek90663172014-02-12 14:41:19 +0100250
251 platform_set_drvdata(pdev, xdev);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100252
253 return 0;
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100254}
255
Michal Simek6f671c62017-08-07 13:24:23 +0200256/**
257 * xwdt_suspend - Suspend the device.
258 *
259 * @dev: handle to the device structure.
260 * Return: 0 always.
261 */
262static int __maybe_unused xwdt_suspend(struct device *dev)
263{
Wolfram Sang20745632018-04-19 16:06:29 +0200264 struct xwdt_device *xdev = dev_get_drvdata(dev);
Michal Simek6f671c62017-08-07 13:24:23 +0200265
266 if (watchdog_active(&xdev->xilinx_wdt_wdd))
267 xilinx_wdt_stop(&xdev->xilinx_wdt_wdd);
268
269 return 0;
270}
271
272/**
273 * xwdt_resume - Resume the device.
274 *
275 * @dev: handle to the device structure.
276 * Return: 0 on success, errno otherwise.
277 */
278static int __maybe_unused xwdt_resume(struct device *dev)
279{
Wolfram Sang20745632018-04-19 16:06:29 +0200280 struct xwdt_device *xdev = dev_get_drvdata(dev);
Michal Simek6f671c62017-08-07 13:24:23 +0200281 int ret = 0;
282
283 if (watchdog_active(&xdev->xilinx_wdt_wdd))
284 ret = xilinx_wdt_start(&xdev->xilinx_wdt_wdd);
285
286 return ret;
287}
288
289static SIMPLE_DEV_PM_OPS(xwdt_pm_ops, xwdt_suspend, xwdt_resume);
290
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100291/* Match table for of_platform binding */
Jingoo Han9ebf1852014-05-07 17:42:22 +0900292static const struct of_device_id xwdt_of_match[] = {
Michal Simek8fce9b32013-05-31 07:56:34 +0200293 { .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100294 { .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
295 {},
296};
297MODULE_DEVICE_TABLE(of, xwdt_of_match);
298
299static struct platform_driver xwdt_driver = {
300 .probe = xwdt_probe,
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100301 .driver = {
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100302 .name = WATCHDOG_NAME,
303 .of_match_table = xwdt_of_match,
Michal Simek6f671c62017-08-07 13:24:23 +0200304 .pm = &xwdt_pm_ops,
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100305 },
306};
307
Axel Linb8ec6112011-11-29 13:56:27 +0800308module_platform_driver(xwdt_driver);
Alejandro Cabrerae9659e62011-06-02 22:13:11 +0100309
310MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>");
311MODULE_DESCRIPTION("Xilinx Watchdog driver");
Marcus Folkesson2e62c492018-03-16 16:14:11 +0100312MODULE_LICENSE("GPL");