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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 2572da44a51192ad181482c1989e66e5eb47dcbe / . / drivers / pinctrl / meson / pinctrl-meson8.c
blob: dd17100efdcfc2fcacc3cb75a473feebd9559e7e [file] [log] [blame]
Thomas Gleixner3c910ec2019-06-01 10:09:00 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]2/*
Martin Blumenstinglb0d46cb2018-04-22 12:53:29 +0200[diff] [blame]3 * Pin controller and GPIO driver for Amlogic Meson8 and Meson8m2.
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]4 *
5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]6 */
7
8#include <dt-bindings/gpio/meson8-gpio.h>
9#include "pinctrl-meson.h"
Jerome Brunetce385aa2017-10-12 14:40:26 +0200[diff] [blame]10#include "pinctrl-meson8-pmx.h"
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]11
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]12static const struct pinctrl_pin_desc meson8_cbus_pins[] = {
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]13 MESON_PIN(GPIOX_0),
14 MESON_PIN(GPIOX_1),
15 MESON_PIN(GPIOX_2),
16 MESON_PIN(GPIOX_3),
17 MESON_PIN(GPIOX_4),
18 MESON_PIN(GPIOX_5),
19 MESON_PIN(GPIOX_6),
20 MESON_PIN(GPIOX_7),
21 MESON_PIN(GPIOX_8),
22 MESON_PIN(GPIOX_9),
23 MESON_PIN(GPIOX_10),
24 MESON_PIN(GPIOX_11),
25 MESON_PIN(GPIOX_12),
26 MESON_PIN(GPIOX_13),
27 MESON_PIN(GPIOX_14),
28 MESON_PIN(GPIOX_15),
29 MESON_PIN(GPIOX_16),
30 MESON_PIN(GPIOX_17),
31 MESON_PIN(GPIOX_18),
32 MESON_PIN(GPIOX_19),
33 MESON_PIN(GPIOX_20),
34 MESON_PIN(GPIOX_21),
35 MESON_PIN(GPIOY_0),
36 MESON_PIN(GPIOY_1),
37 MESON_PIN(GPIOY_2),
38 MESON_PIN(GPIOY_3),
39 MESON_PIN(GPIOY_4),
40 MESON_PIN(GPIOY_5),
41 MESON_PIN(GPIOY_6),
42 MESON_PIN(GPIOY_7),
43 MESON_PIN(GPIOY_8),
44 MESON_PIN(GPIOY_9),
45 MESON_PIN(GPIOY_10),
46 MESON_PIN(GPIOY_11),
47 MESON_PIN(GPIOY_12),
48 MESON_PIN(GPIOY_13),
49 MESON_PIN(GPIOY_14),
50 MESON_PIN(GPIOY_15),
51 MESON_PIN(GPIOY_16),
52 MESON_PIN(GPIODV_0),
53 MESON_PIN(GPIODV_1),
54 MESON_PIN(GPIODV_2),
55 MESON_PIN(GPIODV_3),
56 MESON_PIN(GPIODV_4),
57 MESON_PIN(GPIODV_5),
58 MESON_PIN(GPIODV_6),
59 MESON_PIN(GPIODV_7),
60 MESON_PIN(GPIODV_8),
61 MESON_PIN(GPIODV_9),
62 MESON_PIN(GPIODV_10),
63 MESON_PIN(GPIODV_11),
64 MESON_PIN(GPIODV_12),
65 MESON_PIN(GPIODV_13),
66 MESON_PIN(GPIODV_14),
67 MESON_PIN(GPIODV_15),
68 MESON_PIN(GPIODV_16),
69 MESON_PIN(GPIODV_17),
70 MESON_PIN(GPIODV_18),
71 MESON_PIN(GPIODV_19),
72 MESON_PIN(GPIODV_20),
73 MESON_PIN(GPIODV_21),
74 MESON_PIN(GPIODV_22),
75 MESON_PIN(GPIODV_23),
76 MESON_PIN(GPIODV_24),
77 MESON_PIN(GPIODV_25),
78 MESON_PIN(GPIODV_26),
79 MESON_PIN(GPIODV_27),
80 MESON_PIN(GPIODV_28),
81 MESON_PIN(GPIODV_29),
82 MESON_PIN(GPIOH_0),
83 MESON_PIN(GPIOH_1),
84 MESON_PIN(GPIOH_2),
85 MESON_PIN(GPIOH_3),
86 MESON_PIN(GPIOH_4),
87 MESON_PIN(GPIOH_5),
88 MESON_PIN(GPIOH_6),
89 MESON_PIN(GPIOH_7),
90 MESON_PIN(GPIOH_8),
91 MESON_PIN(GPIOH_9),
92 MESON_PIN(GPIOZ_0),
93 MESON_PIN(GPIOZ_1),
94 MESON_PIN(GPIOZ_2),
95 MESON_PIN(GPIOZ_3),
96 MESON_PIN(GPIOZ_4),
97 MESON_PIN(GPIOZ_5),
98 MESON_PIN(GPIOZ_6),
99 MESON_PIN(GPIOZ_7),
100 MESON_PIN(GPIOZ_8),
101 MESON_PIN(GPIOZ_9),
102 MESON_PIN(GPIOZ_10),
103 MESON_PIN(GPIOZ_11),
104 MESON_PIN(GPIOZ_12),
105 MESON_PIN(GPIOZ_13),
106 MESON_PIN(GPIOZ_14),
107 MESON_PIN(CARD_0),
108 MESON_PIN(CARD_1),
109 MESON_PIN(CARD_2),
110 MESON_PIN(CARD_3),
111 MESON_PIN(CARD_4),
112 MESON_PIN(CARD_5),
113 MESON_PIN(CARD_6),
114 MESON_PIN(BOOT_0),
115 MESON_PIN(BOOT_1),
116 MESON_PIN(BOOT_2),
117 MESON_PIN(BOOT_3),
118 MESON_PIN(BOOT_4),
119 MESON_PIN(BOOT_5),
120 MESON_PIN(BOOT_6),
121 MESON_PIN(BOOT_7),
122 MESON_PIN(BOOT_8),
123 MESON_PIN(BOOT_9),
124 MESON_PIN(BOOT_10),
125 MESON_PIN(BOOT_11),
126 MESON_PIN(BOOT_12),
127 MESON_PIN(BOOT_13),
128 MESON_PIN(BOOT_14),
129 MESON_PIN(BOOT_15),
130 MESON_PIN(BOOT_16),
131 MESON_PIN(BOOT_17),
132 MESON_PIN(BOOT_18),
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]133};
134
135static const struct pinctrl_pin_desc meson8_aobus_pins[] = {
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]136 MESON_PIN(GPIOAO_0),
137 MESON_PIN(GPIOAO_1),
138 MESON_PIN(GPIOAO_2),
139 MESON_PIN(GPIOAO_3),
140 MESON_PIN(GPIOAO_4),
141 MESON_PIN(GPIOAO_5),
142 MESON_PIN(GPIOAO_6),
143 MESON_PIN(GPIOAO_7),
144 MESON_PIN(GPIOAO_8),
145 MESON_PIN(GPIOAO_9),
146 MESON_PIN(GPIOAO_10),
147 MESON_PIN(GPIOAO_11),
148 MESON_PIN(GPIOAO_12),
149 MESON_PIN(GPIOAO_13),
150 MESON_PIN(GPIO_BSD_EN),
151 MESON_PIN(GPIO_TEST_N),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]152};
153
154/* bank X */
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]155static const unsigned int sd_d0_a_pins[] = { GPIOX_0 };
156static const unsigned int sd_d1_a_pins[] = { GPIOX_1 };
157static const unsigned int sd_d2_a_pins[] = { GPIOX_2 };
158static const unsigned int sd_d3_a_pins[] = { GPIOX_3 };
159static const unsigned int sd_clk_a_pins[] = { GPIOX_8 };
160static const unsigned int sd_cmd_a_pins[] = { GPIOX_9 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]161
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]162static const unsigned int sdxc_d0_a_pins[] = { GPIOX_0 };
163static const unsigned int sdxc_d13_a_pins[] = { GPIOX_1, GPIOX_2, GPIOX_3 };
164static const unsigned int sdxc_d47_a_pins[] = { GPIOX_4, GPIOX_5, GPIOX_6,
165 GPIOX_7 };
166static const unsigned int sdxc_clk_a_pins[] = { GPIOX_8 };
167static const unsigned int sdxc_cmd_a_pins[] = { GPIOX_9 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]168
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]169static const unsigned int pcm_out_a_pins[] = { GPIOX_4 };
170static const unsigned int pcm_in_a_pins[] = { GPIOX_5 };
171static const unsigned int pcm_fs_a_pins[] = { GPIOX_6 };
172static const unsigned int pcm_clk_a_pins[] = { GPIOX_7 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]173
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]174static const unsigned int uart_tx_a0_pins[] = { GPIOX_4 };
175static const unsigned int uart_rx_a0_pins[] = { GPIOX_5 };
176static const unsigned int uart_cts_a0_pins[] = { GPIOX_6 };
177static const unsigned int uart_rts_a0_pins[] = { GPIOX_7 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]178
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]179static const unsigned int uart_tx_a1_pins[] = { GPIOX_12 };
180static const unsigned int uart_rx_a1_pins[] = { GPIOX_13 };
181static const unsigned int uart_cts_a1_pins[] = { GPIOX_14 };
182static const unsigned int uart_rts_a1_pins[] = { GPIOX_15 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]183
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]184static const unsigned int uart_tx_b0_pins[] = { GPIOX_16 };
185static const unsigned int uart_rx_b0_pins[] = { GPIOX_17 };
186static const unsigned int uart_cts_b0_pins[] = { GPIOX_18 };
187static const unsigned int uart_rts_b0_pins[] = { GPIOX_19 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]188
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]189static const unsigned int iso7816_det_pins[] = { GPIOX_16 };
190static const unsigned int iso7816_reset_pins[] = { GPIOX_17 };
191static const unsigned int iso7816_clk_pins[] = { GPIOX_18 };
192static const unsigned int iso7816_data_pins[] = { GPIOX_19 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]193
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]194static const unsigned int i2c_sda_d0_pins[] = { GPIOX_16 };
195static const unsigned int i2c_sck_d0_pins[] = { GPIOX_17 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]196
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]197static const unsigned int xtal_32k_out_pins[] = { GPIOX_10 };
198static const unsigned int xtal_24m_out_pins[] = { GPIOX_11 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]199
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]200static const unsigned int pwm_e_pins[] = { GPIOX_10 };
201static const unsigned int pwm_b_x_pins[] = { GPIOX_11 };
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]202
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]203/* bank Y */
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]204static const unsigned int uart_tx_c_pins[] = { GPIOY_0 };
205static const unsigned int uart_rx_c_pins[] = { GPIOY_1 };
206static const unsigned int uart_cts_c_pins[] = { GPIOY_2 };
207static const unsigned int uart_rts_c_pins[] = { GPIOY_3 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]208
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]209static const unsigned int pcm_out_b_pins[] = { GPIOY_4 };
210static const unsigned int pcm_in_b_pins[] = { GPIOY_5 };
211static const unsigned int pcm_fs_b_pins[] = { GPIOY_6 };
212static const unsigned int pcm_clk_b_pins[] = { GPIOY_7 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]213
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]214static const unsigned int i2c_sda_c0_pins[] = { GPIOY_0 };
215static const unsigned int i2c_sck_c0_pins[] = { GPIOY_1 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]216
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]217static const unsigned int pwm_a_y_pins[] = { GPIOY_16 };
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]218
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]219static const unsigned int i2s_out_ch45_pins[] = { GPIOY_0 };
220static const unsigned int i2s_out_ch23_pins[] = { GPIOY_1 };
221static const unsigned int i2s_out_ch01_pins[] = { GPIOY_4 };
222static const unsigned int i2s_in_ch01_pins[] = { GPIOY_5 };
223static const unsigned int i2s_lr_clk_in_pins[] = { GPIOY_6 };
224static const unsigned int i2s_ao_clk_in_pins[] = { GPIOY_7 };
225static const unsigned int i2s_am_clk_pins[] = { GPIOY_8 };
226static const unsigned int i2s_out_ch78_pins[] = { GPIOY_9 };
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]227
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]228static const unsigned int spdif_in_pins[] = { GPIOY_2 };
229static const unsigned int spdif_out_pins[] = { GPIOY_3 };
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]230
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]231/* bank DV */
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]232static const unsigned int dvin_rgb_pins[] = {
233 GPIODV_0, GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5,
234 GPIODV_6, GPIODV_7, GPIODV_8, GPIODV_9, GPIODV_10, GPIODV_11,
235 GPIODV_12, GPIODV_13, GPIODV_14, GPIODV_15, GPIODV_16, GPIODV_17,
236 GPIODV_18, GPIODV_19, GPIODV_20, GPIODV_21, GPIODV_22, GPIODV_23
237};
238static const unsigned int dvin_vs_pins[] = { GPIODV_24 };
239static const unsigned int dvin_hs_pins[] = { GPIODV_25 };
240static const unsigned int dvin_clk_pins[] = { GPIODV_26 };
241static const unsigned int dvin_de_pins[] = { GPIODV_27 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]242
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]243static const unsigned int enc_0_pins[] = { GPIODV_0 };
244static const unsigned int enc_1_pins[] = { GPIODV_1 };
245static const unsigned int enc_2_pins[] = { GPIODV_2 };
246static const unsigned int enc_3_pins[] = { GPIODV_3 };
247static const unsigned int enc_4_pins[] = { GPIODV_4 };
248static const unsigned int enc_5_pins[] = { GPIODV_5 };
249static const unsigned int enc_6_pins[] = { GPIODV_6 };
250static const unsigned int enc_7_pins[] = { GPIODV_7 };
251static const unsigned int enc_8_pins[] = { GPIODV_8 };
252static const unsigned int enc_9_pins[] = { GPIODV_9 };
253static const unsigned int enc_10_pins[] = { GPIODV_10 };
254static const unsigned int enc_11_pins[] = { GPIODV_11 };
255static const unsigned int enc_12_pins[] = { GPIODV_12 };
256static const unsigned int enc_13_pins[] = { GPIODV_13 };
257static const unsigned int enc_14_pins[] = { GPIODV_14 };
258static const unsigned int enc_15_pins[] = { GPIODV_15 };
259static const unsigned int enc_16_pins[] = { GPIODV_16 };
260static const unsigned int enc_17_pins[] = { GPIODV_17 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]261
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]262static const unsigned int uart_tx_b1_pins[] = { GPIODV_24 };
263static const unsigned int uart_rx_b1_pins[] = { GPIODV_25 };
264static const unsigned int uart_cts_b1_pins[] = { GPIODV_26 };
265static const unsigned int uart_rts_b1_pins[] = { GPIODV_27 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]266
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]267static const unsigned int vga_vs_pins[] = { GPIODV_24 };
268static const unsigned int vga_hs_pins[] = { GPIODV_25 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]269
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]270static const unsigned int pwm_c_dv9_pins[] = { GPIODV_9 };
271static const unsigned int pwm_c_dv29_pins[] = { GPIODV_29 };
272static const unsigned int pwm_d_pins[] = { GPIODV_28 };
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]273
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]274/* bank H */
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]275static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 };
276static const unsigned int hdmi_sda_pins[] = { GPIOH_1 };
277static const unsigned int hdmi_scl_pins[] = { GPIOH_2 };
278static const unsigned int hdmi_cec_pins[] = { GPIOH_3 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]279
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]280static const unsigned int spi_ss0_0_pins[] = { GPIOH_3 };
281static const unsigned int spi_miso_0_pins[] = { GPIOH_4 };
282static const unsigned int spi_mosi_0_pins[] = { GPIOH_5 };
283static const unsigned int spi_sclk_0_pins[] = { GPIOH_6 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]284
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]285static const unsigned int i2c_sda_d1_pins[] = { GPIOH_7 };
286static const unsigned int i2c_sck_d1_pins[] = { GPIOH_8 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]287
288/* bank Z */
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]289static const unsigned int spi_ss0_1_pins[] = { GPIOZ_9 };
290static const unsigned int spi_ss1_1_pins[] = { GPIOZ_10 };
291static const unsigned int spi_sclk_1_pins[] = { GPIOZ_11 };
292static const unsigned int spi_mosi_1_pins[] = { GPIOZ_12 };
293static const unsigned int spi_miso_1_pins[] = { GPIOZ_13 };
294static const unsigned int spi_ss2_1_pins[] = { GPIOZ_14 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]295
Martin Blumenstinglbf6f1462018-04-22 12:53:30 +0200[diff] [blame]296static const unsigned int eth_txd3_pins[] = { GPIOZ_0 };
297static const unsigned int eth_txd2_pins[] = { GPIOZ_1 };
298static const unsigned int eth_rxd3_pins[] = { GPIOZ_2 };
299static const unsigned int eth_rxd2_pins[] = { GPIOZ_3 };
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]300static const unsigned int eth_tx_clk_50m_pins[] = { GPIOZ_4 };
301static const unsigned int eth_tx_en_pins[] = { GPIOZ_5 };
302static const unsigned int eth_txd1_pins[] = { GPIOZ_6 };
303static const unsigned int eth_txd0_pins[] = { GPIOZ_7 };
304static const unsigned int eth_rx_clk_in_pins[] = { GPIOZ_8 };
305static const unsigned int eth_rx_dv_pins[] = { GPIOZ_9 };
306static const unsigned int eth_rxd1_pins[] = { GPIOZ_10 };
307static const unsigned int eth_rxd0_pins[] = { GPIOZ_11 };
308static const unsigned int eth_mdio_pins[] = { GPIOZ_12 };
309static const unsigned int eth_mdc_pins[] = { GPIOZ_13 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]310
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]311static const unsigned int i2c_sda_a0_pins[] = { GPIOZ_0 };
312static const unsigned int i2c_sck_a0_pins[] = { GPIOZ_1 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]313
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]314static const unsigned int i2c_sda_b_pins[] = { GPIOZ_2 };
315static const unsigned int i2c_sck_b_pins[] = { GPIOZ_3 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]316
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]317static const unsigned int i2c_sda_c1_pins[] = { GPIOZ_4 };
318static const unsigned int i2c_sck_c1_pins[] = { GPIOZ_5 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]319
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]320static const unsigned int i2c_sda_a1_pins[] = { GPIOZ_0 };
321static const unsigned int i2c_sck_a1_pins[] = { GPIOZ_1 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]322
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]323static const unsigned int i2c_sda_a2_pins[] = { GPIOZ_0 };
324static const unsigned int i2c_sck_a2_pins[] = { GPIOZ_1 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]325
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]326static const unsigned int pwm_a_z0_pins[] = { GPIOZ_0 };
327static const unsigned int pwm_a_z7_pins[] = { GPIOZ_7 };
328static const unsigned int pwm_b_z_pins[] = { GPIOZ_1 };
329static const unsigned int pwm_c_z_pins[] = { GPIOZ_8 };
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]330
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]331/* bank BOOT */
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]332static const unsigned int sd_d0_c_pins[] = { BOOT_0 };
333static const unsigned int sd_d1_c_pins[] = { BOOT_1 };
334static const unsigned int sd_d2_c_pins[] = { BOOT_2 };
335static const unsigned int sd_d3_c_pins[] = { BOOT_3 };
336static const unsigned int sd_cmd_c_pins[] = { BOOT_16 };
337static const unsigned int sd_clk_c_pins[] = { BOOT_17 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]338
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]339static const unsigned int sdxc_d0_c_pins[] = { BOOT_0};
340static const unsigned int sdxc_d13_c_pins[] = { BOOT_1, BOOT_2, BOOT_3 };
341static const unsigned int sdxc_d47_c_pins[] = { BOOT_4, BOOT_5, BOOT_6,
342 BOOT_7 };
343static const unsigned int sdxc_cmd_c_pins[] = { BOOT_16 };
344static const unsigned int sdxc_clk_c_pins[] = { BOOT_17 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]345
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]346static const unsigned int nand_io_pins[] = {
347 BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7
348};
349static const unsigned int nand_io_ce0_pins[] = { BOOT_8 };
350static const unsigned int nand_io_ce1_pins[] = { BOOT_9 };
351static const unsigned int nand_io_rb0_pins[] = { BOOT_10 };
352static const unsigned int nand_ale_pins[] = { BOOT_11 };
353static const unsigned int nand_cle_pins[] = { BOOT_12 };
354static const unsigned int nand_wen_clk_pins[] = { BOOT_13 };
355static const unsigned int nand_ren_clk_pins[] = { BOOT_14 };
356static const unsigned int nand_dqs_pins[] = { BOOT_15 };
357static const unsigned int nand_ce2_pins[] = { BOOT_16 };
358static const unsigned int nand_ce3_pins[] = { BOOT_17 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]359
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]360static const unsigned int nor_d_pins[] = { BOOT_11 };
361static const unsigned int nor_q_pins[] = { BOOT_12 };
362static const unsigned int nor_c_pins[] = { BOOT_13 };
363static const unsigned int nor_cs_pins[] = { BOOT_18 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]364
365/* bank CARD */
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]366static const unsigned int sd_d1_b_pins[] = { CARD_0 };
367static const unsigned int sd_d0_b_pins[] = { CARD_1 };
368static const unsigned int sd_clk_b_pins[] = { CARD_2 };
369static const unsigned int sd_cmd_b_pins[] = { CARD_3 };
370static const unsigned int sd_d3_b_pins[] = { CARD_4 };
371static const unsigned int sd_d2_b_pins[] = { CARD_5 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]372
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]373static const unsigned int sdxc_d13_b_pins[] = { CARD_0, CARD_4, CARD_5 };
374static const unsigned int sdxc_d0_b_pins[] = { CARD_1 };
375static const unsigned int sdxc_clk_b_pins[] = { CARD_2 };
376static const unsigned int sdxc_cmd_b_pins[] = { CARD_3 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]377
378/* bank AO */
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]379static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 };
380static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 };
381static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 };
382static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]383
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]384static const unsigned int remote_input_pins[] = { GPIOAO_7 };
385static const unsigned int remote_output_ao_pins[] = { GPIOAO_13 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]386
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]387static const unsigned int i2c_slave_sck_ao_pins[] = { GPIOAO_4 };
388static const unsigned int i2c_slave_sda_ao_pins[] = { GPIOAO_5 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]389
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]390static const unsigned int uart_tx_ao_b0_pins[] = { GPIOAO_0 };
391static const unsigned int uart_rx_ao_b0_pins[] = { GPIOAO_1 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]392
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]393static const unsigned int uart_tx_ao_b1_pins[] = { GPIOAO_4 };
394static const unsigned int uart_rx_ao_b1_pins[] = { GPIOAO_5 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]395
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]396static const unsigned int i2c_mst_sck_ao_pins[] = { GPIOAO_4 };
397static const unsigned int i2c_mst_sda_ao_pins[] = { GPIOAO_5 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]398
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]399static const unsigned int pwm_f_ao_pins[] = { GPIO_TEST_N };
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]400
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]401static const unsigned int i2s_am_clk_out_ao_pins[] = { GPIOAO_8 };
402static const unsigned int i2s_ao_clk_out_ao_pins[] = { GPIOAO_9 };
403static const unsigned int i2s_lr_clk_out_ao_pins[] = { GPIOAO_10 };
404static const unsigned int i2s_out_ch01_ao_pins[] = { GPIOAO_11 };
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]405
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]406static const unsigned int hdmi_cec_ao_pins[] = { GPIOAO_12 };
Martin Blumenstinglc21b4322017-05-06 18:57:51 +0200[diff] [blame]407
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]408static struct meson_pmx_group meson8_cbus_groups[] = {
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]409 GPIO_GROUP(GPIOX_0),
410 GPIO_GROUP(GPIOX_1),
411 GPIO_GROUP(GPIOX_2),
412 GPIO_GROUP(GPIOX_3),
413 GPIO_GROUP(GPIOX_4),
414 GPIO_GROUP(GPIOX_5),
415 GPIO_GROUP(GPIOX_6),
416 GPIO_GROUP(GPIOX_7),
417 GPIO_GROUP(GPIOX_8),
418 GPIO_GROUP(GPIOX_9),
419 GPIO_GROUP(GPIOX_10),
420 GPIO_GROUP(GPIOX_11),
421 GPIO_GROUP(GPIOX_12),
422 GPIO_GROUP(GPIOX_13),
423 GPIO_GROUP(GPIOX_14),
424 GPIO_GROUP(GPIOX_15),
425 GPIO_GROUP(GPIOX_16),
426 GPIO_GROUP(GPIOX_17),
427 GPIO_GROUP(GPIOX_18),
428 GPIO_GROUP(GPIOX_19),
429 GPIO_GROUP(GPIOX_20),
430 GPIO_GROUP(GPIOX_21),
431 GPIO_GROUP(GPIOY_0),
432 GPIO_GROUP(GPIOY_1),
433 GPIO_GROUP(GPIOY_2),
434 GPIO_GROUP(GPIOY_3),
435 GPIO_GROUP(GPIOY_4),
436 GPIO_GROUP(GPIOY_5),
437 GPIO_GROUP(GPIOY_6),
438 GPIO_GROUP(GPIOY_7),
439 GPIO_GROUP(GPIOY_8),
440 GPIO_GROUP(GPIOY_9),
441 GPIO_GROUP(GPIOY_10),
442 GPIO_GROUP(GPIOY_11),
443 GPIO_GROUP(GPIOY_12),
444 GPIO_GROUP(GPIOY_13),
445 GPIO_GROUP(GPIOY_14),
446 GPIO_GROUP(GPIOY_15),
447 GPIO_GROUP(GPIOY_16),
448 GPIO_GROUP(GPIODV_0),
449 GPIO_GROUP(GPIODV_1),
450 GPIO_GROUP(GPIODV_2),
451 GPIO_GROUP(GPIODV_3),
452 GPIO_GROUP(GPIODV_4),
453 GPIO_GROUP(GPIODV_5),
454 GPIO_GROUP(GPIODV_6),
455 GPIO_GROUP(GPIODV_7),
456 GPIO_GROUP(GPIODV_8),
457 GPIO_GROUP(GPIODV_9),
458 GPIO_GROUP(GPIODV_10),
459 GPIO_GROUP(GPIODV_11),
460 GPIO_GROUP(GPIODV_12),
461 GPIO_GROUP(GPIODV_13),
462 GPIO_GROUP(GPIODV_14),
463 GPIO_GROUP(GPIODV_15),
464 GPIO_GROUP(GPIODV_16),
465 GPIO_GROUP(GPIODV_17),
466 GPIO_GROUP(GPIODV_18),
467 GPIO_GROUP(GPIODV_19),
468 GPIO_GROUP(GPIODV_20),
469 GPIO_GROUP(GPIODV_21),
470 GPIO_GROUP(GPIODV_22),
471 GPIO_GROUP(GPIODV_23),
472 GPIO_GROUP(GPIODV_24),
473 GPIO_GROUP(GPIODV_25),
474 GPIO_GROUP(GPIODV_26),
475 GPIO_GROUP(GPIODV_27),
476 GPIO_GROUP(GPIODV_28),
477 GPIO_GROUP(GPIODV_29),
478 GPIO_GROUP(GPIOH_0),
479 GPIO_GROUP(GPIOH_1),
480 GPIO_GROUP(GPIOH_2),
481 GPIO_GROUP(GPIOH_3),
482 GPIO_GROUP(GPIOH_4),
483 GPIO_GROUP(GPIOH_5),
484 GPIO_GROUP(GPIOH_6),
485 GPIO_GROUP(GPIOH_7),
486 GPIO_GROUP(GPIOH_8),
487 GPIO_GROUP(GPIOH_9),
488 GPIO_GROUP(GPIOZ_0),
489 GPIO_GROUP(GPIOZ_1),
490 GPIO_GROUP(GPIOZ_2),
491 GPIO_GROUP(GPIOZ_3),
492 GPIO_GROUP(GPIOZ_4),
493 GPIO_GROUP(GPIOZ_5),
494 GPIO_GROUP(GPIOZ_6),
495 GPIO_GROUP(GPIOZ_7),
496 GPIO_GROUP(GPIOZ_8),
497 GPIO_GROUP(GPIOZ_9),
498 GPIO_GROUP(GPIOZ_10),
499 GPIO_GROUP(GPIOZ_11),
500 GPIO_GROUP(GPIOZ_12),
501 GPIO_GROUP(GPIOZ_13),
502 GPIO_GROUP(GPIOZ_14),
Martin Blumenstingl619cdd12018-12-09 20:50:54 +0100[diff] [blame]503 GPIO_GROUP(CARD_0),
504 GPIO_GROUP(CARD_1),
505 GPIO_GROUP(CARD_2),
506 GPIO_GROUP(CARD_3),
507 GPIO_GROUP(CARD_4),
508 GPIO_GROUP(CARD_5),
509 GPIO_GROUP(CARD_6),
510 GPIO_GROUP(BOOT_0),
511 GPIO_GROUP(BOOT_1),
512 GPIO_GROUP(BOOT_2),
513 GPIO_GROUP(BOOT_3),
514 GPIO_GROUP(BOOT_4),
515 GPIO_GROUP(BOOT_5),
516 GPIO_GROUP(BOOT_6),
517 GPIO_GROUP(BOOT_7),
518 GPIO_GROUP(BOOT_8),
519 GPIO_GROUP(BOOT_9),
520 GPIO_GROUP(BOOT_10),
521 GPIO_GROUP(BOOT_11),
522 GPIO_GROUP(BOOT_12),
523 GPIO_GROUP(BOOT_13),
524 GPIO_GROUP(BOOT_14),
525 GPIO_GROUP(BOOT_15),
526 GPIO_GROUP(BOOT_16),
527 GPIO_GROUP(BOOT_17),
528 GPIO_GROUP(BOOT_18),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]529
530 /* bank X */
531 GROUP(sd_d0_a, 8, 5),
532 GROUP(sd_d1_a, 8, 4),
533 GROUP(sd_d2_a, 8, 3),
534 GROUP(sd_d3_a, 8, 2),
535 GROUP(sd_clk_a, 8, 1),
536 GROUP(sd_cmd_a, 8, 0),
537
538 GROUP(sdxc_d0_a, 5, 14),
539 GROUP(sdxc_d13_a, 5, 13),
540 GROUP(sdxc_d47_a, 5, 12),
541 GROUP(sdxc_clk_a, 5, 11),
542 GROUP(sdxc_cmd_a, 5, 10),
543
544 GROUP(pcm_out_a, 3, 30),
545 GROUP(pcm_in_a, 3, 29),
546 GROUP(pcm_fs_a, 3, 28),
547 GROUP(pcm_clk_a, 3, 27),
548
549 GROUP(uart_tx_a0, 4, 17),
550 GROUP(uart_rx_a0, 4, 16),
551 GROUP(uart_cts_a0, 4, 15),
552 GROUP(uart_rts_a0, 4, 14),
553
554 GROUP(uart_tx_a1, 4, 13),
555 GROUP(uart_rx_a1, 4, 12),
556 GROUP(uart_cts_a1, 4, 11),
557 GROUP(uart_rts_a1, 4, 10),
558
559 GROUP(uart_tx_b0, 4, 9),
560 GROUP(uart_rx_b0, 4, 8),
561 GROUP(uart_cts_b0, 4, 7),
562 GROUP(uart_rts_b0, 4, 6),
563
564 GROUP(iso7816_det, 4, 21),
565 GROUP(iso7816_reset, 4, 20),
566 GROUP(iso7816_clk, 4, 19),
567 GROUP(iso7816_data, 4, 18),
568
569 GROUP(i2c_sda_d0, 4, 5),
570 GROUP(i2c_sck_d0, 4, 4),
571
572 GROUP(xtal_32k_out, 3, 22),
573 GROUP(xtal_24m_out, 3, 23),
574
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]575 GROUP(pwm_e, 9, 19),
576 GROUP(pwm_b_x, 2, 3),
577
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]578 /* bank Y */
579 GROUP(uart_tx_c, 1, 19),
580 GROUP(uart_rx_c, 1, 18),
581 GROUP(uart_cts_c, 1, 17),
582 GROUP(uart_rts_c, 1, 16),
583
584 GROUP(pcm_out_b, 4, 25),
585 GROUP(pcm_in_b, 4, 24),
586 GROUP(pcm_fs_b, 4, 23),
587 GROUP(pcm_clk_b, 4, 22),
588
589 GROUP(i2c_sda_c0, 1, 15),
590 GROUP(i2c_sck_c0, 1, 14),
591
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]592 GROUP(pwm_a_y, 9, 14),
593
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]594 GROUP(i2s_out_ch45, 1, 10),
595 GROUP(i2s_out_ch23, 1, 19),
596 GROUP(i2s_out_ch01, 1, 6),
597 GROUP(i2s_in_ch01, 1, 5),
598 GROUP(i2s_lr_clk_in, 1, 4),
599 GROUP(i2s_ao_clk_in, 1, 2),
600 GROUP(i2s_am_clk, 1, 0),
601 GROUP(i2s_out_ch78, 1, 11),
602
603 GROUP(spdif_in, 1, 8),
604 GROUP(spdif_out, 1, 7),
605
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]606 /* bank DV */
607 GROUP(dvin_rgb, 0, 6),
608 GROUP(dvin_vs, 0, 9),
609 GROUP(dvin_hs, 0, 8),
610 GROUP(dvin_clk, 0, 7),
611 GROUP(dvin_de, 0, 10),
612
613 GROUP(enc_0, 7, 0),
614 GROUP(enc_1, 7, 1),
615 GROUP(enc_2, 7, 2),
616 GROUP(enc_3, 7, 3),
617 GROUP(enc_4, 7, 4),
618 GROUP(enc_5, 7, 5),
619 GROUP(enc_6, 7, 6),
620 GROUP(enc_7, 7, 7),
621 GROUP(enc_8, 7, 8),
622 GROUP(enc_9, 7, 9),
623 GROUP(enc_10, 7, 10),
624 GROUP(enc_11, 7, 11),
625 GROUP(enc_12, 7, 12),
626 GROUP(enc_13, 7, 13),
627 GROUP(enc_14, 7, 14),
628 GROUP(enc_15, 7, 15),
629 GROUP(enc_16, 7, 16),
630 GROUP(enc_17, 7, 17),
631
632 GROUP(uart_tx_b1, 6, 23),
633 GROUP(uart_rx_b1, 6, 22),
634 GROUP(uart_cts_b1, 6, 21),
635 GROUP(uart_rts_b1, 6, 20),
636
637 GROUP(vga_vs, 0, 21),
638 GROUP(vga_hs, 0, 20),
639
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]640 GROUP(pwm_c_dv9, 3, 24),
641 GROUP(pwm_c_dv29, 3, 25),
642 GROUP(pwm_d, 3, 26),
643
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]644 /* bank H */
645 GROUP(hdmi_hpd, 1, 26),
646 GROUP(hdmi_sda, 1, 25),
647 GROUP(hdmi_scl, 1, 24),
648 GROUP(hdmi_cec, 1, 23),
649
650 GROUP(spi_ss0_0, 9, 13),
651 GROUP(spi_miso_0, 9, 12),
652 GROUP(spi_mosi_0, 9, 11),
653 GROUP(spi_sclk_0, 9, 10),
654
655 GROUP(i2c_sda_d1, 4, 3),
656 GROUP(i2c_sck_d1, 4, 2),
657
658 /* bank Z */
659 GROUP(spi_ss0_1, 8, 16),
660 GROUP(spi_ss1_1, 8, 12),
661 GROUP(spi_sclk_1, 8, 15),
662 GROUP(spi_mosi_1, 8, 14),
663 GROUP(spi_miso_1, 8, 13),
664 GROUP(spi_ss2_1, 8, 17),
665
666 GROUP(eth_tx_clk_50m, 6, 15),
667 GROUP(eth_tx_en, 6, 14),
668 GROUP(eth_txd1, 6, 13),
669 GROUP(eth_txd0, 6, 12),
670 GROUP(eth_rx_clk_in, 6, 10),
671 GROUP(eth_rx_dv, 6, 11),
672 GROUP(eth_rxd1, 6, 8),
673 GROUP(eth_rxd0, 6, 7),
674 GROUP(eth_mdio, 6, 6),
675 GROUP(eth_mdc, 6, 5),
676
Martin Blumenstinglbf6f1462018-04-22 12:53:30 +0200[diff] [blame]677 /* NOTE: the following four groups are only available on Meson8m2: */
678 GROUP(eth_rxd2, 6, 3),
679 GROUP(eth_rxd3, 6, 2),
680 GROUP(eth_txd2, 6, 1),
681 GROUP(eth_txd3, 6, 0),
682
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]683 GROUP(i2c_sda_a0, 5, 31),
684 GROUP(i2c_sck_a0, 5, 30),
685
686 GROUP(i2c_sda_b, 5, 27),
687 GROUP(i2c_sck_b, 5, 26),
688
689 GROUP(i2c_sda_c1, 5, 25),
690 GROUP(i2c_sck_c1, 5, 24),
691
692 GROUP(i2c_sda_a1, 5, 9),
693 GROUP(i2c_sck_a1, 5, 8),
694
695 GROUP(i2c_sda_a2, 5, 7),
696 GROUP(i2c_sck_a2, 5, 6),
697
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]698 GROUP(pwm_a_z0, 9, 16),
699 GROUP(pwm_a_z7, 2, 0),
700 GROUP(pwm_b_z, 9, 15),
701 GROUP(pwm_c_z, 2, 1),
702
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]703 /* bank BOOT */
704 GROUP(sd_d0_c, 6, 29),
705 GROUP(sd_d1_c, 6, 28),
706 GROUP(sd_d2_c, 6, 27),
707 GROUP(sd_d3_c, 6, 26),
708 GROUP(sd_cmd_c, 6, 25),
709 GROUP(sd_clk_c, 6, 24),
710
711 GROUP(sdxc_d0_c, 4, 30),
712 GROUP(sdxc_d13_c, 4, 29),
713 GROUP(sdxc_d47_c, 4, 28),
714 GROUP(sdxc_cmd_c, 4, 27),
715 GROUP(sdxc_clk_c, 4, 26),
716
717 GROUP(nand_io, 2, 26),
718 GROUP(nand_io_ce0, 2, 25),
719 GROUP(nand_io_ce1, 2, 24),
720 GROUP(nand_io_rb0, 2, 17),
721 GROUP(nand_ale, 2, 21),
722 GROUP(nand_cle, 2, 20),
723 GROUP(nand_wen_clk, 2, 19),
724 GROUP(nand_ren_clk, 2, 18),
725 GROUP(nand_dqs, 2, 27),
726 GROUP(nand_ce2, 2, 23),
727 GROUP(nand_ce3, 2, 22),
728
729 GROUP(nor_d, 5, 1),
730 GROUP(nor_q, 5, 3),
731 GROUP(nor_c, 5, 2),
732 GROUP(nor_cs, 5, 0),
733
734 /* bank CARD */
735 GROUP(sd_d1_b, 2, 14),
736 GROUP(sd_d0_b, 2, 15),
737 GROUP(sd_clk_b, 2, 11),
738 GROUP(sd_cmd_b, 2, 10),
739 GROUP(sd_d3_b, 2, 12),
740 GROUP(sd_d2_b, 2, 13),
741
742 GROUP(sdxc_d13_b, 2, 6),
743 GROUP(sdxc_d0_b, 2, 7),
744 GROUP(sdxc_clk_b, 2, 5),
745 GROUP(sdxc_cmd_b, 2, 4),
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]746};
747
748static struct meson_pmx_group meson8_aobus_groups[] = {
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]749 GPIO_GROUP(GPIOAO_0),
750 GPIO_GROUP(GPIOAO_1),
751 GPIO_GROUP(GPIOAO_2),
752 GPIO_GROUP(GPIOAO_3),
753 GPIO_GROUP(GPIOAO_4),
754 GPIO_GROUP(GPIOAO_5),
755 GPIO_GROUP(GPIOAO_6),
756 GPIO_GROUP(GPIOAO_7),
757 GPIO_GROUP(GPIOAO_8),
758 GPIO_GROUP(GPIOAO_9),
759 GPIO_GROUP(GPIOAO_10),
760 GPIO_GROUP(GPIOAO_11),
761 GPIO_GROUP(GPIOAO_12),
762 GPIO_GROUP(GPIOAO_13),
763 GPIO_GROUP(GPIO_BSD_EN),
764 GPIO_GROUP(GPIO_TEST_N),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]765
766 /* bank AO */
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]767 GROUP(uart_tx_ao_a, 0, 12),
768 GROUP(uart_rx_ao_a, 0, 11),
769 GROUP(uart_cts_ao_a, 0, 10),
770 GROUP(uart_rts_ao_a, 0, 9),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]771
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]772 GROUP(remote_input, 0, 0),
Martin Blumenstingle70a3842017-05-06 18:57:50 +0200[diff] [blame]773 GROUP(remote_output_ao, 0, 31),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]774
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]775 GROUP(i2c_slave_sck_ao, 0, 2),
776 GROUP(i2c_slave_sda_ao, 0, 1),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]777
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]778 GROUP(uart_tx_ao_b0, 0, 26),
779 GROUP(uart_rx_ao_b0, 0, 25),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]780
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]781 GROUP(uart_tx_ao_b1, 0, 24),
782 GROUP(uart_rx_ao_b1, 0, 23),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]783
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]784 GROUP(i2c_mst_sck_ao, 0, 6),
785 GROUP(i2c_mst_sda_ao, 0, 5),
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]786
787 GROUP(pwm_f_ao, 0, 19),
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]788
789 GROUP(i2s_am_clk_out_ao, 0, 30),
790 GROUP(i2s_ao_clk_out_ao, 0, 29),
791 GROUP(i2s_lr_clk_out_ao, 0, 28),
792 GROUP(i2s_out_ch01_ao, 0, 27),
Martin Blumenstinglc21b4322017-05-06 18:57:51 +0200[diff] [blame]793
794 GROUP(hdmi_cec_ao, 0, 17),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]795};
796
Martin Blumenstingl8e5ba8b2018-12-09 20:50:52 +0100[diff] [blame]797static const char * const gpio_periphs_groups[] = {
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]798 "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
799 "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
800 "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
801 "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
802 "GPIOX_20", "GPIOX_21",
803
804 "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4",
805 "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9",
806 "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14",
807 "GPIOY_15", "GPIOY_16",
808
809 "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4",
810 "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9",
811 "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14",
812 "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19",
813 "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24",
814 "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29",
815
816 "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
817 "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9",
818
819 "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
820 "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
821 "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14",
822
823 "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
824 "CARD_5", "CARD_6",
825
826 "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
827 "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
828 "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
829 "BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18",
Martin Blumenstingl42f9b482018-12-09 20:50:50 +0100[diff] [blame]830};
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]831
Martin Blumenstingl42f9b482018-12-09 20:50:50 +0100[diff] [blame]832static const char * const gpio_aobus_groups[] = {
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]833 "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3",
834 "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7",
835 "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11",
836 "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N"
837};
838
839static const char * const sd_a_groups[] = {
840 "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a", "sd_cmd_a"
841};
842
843static const char * const sdxc_a_groups[] = {
844 "sdxc_d0_a", "sdxc_d13_a", "sdxc_d47_a", "sdxc_clk_a", "sdxc_cmd_a"
845};
846
847static const char * const pcm_a_groups[] = {
848 "pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a"
849};
850
851static const char * const uart_a_groups[] = {
852 "uart_tx_a0", "uart_rx_a0", "uart_cts_a0", "uart_rts_a0",
853 "uart_tx_a1", "uart_rx_a1", "uart_cts_a1", "uart_rts_a1"
854};
855
856static const char * const uart_b_groups[] = {
857 "uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0",
858 "uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1"
859};
860
861static const char * const iso7816_groups[] = {
862 "iso7816_det", "iso7816_reset", "iso7816_clk", "iso7816_data"
863};
864
865static const char * const i2c_d_groups[] = {
866 "i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1"
867};
868
869static const char * const xtal_groups[] = {
870 "xtal_32k_out", "xtal_24m_out"
871};
872
873static const char * const uart_c_groups[] = {
874 "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c"
875};
876
877static const char * const pcm_b_groups[] = {
878 "pcm_out_b", "pcm_in_b", "pcm_fs_b", "pcm_clk_b"
879};
880
881static const char * const i2c_c_groups[] = {
882 "i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1"
883};
884
885static const char * const dvin_groups[] = {
886 "dvin_rgb", "dvin_vs", "dvin_hs", "dvin_clk", "dvin_de"
887};
888
889static const char * const enc_groups[] = {
890 "enc_0", "enc_1", "enc_2", "enc_3", "enc_4", "enc_5",
891 "enc_6", "enc_7", "enc_8", "enc_9", "enc_10", "enc_11",
892 "enc_12", "enc_13", "enc_14", "enc_15", "enc_16", "enc_17"
893};
894
895static const char * const vga_groups[] = {
896 "vga_vs", "vga_hs"
897};
898
899static const char * const hdmi_groups[] = {
900 "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec"
901};
902
903static const char * const spi_groups[] = {
904 "spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0",
905 "spi_ss0_1", "spi_ss1_1", "spi_sclk_1", "spi_mosi_1",
906 "spi_miso_1", "spi_ss2_1"
907};
908
909static const char * const ethernet_groups[] = {
910 "eth_tx_clk_50m", "eth_tx_en", "eth_txd1",
911 "eth_txd0", "eth_rx_clk_in", "eth_rx_dv",
Martin Blumenstinglbf6f1462018-04-22 12:53:30 +0200[diff] [blame]912 "eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc", "eth_rxd2",
913 "eth_rxd3", "eth_txd2", "eth_txd3"
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]914};
915
916static const char * const i2c_a_groups[] = {
917 "i2c_sda_a0", "i2c_sck_a0", "i2c_sda_a1", "i2c_sck_a1",
918 "i2c_sda_a2", "i2c_sck_a2"
919};
920
921static const char * const i2c_b_groups[] = {
922 "i2c_sda_b", "i2c_sck_b"
923};
924
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]925static const char * const i2s_groups[] = {
926 "i2s_out_ch45", "i2s_out_ch23_pins", "i2s_out_ch01_pins",
927 "i2s_in_ch01_pins", "i2s_lr_clk_in_pins", "i2s_ao_clk_in_pins",
928 "i2s_am_clk_pins", "i2s_out_ch78_pins"
929};
930
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]931static const char * const sd_c_groups[] = {
932 "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c",
933 "sd_cmd_c", "sd_clk_c"
934};
935
936static const char * const sdxc_c_groups[] = {
937 "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c",
938 "sdxc_clk_c"
939};
940
941static const char * const nand_groups[] = {
942 "nand_io", "nand_io_ce0", "nand_io_ce1",
943 "nand_io_rb0", "nand_ale", "nand_cle",
944 "nand_wen_clk", "nand_ren_clk", "nand_dqs",
945 "nand_ce2", "nand_ce3"
946};
947
948static const char * const nor_groups[] = {
949 "nor_d", "nor_q", "nor_c", "nor_cs"
950};
951
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]952static const char * const pwm_a_groups[] = {
953 "pwm_a_y", "pwm_a_z0", "pwm_a_z7"
954};
955
956static const char * const pwm_b_groups[] = {
957 "pwm_b_x", "pwm_b_z"
958};
959
960static const char * const pwm_c_groups[] = {
961 "pwm_c_dv9", "pwm_c_dv29", "pwm_c_z"
962};
963
964static const char * const pwm_d_groups[] = {
965 "pwm_d"
966};
967
968static const char * const pwm_e_groups[] = {
969 "pwm_e"
970};
971
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]972static const char * const sd_b_groups[] = {
973 "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b",
974 "sd_d3_b", "sd_d2_b"
975};
976
977static const char * const sdxc_b_groups[] = {
978 "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b"
979};
980
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]981static const char * const spdif_groups[] = {
982 "spdif_in", "spdif_out"
983};
984
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]985static const char * const uart_ao_groups[] = {
986 "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a"
987};
988
989static const char * const remote_groups[] = {
Martin Blumenstingle70a3842017-05-06 18:57:50 +0200[diff] [blame]990 "remote_input", "remote_output_ao"
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]991};
992
993static const char * const i2c_slave_ao_groups[] = {
994 "i2c_slave_sck_ao", "i2c_slave_sda_ao"
995};
996
997static const char * const uart_ao_b_groups[] = {
998 "uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1"
999};
1000
1001static const char * const i2c_mst_ao_groups[] = {
1002 "i2c_mst_sck_ao", "i2c_mst_sda_ao"
1003};
1004
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]1005static const char * const pwm_f_ao_groups[] = {
1006 "pwm_f_ao"
1007};
1008
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]1009static const char * const i2s_ao_groups[] = {
1010 "i2s_am_clk_out_ao", "i2s_ao_clk_out_ao", "i2s_lr_clk_out_ao",
1011 "i2s_out_ch01_ao"
1012};
1013
Martin Blumenstinglc21b4322017-05-06 18:57:51 +0200[diff] [blame]1014static const char * const hdmi_cec_ao_groups[] = {
1015 "hdmi_cec_ao"
1016};
1017
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]1018static struct meson_pmx_func meson8_cbus_functions[] = {
Martin Blumenstingl8e5ba8b2018-12-09 20:50:52 +0100[diff] [blame]1019 FUNCTION(gpio_periphs),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]1020 FUNCTION(sd_a),
1021 FUNCTION(sdxc_a),
1022 FUNCTION(pcm_a),
1023 FUNCTION(uart_a),
1024 FUNCTION(uart_b),
1025 FUNCTION(iso7816),
1026 FUNCTION(i2c_d),
1027 FUNCTION(xtal),
1028 FUNCTION(uart_c),
1029 FUNCTION(pcm_b),
1030 FUNCTION(i2c_c),
1031 FUNCTION(dvin),
1032 FUNCTION(enc),
1033 FUNCTION(vga),
1034 FUNCTION(hdmi),
1035 FUNCTION(spi),
1036 FUNCTION(ethernet),
1037 FUNCTION(i2c_a),
1038 FUNCTION(i2c_b),
1039 FUNCTION(sd_c),
1040 FUNCTION(sdxc_c),
1041 FUNCTION(nand),
1042 FUNCTION(nor),
1043 FUNCTION(sd_b),
1044 FUNCTION(sdxc_b),
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]1045 FUNCTION(pwm_a),
1046 FUNCTION(pwm_b),
1047 FUNCTION(pwm_c),
1048 FUNCTION(pwm_d),
1049 FUNCTION(pwm_e),
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]1050 FUNCTION(i2s),
1051 FUNCTION(spdif),
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]1052};
1053
1054static struct meson_pmx_func meson8_aobus_functions[] = {
Martin Blumenstingl42f9b482018-12-09 20:50:50 +0100[diff] [blame]1055 FUNCTION(gpio_aobus),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]1056 FUNCTION(uart_ao),
1057 FUNCTION(remote),
1058 FUNCTION(i2c_slave_ao),
1059 FUNCTION(uart_ao_b),
1060 FUNCTION(i2c_mst_ao),
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]1061 FUNCTION(pwm_f_ao),
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]1062 FUNCTION(i2s_ao),
Martin Blumenstinglc21b4322017-05-06 18:57:51 +0200[diff] [blame]1063 FUNCTION(hdmi_cec_ao),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]1064};
1065
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]1066static struct meson_bank meson8_cbus_banks[] = {
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]1067 /* name first last irq pullen pull dir out in */
1068 BANK("X", GPIOX_0, GPIOX_21, 112, 133, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
1069 BANK("Y", GPIOY_0, GPIOY_16, 95, 111, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
1070 BANK("DV", GPIODV_0, GPIODV_29, 65, 94, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
1071 BANK("H", GPIOH_0, GPIOH_9, 29, 38, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
1072 BANK("Z", GPIOZ_0, GPIOZ_14, 14, 28, 1, 0, 1, 0, 3, 17, 4, 17, 5, 17),
1073 BANK("CARD", CARD_0, CARD_6, 58, 64, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
1074 BANK("BOOT", BOOT_0, BOOT_18, 39, 57, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]1075};
1076
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]1077static struct meson_bank meson8_aobus_banks[] = {
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]1078 /* name first last irq pullen pull dir out in */
Jerome Brunete91b1622018-10-29 16:13:39 +0100[diff] [blame]1079 BANK("AO", GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]1080};
1081
Jerome Brunet277d14e2017-10-12 14:40:25 +0200[diff] [blame]1082static struct meson_pinctrl_data meson8_cbus_pinctrl_data = {
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200[diff] [blame]1083 .name = "cbus-banks",
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]1084 .pins = meson8_cbus_pins,
1085 .groups = meson8_cbus_groups,
1086 .funcs = meson8_cbus_functions,
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200[diff] [blame]1087 .banks = meson8_cbus_banks,
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]1088 .num_pins = ARRAY_SIZE(meson8_cbus_pins),
1089 .num_groups = ARRAY_SIZE(meson8_cbus_groups),
1090 .num_funcs = ARRAY_SIZE(meson8_cbus_functions),
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200[diff] [blame]1091 .num_banks = ARRAY_SIZE(meson8_cbus_banks),
Jerome Brunetce385aa2017-10-12 14:40:26 +0200[diff] [blame]1092 .pmx_ops = &meson8_pmx_ops,
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]1093};
1094
Jerome Brunet277d14e2017-10-12 14:40:25 +0200[diff] [blame]1095static struct meson_pinctrl_data meson8_aobus_pinctrl_data = {
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200[diff] [blame]1096 .name = "ao-bank",
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]1097 .pins = meson8_aobus_pins,
1098 .groups = meson8_aobus_groups,
1099 .funcs = meson8_aobus_functions,
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200[diff] [blame]1100 .banks = meson8_aobus_banks,
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]1101 .num_pins = ARRAY_SIZE(meson8_aobus_pins),
1102 .num_groups = ARRAY_SIZE(meson8_aobus_groups),
1103 .num_funcs = ARRAY_SIZE(meson8_aobus_functions),
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200[diff] [blame]1104 .num_banks = ARRAY_SIZE(meson8_aobus_banks),
Jerome Brunetce385aa2017-10-12 14:40:26 +0200[diff] [blame]1105 .pmx_ops = &meson8_pmx_ops,
Qianggui Songfd422962019-11-15 20:03:47 +0800[diff] [blame]1106 .parse_dt = &meson8_aobus_parse_dt_extra,
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]1107};
Jerome Brunet277d14e2017-10-12 14:40:25 +0200[diff] [blame]1108
1109static const struct of_device_id meson8_pinctrl_dt_match[] = {
1110 {
1111 .compatible = "amlogic,meson8-cbus-pinctrl",
1112 .data = &meson8_cbus_pinctrl_data,
1113 },
1114 {
1115 .compatible = "amlogic,meson8-aobus-pinctrl",
1116 .data = &meson8_aobus_pinctrl_data,
1117 },
Martin Blumenstinglb0d46cb2018-04-22 12:53:29 +0200[diff] [blame]1118 {
1119 .compatible = "amlogic,meson8m2-cbus-pinctrl",
1120 .data = &meson8_cbus_pinctrl_data,
1121 },
1122 {
1123 .compatible = "amlogic,meson8m2-aobus-pinctrl",
1124 .data = &meson8_aobus_pinctrl_data,
1125 },
Jerome Brunet277d14e2017-10-12 14:40:25 +0200[diff] [blame]1126 { },
1127};
1128
1129static struct platform_driver meson8_pinctrl_driver = {
1130 .probe = meson_pinctrl_probe,
1131 .driver = {
1132 .name = "meson8-pinctrl",
1133 .of_match_table = meson8_pinctrl_dt_match,
1134 },
1135};
1136builtin_platform_driver(meson8_pinctrl_driver);