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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 2572da44a51192ad181482c1989e66e5eb47dcbe / . / drivers / pinctrl / freescale / pinctrl-imx8mq.c
blob: 3ed3c98bcedb6a1e9e93b697a095713f98f75dff [file] [log] [blame]
Lucas Stach45b85fc2018-07-02 14:59:06 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP
5 * Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
6 */
7
8#include <linux/err.h>
9#include <linux/init.h>
10#include <linux/io.h>
Anson Huange38b6bb2020-06-24 14:24:00 +0800[diff] [blame]11#include <linux/module.h>
Lucas Stach45b85fc2018-07-02 14:59:06 +0300[diff] [blame]12#include <linux/of.h>
13#include <linux/of_device.h>
14#include <linux/pinctrl/pinctrl.h>
15
16#include "pinctrl-imx.h"
17
18enum imx8mq_pads {
19 MX8MQ_PAD_RESERVE0 = 0,
20 MX8MQ_PAD_RESERVE1 = 1,
21 MX8MQ_PAD_RESERVE2 = 2,
22 MX8MQ_PAD_RESERVE3 = 3,
23 MX8MQ_PAD_RESERVE4 = 4,
24 MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX = 5,
25 MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX = 6,
26 MX8MQ_IOMUXC_ONOFF_SNVSMIX = 7,
27 MX8MQ_IOMUXC_POR_B_SNVSMIX = 8,
28 MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX = 9,
29 MX8MQ_IOMUXC_GPIO1_IO00 = 10,
30 MX8MQ_IOMUXC_GPIO1_IO01 = 11,
31 MX8MQ_IOMUXC_GPIO1_IO02 = 12,
32 MX8MQ_IOMUXC_GPIO1_IO03 = 13,
33 MX8MQ_IOMUXC_GPIO1_IO04 = 14,
34 MX8MQ_IOMUXC_GPIO1_IO05 = 15,
35 MX8MQ_IOMUXC_GPIO1_IO06 = 16,
36 MX8MQ_IOMUXC_GPIO1_IO07 = 17,
37 MX8MQ_IOMUXC_GPIO1_IO08 = 18,
38 MX8MQ_IOMUXC_GPIO1_IO09 = 19,
39 MX8MQ_IOMUXC_GPIO1_IO10 = 20,
40 MX8MQ_IOMUXC_GPIO1_IO11 = 21,
41 MX8MQ_IOMUXC_GPIO1_IO12 = 22,
42 MX8MQ_IOMUXC_GPIO1_IO13 = 23,
43 MX8MQ_IOMUXC_GPIO1_IO14 = 24,
44 MX8MQ_IOMUXC_GPIO1_IO15 = 25,
45 MX8MQ_IOMUXC_ENET_MDC = 26,
46 MX8MQ_IOMUXC_ENET_MDIO = 27,
47 MX8MQ_IOMUXC_ENET_TD3 = 28,
48 MX8MQ_IOMUXC_ENET_TD2 = 29,
49 MX8MQ_IOMUXC_ENET_TD1 = 30,
50 MX8MQ_IOMUXC_ENET_TD0 = 31,
51 MX8MQ_IOMUXC_ENET_TX_CTL = 32,
52 MX8MQ_IOMUXC_ENET_TXC = 33,
53 MX8MQ_IOMUXC_ENET_RX_CTL = 34,
54 MX8MQ_IOMUXC_ENET_RXC = 35,
55 MX8MQ_IOMUXC_ENET_RD0 = 36,
56 MX8MQ_IOMUXC_ENET_RD1 = 37,
57 MX8MQ_IOMUXC_ENET_RD2 = 38,
58 MX8MQ_IOMUXC_ENET_RD3 = 39,
59 MX8MQ_IOMUXC_SD1_CLK = 40,
60 MX8MQ_IOMUXC_SD1_CMD = 41,
61 MX8MQ_IOMUXC_SD1_DATA0 = 42,
62 MX8MQ_IOMUXC_SD1_DATA1 = 43,
63 MX8MQ_IOMUXC_SD1_DATA2 = 44,
64 MX8MQ_IOMUXC_SD1_DATA3 = 45,
65 MX8MQ_IOMUXC_SD1_DATA4 = 46,
66 MX8MQ_IOMUXC_SD1_DATA5 = 47,
67 MX8MQ_IOMUXC_SD1_DATA6 = 48,
68 MX8MQ_IOMUXC_SD1_DATA7 = 49,
69 MX8MQ_IOMUXC_SD1_RESET_B = 50,
70 MX8MQ_IOMUXC_SD1_STROBE = 51,
71 MX8MQ_IOMUXC_SD2_CD_B = 52,
72 MX8MQ_IOMUXC_SD2_CLK = 53,
73 MX8MQ_IOMUXC_SD2_CMD = 54,
74 MX8MQ_IOMUXC_SD2_DATA0 = 55,
75 MX8MQ_IOMUXC_SD2_DATA1 = 56,
76 MX8MQ_IOMUXC_SD2_DATA2 = 57,
77 MX8MQ_IOMUXC_SD2_DATA3 = 58,
78 MX8MQ_IOMUXC_SD2_RESET_B = 59,
79 MX8MQ_IOMUXC_SD2_WP = 60,
80 MX8MQ_IOMUXC_NAND_ALE = 61,
81 MX8MQ_IOMUXC_NAND_CE0_B = 62,
82 MX8MQ_IOMUXC_NAND_CE1_B = 63,
83 MX8MQ_IOMUXC_NAND_CE2_B = 64,
84 MX8MQ_IOMUXC_NAND_CE3_B = 65,
85 MX8MQ_IOMUXC_NAND_CLE = 66,
86 MX8MQ_IOMUXC_NAND_DATA00 = 67,
87 MX8MQ_IOMUXC_NAND_DATA01 = 68,
88 MX8MQ_IOMUXC_NAND_DATA02 = 69,
89 MX8MQ_IOMUXC_NAND_DATA03 = 70,
90 MX8MQ_IOMUXC_NAND_DATA04 = 71,
91 MX8MQ_IOMUXC_NAND_DATA05 = 72,
92 MX8MQ_IOMUXC_NAND_DATA06 = 73,
93 MX8MQ_IOMUXC_NAND_DATA07 = 74,
94 MX8MQ_IOMUXC_NAND_DQS = 75,
95 MX8MQ_IOMUXC_NAND_RE_B = 76,
96 MX8MQ_IOMUXC_NAND_READY_B = 77,
97 MX8MQ_IOMUXC_NAND_WE_B = 78,
98 MX8MQ_IOMUXC_NAND_WP_B = 79,
99 MX8MQ_IOMUXC_SAI5_RXFS = 80,
100 MX8MQ_IOMUXC_SAI5_RXC = 81,
101 MX8MQ_IOMUXC_SAI5_RXD0 = 82,
102 MX8MQ_IOMUXC_SAI5_RXD1 = 83,
103 MX8MQ_IOMUXC_SAI5_RXD2 = 84,
104 MX8MQ_IOMUXC_SAI5_RXD3 = 85,
105 MX8MQ_IOMUXC_SAI5_MCLK = 86,
106 MX8MQ_IOMUXC_SAI1_RXFS = 87,
107 MX8MQ_IOMUXC_SAI1_RXC = 88,
108 MX8MQ_IOMUXC_SAI1_RXD0 = 89,
109 MX8MQ_IOMUXC_SAI1_RXD1 = 90,
110 MX8MQ_IOMUXC_SAI1_RXD2 = 91,
111 MX8MQ_IOMUXC_SAI1_RXD3 = 92,
112 MX8MQ_IOMUXC_SAI1_RXD4 = 93,
113 MX8MQ_IOMUXC_SAI1_RXD5 = 94,
114 MX8MQ_IOMUXC_SAI1_RXD6 = 95,
115 MX8MQ_IOMUXC_SAI1_RXD7 = 96,
116 MX8MQ_IOMUXC_SAI1_TXFS = 97,
117 MX8MQ_IOMUXC_SAI1_TXC = 98,
118 MX8MQ_IOMUXC_SAI1_TXD0 = 99,
119 MX8MQ_IOMUXC_SAI1_TXD1 = 100,
120 MX8MQ_IOMUXC_SAI1_TXD2 = 101,
121 MX8MQ_IOMUXC_SAI1_TXD3 = 102,
122 MX8MQ_IOMUXC_SAI1_TXD4 = 103,
123 MX8MQ_IOMUXC_SAI1_TXD5 = 104,
124 MX8MQ_IOMUXC_SAI1_TXD6 = 105,
125 MX8MQ_IOMUXC_SAI1_TXD7 = 106,
126 MX8MQ_IOMUXC_SAI1_MCLK = 107,
127 MX8MQ_IOMUXC_SAI2_RXFS = 108,
128 MX8MQ_IOMUXC_SAI2_RXC = 109,
129 MX8MQ_IOMUXC_SAI2_RXD0 = 110,
130 MX8MQ_IOMUXC_SAI2_TXFS = 111,
131 MX8MQ_IOMUXC_SAI2_TXC = 112,
132 MX8MQ_IOMUXC_SAI2_TXD0 = 113,
133 MX8MQ_IOMUXC_SAI2_MCLK = 114,
134 MX8MQ_IOMUXC_SAI3_RXFS = 115,
135 MX8MQ_IOMUXC_SAI3_RXC = 116,
136 MX8MQ_IOMUXC_SAI3_RXD = 117,
137 MX8MQ_IOMUXC_SAI3_TXFS = 118,
138 MX8MQ_IOMUXC_SAI3_TXC = 119,
139 MX8MQ_IOMUXC_SAI3_TXD = 120,
140 MX8MQ_IOMUXC_SAI3_MCLK = 121,
141 MX8MQ_IOMUXC_SPDIF_TX = 122,
142 MX8MQ_IOMUXC_SPDIF_RX = 123,
143 MX8MQ_IOMUXC_SPDIF_EXT_CLK = 124,
144 MX8MQ_IOMUXC_ECSPI1_SCLK = 125,
145 MX8MQ_IOMUXC_ECSPI1_MOSI = 126,
146 MX8MQ_IOMUXC_ECSPI1_MISO = 127,
147 MX8MQ_IOMUXC_ECSPI1_SS0 = 128,
148 MX8MQ_IOMUXC_ECSPI2_SCLK = 129,
149 MX8MQ_IOMUXC_ECSPI2_MOSI = 130,
150 MX8MQ_IOMUXC_ECSPI2_MISO = 131,
151 MX8MQ_IOMUXC_ECSPI2_SS0 = 132,
152 MX8MQ_IOMUXC_I2C1_SCL = 133,
153 MX8MQ_IOMUXC_I2C1_SDA = 134,
154 MX8MQ_IOMUXC_I2C2_SCL = 135,
155 MX8MQ_IOMUXC_I2C2_SDA = 136,
156 MX8MQ_IOMUXC_I2C3_SCL = 137,
157 MX8MQ_IOMUXC_I2C3_SDA = 138,
158 MX8MQ_IOMUXC_I2C4_SCL = 139,
159 MX8MQ_IOMUXC_I2C4_SDA = 140,
160 MX8MQ_IOMUXC_UART1_RXD = 141,
161 MX8MQ_IOMUXC_UART1_TXD = 142,
162 MX8MQ_IOMUXC_UART2_RXD = 143,
163 MX8MQ_IOMUXC_UART2_TXD = 144,
164 MX8MQ_IOMUXC_UART3_RXD = 145,
165 MX8MQ_IOMUXC_UART3_TXD = 146,
166 MX8MQ_IOMUXC_UART4_RXD = 147,
167 MX8MQ_IOMUXC_UART4_TXD = 148,
168};
169
170/* Pad names for the pinmux subsystem */
171static const struct pinctrl_pin_desc imx8mq_pinctrl_pads[] = {
172 IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE0),
173 IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE1),
174 IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE2),
175 IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE3),
176 IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE4),
177 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX),
178 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX),
179 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ONOFF_SNVSMIX),
180 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_POR_B_SNVSMIX),
181 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX),
182 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO00),
183 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO01),
184 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO02),
185 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO03),
186 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO04),
187 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO05),
188 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO06),
189 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO07),
190 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO08),
191 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO09),
192 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO10),
193 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO11),
194 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO12),
195 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO13),
196 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO14),
197 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO15),
198 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_MDC),
199 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_MDIO),
200 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD3),
201 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD2),
202 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD1),
203 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD0),
204 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TX_CTL),
205 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TXC),
206 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RX_CTL),
207 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RXC),
208 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD0),
209 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD1),
210 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD2),
211 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD3),
212 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_CLK),
213 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_CMD),
214 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA0),
215 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA1),
216 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA2),
217 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA3),
218 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA4),
219 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA5),
220 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA6),
221 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA7),
222 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_RESET_B),
223 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_STROBE),
224 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_CD_B),
225 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_CLK),
226 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_CMD),
227 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA0),
228 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA1),
229 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA2),
230 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA3),
231 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_RESET_B),
232 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_WP),
233 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_ALE),
234 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE0_B),
235 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE1_B),
236 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE2_B),
237 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE3_B),
238 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CLE),
239 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA00),
240 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA01),
241 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA02),
242 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA03),
243 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA04),
244 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA05),
245 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA06),
246 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA07),
247 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DQS),
248 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_RE_B),
249 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_READY_B),
250 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_WE_B),
251 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_WP_B),
252 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXFS),
253 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXC),
254 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD0),
255 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD1),
256 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD2),
257 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD3),
258 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_MCLK),
259 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXFS),
260 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXC),
261 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD0),
262 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD1),
263 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD2),
264 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD3),
265 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD4),
266 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD5),
267 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD6),
268 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD7),
269 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXFS),
270 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXC),
271 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD0),
272 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD1),
273 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD2),
274 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD3),
275 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD4),
276 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD5),
277 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD6),
278 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD7),
279 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_MCLK),
280 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_RXFS),
281 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_RXC),
282 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_RXD0),
283 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_TXFS),
284 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_TXC),
285 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_TXD0),
286 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_MCLK),
287 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_RXFS),
288 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_RXC),
289 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_RXD),
290 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_TXFS),
291 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_TXC),
292 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_TXD),
293 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_MCLK),
294 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SPDIF_TX),
295 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SPDIF_RX),
296 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SPDIF_EXT_CLK),
297 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_SCLK),
298 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_MOSI),
299 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_MISO),
300 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_SS0),
301 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_SCLK),
302 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_MOSI),
303 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_MISO),
304 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_SS0),
305 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C1_SCL),
306 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C1_SDA),
307 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C2_SCL),
308 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C2_SDA),
309 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C3_SCL),
310 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C3_SDA),
311 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C4_SCL),
312 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C4_SDA),
313 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART1_RXD),
314 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART1_TXD),
315 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART2_RXD),
316 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART2_TXD),
317 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART3_RXD),
318 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART3_TXD),
319 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART4_RXD),
320 IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART4_TXD),
321};
322
323static const struct imx_pinctrl_soc_info imx8mq_pinctrl_info = {
324 .pins = imx8mq_pinctrl_pads,
325 .npins = ARRAY_SIZE(imx8mq_pinctrl_pads),
326 .gpr_compatible = "fsl,imx8mq-iomuxc-gpr",
327};
328
329static const struct of_device_id imx8mq_pinctrl_of_match[] = {
330 { .compatible = "fsl,imx8mq-iomuxc", .data = &imx8mq_pinctrl_info, },
331 { /* sentinel */ }
332};
Anson Huange38b6bb2020-06-24 14:24:00 +0800[diff] [blame]333MODULE_DEVICE_TABLE(of, imx8mq_pinctrl_of_match);
Lucas Stach45b85fc2018-07-02 14:59:06 +0300[diff] [blame]334
335static int imx8mq_pinctrl_probe(struct platform_device *pdev)
336{
337 return imx_pinctrl_probe(pdev, &imx8mq_pinctrl_info);
338}
339
340static struct platform_driver imx8mq_pinctrl_driver = {
341 .driver = {
342 .name = "imx8mq-pinctrl",
Fabio Estevamf6b6db22021-03-28 15:30:33 -0300[diff] [blame]343 .of_match_table = imx8mq_pinctrl_of_match,
Abel Vesa855811e2019-04-08 18:38:31 +0000[diff] [blame]344 .pm = &imx_pinctrl_pm_ops,
Lucas Stach45b85fc2018-07-02 14:59:06 +0300[diff] [blame]345 .suppress_bind_attrs = true,
346 },
347 .probe = imx8mq_pinctrl_probe,
348};
349
350static int __init imx8mq_pinctrl_init(void)
351{
352 return platform_driver_register(&imx8mq_pinctrl_driver);
353}
354arch_initcall(imx8mq_pinctrl_init);
Anson Huange38b6bb2020-06-24 14:24:00 +0800[diff] [blame]355
356MODULE_AUTHOR("Lucas Stach <l.stach@pengutronix.de>");
357MODULE_DESCRIPTION("NXP i.MX8MQ pinctrl driver");
358MODULE_LICENSE("GPL v2");