blob: 6eca2a406ee378f0e842a8db6eecdd4f1b05878e [file] [log] [blame]
Thomas Gleixnerec8f24b2019-05-19 13:07:45 +01001# SPDX-License-Identifier: GPL-2.0-only
Jerome Brunet889c2b72019-02-01 13:58:41 +01002# Amlogic clock drivers
Carlo Caione7a29a862015-06-01 13:13:53 +02003
Jerome Brunet889c2b72019-02-01 13:58:41 +01004obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
Neil Armstrong26d34432019-07-31 10:40:17 +02005obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
Jerome Brunet889c2b72019-02-01 13:58:41 +01006obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
Jerome Brunet6682bd42019-02-01 15:53:45 +01007obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o
Jerome Brunet889c2b72019-02-01 13:58:41 +01008obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o
9obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o
10obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
11obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o
12obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
13obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
14
15# Amlogic Clock controllers
16
17obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
18obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
19obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
Neil Armstrong042f01b2019-02-12 17:28:59 +010020obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
Martin Blumenstingl64aa7002019-11-17 15:07:31 +010021obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o