Thomas Gleixner | ec8f24b | 2019-05-19 13:07:45 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Jerome Brunet | 889c2b7 | 2019-02-01 13:58:41 +0100 | [diff] [blame] | 2 | # Amlogic clock drivers |
Carlo Caione | 7a29a86 | 2015-06-01 13:13:53 +0200 | [diff] [blame] | 3 | |
Jerome Brunet | 889c2b7 | 2019-02-01 13:58:41 +0100 | [diff] [blame] | 4 | obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o |
Neil Armstrong | 26d3443 | 2019-07-31 10:40:17 +0200 | [diff] [blame] | 5 | obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o |
Jerome Brunet | 889c2b7 | 2019-02-01 13:58:41 +0100 | [diff] [blame] | 6 | obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o |
Jerome Brunet | 6682bd4 | 2019-02-01 15:53:45 +0100 | [diff] [blame] | 7 | obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o |
Jerome Brunet | 889c2b7 | 2019-02-01 13:58:41 +0100 | [diff] [blame] | 8 | obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o |
| 9 | obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o |
| 10 | obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o |
| 11 | obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o |
| 12 | obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o |
| 13 | obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o |
| 14 | |
| 15 | # Amlogic Clock controllers |
| 16 | |
| 17 | obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o |
| 18 | obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o |
| 19 | obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o |
Neil Armstrong | 042f01b | 2019-02-12 17:28:59 +0100 | [diff] [blame] | 20 | obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o |
Martin Blumenstingl | 64aa700 | 2019-11-17 15:07:31 +0100 | [diff] [blame] | 21 | obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o |