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Padmavathi Venna40476f62013-01-18 17:17:01 +05301* Samsung I2S controller
2
3Required SoC Specific Properties:
4
Padmavathi Venna7da493e2013-08-12 15:19:51 +05305- compatible : should be one of the following.
6 - samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
7 - samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with
8 secondary fifo, s/w reset control and internal mux for root clk src.
Padmavathi Vennaa5a56872014-11-07 12:24:40 +05309 - samsung,exynos5420-i2s: for 8/16/24bit multichannel(5.1) I2S for
Sylwester Nawrockie2ce8522018-02-12 17:15:32 +010010 playback, stereo channel capture, secondary fifo using internal
Padmavathi Vennaa5a56872014-11-07 12:24:40 +053011 or external dma, s/w reset control, internal mux for root clk src
12 and 7.1 channel TDM support for playback. TDM (Time division multiplexing)
13 is to allow transfer of multiple channel audio data on single data line.
14 - samsung,exynos7-i2s: with all the available features of exynos5 i2s,
15 exynos7 I2S has 7.1 channel TDM support for capture, secondary fifo
16 with only external dma and more no.of root clk sampling frequencies.
17 - samsung,exynos7-i2s1: I2S1 on previous samsung platforms supports
18 stereo channels. exynos7 i2s1 upgraded to 5.1 multichannel with
19 slightly modified bit offsets.
Padmavathi Venna7da493e2013-08-12 15:19:51 +053020
Padmavathi Venna40476f62013-01-18 17:17:01 +053021- reg: physical base address of the controller and length of memory mapped
22 region.
23- dmas: list of DMA controller phandle and DMA request line ordered pairs.
24- dma-names: identifier string for each DMA request line in the dmas property.
25 These strings correspond 1:1 with the ordered pairs in dmas.
Padmavathi Venna4a3afb72013-06-18 00:02:31 +090026- clocks: Handle to iis clock and RCLK source clk.
27- clock-names:
Sylwester Nawrockie2ce8522018-02-12 17:15:32 +010028 i2s0 uses some base clocks from CMU and some are from audio subsystem internal
Padmavathi Venna4a3afb72013-06-18 00:02:31 +090029 clock controller. The clock names for i2s0 should be "iis", "i2s_opclk0" and
30 "i2s_opclk1" as shown in the example below.
31 i2s1 and i2s2 uses clocks from CMU. The clock names for i2s1 and i2s2 should
32 be "iis" and "i2s_opclk0".
33 "iis" is the i2s bus clock and i2s_opclk0, i2s_opclk1 are sources of the root
34 clk. i2s0 has internal mux to select the source of root clk and i2s1 and i2s2
35 doesn't have any such mux.
Sylwester Nawrocki0d40c612015-01-14 19:42:38 +010036- #clock-cells: should be 1, this property must be present if the I2S device
37 is a clock provider in terms of the common clock bindings, described in
38 ../clock/clock-bindings.txt.
Sylwester Nawrockie2ce8522018-02-12 17:15:32 +010039- clock-output-names (deprecated): from the common clock bindings, names of
40 the CDCLK I2S output clocks, suggested values are "i2s_cdclk0", "i2s_cdclk1",
41 "i2s_cdclk3" for the I2S0, I2S1, I2S2 devices respectively.
Sylwester Nawrocki0d40c612015-01-14 19:42:38 +010042
43There are following clocks available at the I2S device nodes:
44 CLK_I2S_CDCLK - the CDCLK (CODECLKO) gate clock,
45 CLK_I2S_RCLK_PSR - the RCLK prescaler divider clock (corresponding to the
46 IISPSR register),
47 CLK_I2S_RCLK_SRC - the RCLKSRC mux clock (corresponding to RCLKSRC bit in
48 IISMOD register).
49
50Refer to the SoC datasheet for availability of the above clocks.
51The CLK_I2S_RCLK_PSR and CLK_I2S_RCLK_SRC clocks are usually only available
Sylwester Nawrockie2ce8522018-02-12 17:15:32 +010052in the IIS Multi Audio Interface.
53
54Note: Old DTs may not have the #clock-cells property and then not use the I2S
55node as a clock supplier.
Padmavathi Venna40476f62013-01-18 17:17:01 +053056
57Optional SoC Specific Properties:
58
Padmavathi Venna40476f62013-01-18 17:17:01 +053059- samsung,idma-addr: Internal DMA register base address of the audio
60 sub system(used in secondary sound source).
Padmavathi Venna4a3afb72013-06-18 00:02:31 +090061- pinctrl-0: Should specify pin control groups used for this controller.
62- pinctrl-names: Should contain only one value - "default".
Sylwester Nawrocki3f0c43e2018-02-12 17:15:38 +010063- #sound-dai-cells: should be 1.
Padmavathi Venna40476f62013-01-18 17:17:01 +053064
Sylwester Nawrocki0d40c612015-01-14 19:42:38 +010065
Padmavathi Venna40476f62013-01-18 17:17:01 +053066Example:
67
Marco Franchi48c926c2017-11-08 14:27:48 -020068i2s0: i2s@3830000 {
Padmavathi Venna7da493e2013-08-12 15:19:51 +053069 compatible = "samsung,s5pv210-i2s";
Padmavathi Venna40476f62013-01-18 17:17:01 +053070 reg = <0x03830000 0x100>;
71 dmas = <&pdma0 10
72 &pdma0 9
73 &pdma0 8>;
74 dma-names = "tx", "rx", "tx-sec";
Padmavathi Venna4a3afb72013-06-18 00:02:31 +090075 clocks = <&clock_audss EXYNOS_I2S_BUS>,
76 <&clock_audss EXYNOS_I2S_BUS>,
77 <&clock_audss EXYNOS_SCLK_I2S>;
78 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
Sylwester Nawrockie2ce8522018-02-12 17:15:32 +010079 #clock-cells = <1>;
Padmavathi Venna40476f62013-01-18 17:17:01 +053080 samsung,idma-addr = <0x03000000>;
Padmavathi Venna4a3afb72013-06-18 00:02:31 +090081 pinctrl-names = "default";
82 pinctrl-0 = <&i2s0_bus>;
Sylwester Nawrocki3f0c43e2018-02-12 17:15:38 +010083 #sound-dai-cells = <1>;
Padmavathi Venna40476f62013-01-18 17:17:01 +053084};