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Thomas Gleixneracee2e82019-06-04 10:10:53 +02001// SPDX-License-Identifier: GPL-2.0-only
Philipp Zabel3edba6b2015-09-30 13:55:47 +01002/*
3 * i.MX6 OCOTP fusebox driver
4 *
5 * Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
6 *
7 * Based on the barebox ocotp driver,
8 * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>,
9 * Orex Computed Radiography
10 *
Richard Leitner0642bac2017-03-31 13:44:55 +010011 * Write support based on the fsl_otp driver,
12 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
Philipp Zabel3edba6b2015-09-30 13:55:47 +010013 */
14
Peng Fandeb31972016-06-02 12:05:11 +010015#include <linux/clk.h>
Philipp Zabel3edba6b2015-09-30 13:55:47 +010016#include <linux/device.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/nvmem-provider.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/platform_device.h>
Philipp Zabel3edba6b2015-09-30 13:55:47 +010023#include <linux/slab.h>
Richard Leitner0642bac2017-03-31 13:44:55 +010024#include <linux/delay.h>
Philipp Zabel3edba6b2015-09-30 13:55:47 +010025
Richard Leitner9b665872017-03-31 13:44:54 +010026#define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the
27 * OTP Bank0 Word0
28 */
29#define IMX_OCOTP_OFFSET_PER_WORD 0x10 /* Offset between the start addr
30 * of two consecutive OTP words.
31 */
Richard Leitner0642bac2017-03-31 13:44:55 +010032
Richard Leitner9b665872017-03-31 13:44:54 +010033#define IMX_OCOTP_ADDR_CTRL 0x0000
Richard Leitner0642bac2017-03-31 13:44:55 +010034#define IMX_OCOTP_ADDR_CTRL_SET 0x0004
Richard Leitner9b665872017-03-31 13:44:54 +010035#define IMX_OCOTP_ADDR_CTRL_CLR 0x0008
Richard Leitner0642bac2017-03-31 13:44:55 +010036#define IMX_OCOTP_ADDR_TIMING 0x0010
Bryan O'Donoghueffd91152017-10-24 10:54:29 +010037#define IMX_OCOTP_ADDR_DATA0 0x0020
38#define IMX_OCOTP_ADDR_DATA1 0x0030
39#define IMX_OCOTP_ADDR_DATA2 0x0040
40#define IMX_OCOTP_ADDR_DATA3 0x0050
Richard Leitner9b665872017-03-31 13:44:54 +010041
Bryan O'Donoghuec03bb442019-06-26 11:27:28 +010042#define IMX_OCOTP_BM_CTRL_ADDR 0x000000FF
Richard Leitner0642bac2017-03-31 13:44:55 +010043#define IMX_OCOTP_BM_CTRL_BUSY 0x00000100
Richard Leitner9b665872017-03-31 13:44:54 +010044#define IMX_OCOTP_BM_CTRL_ERROR 0x00000200
Richard Leitner0642bac2017-03-31 13:44:55 +010045#define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400
Richard Leitner9b665872017-03-31 13:44:54 +010046
Peng Fan226c5122020-01-09 10:40:16 +000047#define IMX_OCOTP_BM_CTRL_DEFAULT \
48 { \
49 .bm_addr = IMX_OCOTP_BM_CTRL_ADDR, \
50 .bm_busy = IMX_OCOTP_BM_CTRL_BUSY, \
51 .bm_error = IMX_OCOTP_BM_CTRL_ERROR, \
52 .bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS,\
53 }
54
Bryan O'Donoghue159dbaf2019-06-26 11:27:30 +010055#define TIMING_STROBE_PROG_US 10 /* Min time to blow a fuse */
56#define TIMING_STROBE_READ_NS 37 /* Min time before read */
57#define TIMING_RELAX_NS 17
Bryan O'Donoghue828ae7a42017-10-24 10:54:31 +010058#define DEF_FSOURCE 1001 /* > 1000 ns */
59#define DEF_STROBE_PROG 10000 /* IPG clocks */
Richard Leitner0642bac2017-03-31 13:44:55 +010060#define IMX_OCOTP_WR_UNLOCK 0x3E770000
Richard Leitner9b665872017-03-31 13:44:54 +010061#define IMX_OCOTP_READ_LOCKED_VAL 0xBADABADA
62
Richard Leitner0642bac2017-03-31 13:44:55 +010063static DEFINE_MUTEX(ocotp_mutex);
64
Philipp Zabel3edba6b2015-09-30 13:55:47 +010065struct ocotp_priv {
66 struct device *dev;
Peng Fandeb31972016-06-02 12:05:11 +010067 struct clk *clk;
Philipp Zabel3edba6b2015-09-30 13:55:47 +010068 void __iomem *base;
Bryan O'Donoghuee20d2b22017-10-24 10:54:28 +010069 const struct ocotp_params *params;
Richard Leitner0642bac2017-03-31 13:44:55 +010070 struct nvmem_config *config;
Philipp Zabel3edba6b2015-09-30 13:55:47 +010071};
72
Peng Fan226c5122020-01-09 10:40:16 +000073struct ocotp_ctrl_reg {
74 u32 bm_addr;
75 u32 bm_busy;
76 u32 bm_error;
77 u32 bm_rel_shadows;
78};
79
Bryan O'Donoghue828ae7a42017-10-24 10:54:31 +010080struct ocotp_params {
81 unsigned int nregs;
82 unsigned int bank_address_words;
83 void (*set_timing)(struct ocotp_priv *priv);
Peng Fan226c5122020-01-09 10:40:16 +000084 struct ocotp_ctrl_reg ctrl;
Bryan O'Donoghue828ae7a42017-10-24 10:54:31 +010085};
86
Peng Fan226c5122020-01-09 10:40:16 +000087static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags)
Richard Leitner0642bac2017-03-31 13:44:55 +010088{
89 int count;
90 u32 c, mask;
Peng Fan226c5122020-01-09 10:40:16 +000091 u32 bm_ctrl_busy, bm_ctrl_error;
92 void __iomem *base = priv->base;
Richard Leitner0642bac2017-03-31 13:44:55 +010093
Peng Fan226c5122020-01-09 10:40:16 +000094 bm_ctrl_busy = priv->params->ctrl.bm_busy;
95 bm_ctrl_error = priv->params->ctrl.bm_error;
96
97 mask = bm_ctrl_busy | bm_ctrl_error | flags;
Richard Leitner0642bac2017-03-31 13:44:55 +010098
99 for (count = 10000; count >= 0; count--) {
100 c = readl(base + IMX_OCOTP_ADDR_CTRL);
101 if (!(c & mask))
102 break;
103 cpu_relax();
104 }
105
106 if (count < 0) {
107 /* HW_OCOTP_CTRL[ERROR] will be set under the following
108 * conditions:
109 * - A write is performed to a shadow register during a shadow
110 * reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is
111 * set. In addition, the contents of the shadow register shall
112 * not be updated.
113 * - A write is performed to a shadow register which has been
114 * locked.
115 * - A read is performed to from a shadow register which has
116 * been read locked.
117 * - A program is performed to a fuse word which has been locked
118 * - A read is performed to from a fuse word which has been read
119 * locked.
120 */
Peng Fan226c5122020-01-09 10:40:16 +0000121 if (c & bm_ctrl_error)
Richard Leitner0642bac2017-03-31 13:44:55 +0100122 return -EPERM;
123 return -ETIMEDOUT;
124 }
125
126 return 0;
127}
128
Peng Fan226c5122020-01-09 10:40:16 +0000129static void imx_ocotp_clr_err_if_set(struct ocotp_priv *priv)
Richard Leitner9b665872017-03-31 13:44:54 +0100130{
Peng Fan226c5122020-01-09 10:40:16 +0000131 u32 c, bm_ctrl_error;
132 void __iomem *base = priv->base;
133
134 bm_ctrl_error = priv->params->ctrl.bm_error;
Richard Leitner9b665872017-03-31 13:44:54 +0100135
136 c = readl(base + IMX_OCOTP_ADDR_CTRL);
Peng Fan226c5122020-01-09 10:40:16 +0000137 if (!(c & bm_ctrl_error))
Richard Leitner9b665872017-03-31 13:44:54 +0100138 return;
139
Peng Fan226c5122020-01-09 10:40:16 +0000140 writel(bm_ctrl_error, base + IMX_OCOTP_ADDR_CTRL_CLR);
Richard Leitner9b665872017-03-31 13:44:54 +0100141}
142
Srinivas Kandagatla33e5e292016-04-24 20:28:13 +0100143static int imx_ocotp_read(void *context, unsigned int offset,
144 void *val, size_t bytes)
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100145{
146 struct ocotp_priv *priv = context;
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100147 unsigned int count;
Srinivas Kandagatla33e5e292016-04-24 20:28:13 +0100148 u32 *buf = val;
Peng Fandeb31972016-06-02 12:05:11 +0100149 int i, ret;
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100150 u32 index;
151
152 index = offset >> 2;
Srinivas Kandagatla33e5e292016-04-24 20:28:13 +0100153 count = bytes >> 2;
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100154
Bryan O'Donoghuee20d2b22017-10-24 10:54:28 +0100155 if (count > (priv->params->nregs - index))
156 count = priv->params->nregs - index;
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100157
Richard Leitner0642bac2017-03-31 13:44:55 +0100158 mutex_lock(&ocotp_mutex);
159
Peng Fandeb31972016-06-02 12:05:11 +0100160 ret = clk_prepare_enable(priv->clk);
161 if (ret < 0) {
Richard Leitner0642bac2017-03-31 13:44:55 +0100162 mutex_unlock(&ocotp_mutex);
Peng Fandeb31972016-06-02 12:05:11 +0100163 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
164 return ret;
165 }
Richard Leitner9b665872017-03-31 13:44:54 +0100166
Peng Fan226c5122020-01-09 10:40:16 +0000167 ret = imx_ocotp_wait_for_busy(priv, 0);
Richard Leitner0642bac2017-03-31 13:44:55 +0100168 if (ret < 0) {
169 dev_err(priv->dev, "timeout during read setup\n");
170 goto read_end;
171 }
172
Richard Leitner9b665872017-03-31 13:44:54 +0100173 for (i = index; i < (index + count); i++) {
174 *buf++ = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 +
175 i * IMX_OCOTP_OFFSET_PER_WORD);
176
177 /* 47.3.1.2
178 * For "read locked" registers 0xBADABADA will be returned and
179 * HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by
180 * software before any new write, read or reload access can be
181 * issued
182 */
183 if (*(buf - 1) == IMX_OCOTP_READ_LOCKED_VAL)
Peng Fan226c5122020-01-09 10:40:16 +0000184 imx_ocotp_clr_err_if_set(priv);
Richard Leitner9b665872017-03-31 13:44:54 +0100185 }
Richard Leitner0642bac2017-03-31 13:44:55 +0100186 ret = 0;
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100187
Richard Leitner0642bac2017-03-31 13:44:55 +0100188read_end:
Peng Fandeb31972016-06-02 12:05:11 +0100189 clk_disable_unprepare(priv->clk);
Richard Leitner0642bac2017-03-31 13:44:55 +0100190 mutex_unlock(&ocotp_mutex);
191 return ret;
192}
193
Bryan O'Donoghueb50cb682017-10-24 10:54:30 +0100194static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
Richard Leitner0642bac2017-03-31 13:44:55 +0100195{
Richard Leitner0642bac2017-03-31 13:44:55 +0100196 unsigned long clk_rate = 0;
197 unsigned long strobe_read, relax, strobe_prog;
198 u32 timing = 0;
Richard Leitner0642bac2017-03-31 13:44:55 +0100199
200 /* 47.3.1.3.1
201 * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX]
202 * fields with timing values to match the current frequency of the
203 * ipg_clk. OTP writes will work at maximum bus frequencies as long
204 * as the HW_OCOTP_TIMING parameters are set correctly.
Bryan O'Donoghue159dbaf2019-06-26 11:27:30 +0100205 *
206 * Note: there are minimum timings required to ensure an OTP fuse burns
207 * correctly that are independent of the ipg_clk. Those values are not
208 * formally documented anywhere however, working from the minimum
209 * timings given in u-boot we can say:
210 *
211 * - Minimum STROBE_PROG time is 10 microseconds. Intuitively 10
212 * microseconds feels about right as representative of a minimum time
213 * to physically burn out a fuse.
214 *
215 * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before
216 * performing another read is 37 nanoseconds
217 *
218 * - Minimum RELAX timing is 17 nanoseconds. This final RELAX minimum
219 * timing is not entirely clear the documentation says "This
220 * count value specifies the time to add to all default timing
221 * parameters other than the Tpgm and Trd. It is given in number
222 * of ipg_clk periods." where Tpgm and Trd refer to STROBE_PROG
223 * and STROBE_READ respectively. What the other timing parameters
224 * are though, is not specified. Experience shows a zero RELAX
225 * value will mess up a re-load of the shadow registers post OTP
226 * burn.
Richard Leitner0642bac2017-03-31 13:44:55 +0100227 */
228 clk_rate = clk_get_rate(priv->clk);
229
Bryan O'Donoghue159dbaf2019-06-26 11:27:30 +0100230 relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1;
231 strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS,
232 1000000000);
233 strobe_read += 2 * (relax + 1) - 1;
234 strobe_prog = DIV_ROUND_CLOSEST(clk_rate * TIMING_STROBE_PROG_US,
235 1000000);
236 strobe_prog += 2 * (relax + 1) - 1;
Richard Leitner0642bac2017-03-31 13:44:55 +0100237
Bryan O'Donoghue0493c472019-06-26 11:27:29 +0100238 timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000;
239 timing |= strobe_prog & 0x00000FFF;
Richard Leitner0642bac2017-03-31 13:44:55 +0100240 timing |= (relax << 12) & 0x0000F000;
241 timing |= (strobe_read << 16) & 0x003F0000;
242
243 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
Bryan O'Donoghueb50cb682017-10-24 10:54:30 +0100244}
245
Bryan O'Donoghue828ae7a42017-10-24 10:54:31 +0100246static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv)
247{
248 unsigned long clk_rate = 0;
249 u64 fsource, strobe_prog;
250 u32 timing = 0;
251
252 /* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1
253 * 6.4.3.3
254 */
255 clk_rate = clk_get_rate(priv->clk);
256 fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE,
257 NSEC_PER_SEC) + 1;
258 strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG,
259 NSEC_PER_SEC) + 1;
260
261 timing = strobe_prog & 0x00000FFF;
262 timing |= (fsource << 12) & 0x000FF000;
263
264 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
265}
266
Bryan O'Donoghueb50cb682017-10-24 10:54:30 +0100267static int imx_ocotp_write(void *context, unsigned int offset, void *val,
268 size_t bytes)
269{
270 struct ocotp_priv *priv = context;
271 u32 *buf = val;
272 int ret;
273
274 u32 ctrl;
275 u8 waddr;
276 u8 word = 0;
277
278 /* allow only writing one complete OTP word at a time */
279 if ((bytes != priv->config->word_size) ||
280 (offset % priv->config->word_size))
281 return -EINVAL;
282
283 mutex_lock(&ocotp_mutex);
284
285 ret = clk_prepare_enable(priv->clk);
286 if (ret < 0) {
287 mutex_unlock(&ocotp_mutex);
288 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
289 return ret;
290 }
291
292 /* Setup the write timing values */
Bryan O'Donoghue828ae7a42017-10-24 10:54:31 +0100293 priv->params->set_timing(priv);
Richard Leitner0642bac2017-03-31 13:44:55 +0100294
295 /* 47.3.1.3.2
296 * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.
297 * Overlapped accesses are not supported by the controller. Any pending
298 * write or reload must be completed before a write access can be
299 * requested.
300 */
Peng Fan226c5122020-01-09 10:40:16 +0000301 ret = imx_ocotp_wait_for_busy(priv, 0);
Richard Leitner0642bac2017-03-31 13:44:55 +0100302 if (ret < 0) {
303 dev_err(priv->dev, "timeout during timing setup\n");
304 goto write_end;
305 }
306
307 /* 47.3.1.3.3
308 * Write the requested address to HW_OCOTP_CTRL[ADDR] and program the
309 * unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed
310 * for each write access. The lock code is documented in the register
311 * description. Both the unlock code and address can be written in the
312 * same operation.
313 */
Bryan O'Donoghueffd91152017-10-24 10:54:29 +0100314 if (priv->params->bank_address_words != 0) {
315 /*
316 * In banked/i.MX7 mode the OTP register bank goes into waddr
317 * see i.MX 7Solo Applications Processor Reference Manual, Rev.
318 * 0.1 section 6.4.3.1
319 */
320 offset = offset / priv->config->word_size;
321 waddr = offset / priv->params->bank_address_words;
322 word = offset & (priv->params->bank_address_words - 1);
323 } else {
324 /*
325 * Non-banked i.MX6 mode.
326 * OTP write/read address specifies one of 128 word address
327 * locations
328 */
329 waddr = offset / 4;
330 }
Richard Leitner0642bac2017-03-31 13:44:55 +0100331
332 ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL);
Peng Fan226c5122020-01-09 10:40:16 +0000333 ctrl &= ~priv->params->ctrl.bm_addr;
334 ctrl |= waddr & priv->params->ctrl.bm_addr;
Richard Leitner0642bac2017-03-31 13:44:55 +0100335 ctrl |= IMX_OCOTP_WR_UNLOCK;
336
337 writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL);
338
339 /* 47.3.1.3.4
340 * Write the data to the HW_OCOTP_DATA register. This will automatically
341 * set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To
342 * protect programming same OTP bit twice, before program OCOTP will
343 * automatically read fuse value in OTP and use read value to mask
344 * program data. The controller will use masked program data to program
345 * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit
346 * fields with 1's will result in that OTP bit being programmed. Bit
347 * fields with 0's will be ignored. At the same time that the write is
348 * accepted, the controller makes an internal copy of
349 * HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write
350 * sequence is initiated. This copy guarantees that erroneous writes to
351 * HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It
352 * should also be noted that during the programming HW_OCOTP_DATA will
353 * shift right (with zero fill). This shifting is required to program
354 * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be
355 * modified.
Bryan O'Donoghueffd91152017-10-24 10:54:29 +0100356 * Note: on i.MX7 there are four data fields to write for banked write
357 * with the fuse blowing operation only taking place after data0
358 * has been written. This is why data0 must always be the last
359 * register written.
Richard Leitner0642bac2017-03-31 13:44:55 +0100360 */
Bryan O'Donoghueffd91152017-10-24 10:54:29 +0100361 if (priv->params->bank_address_words != 0) {
362 /* Banked/i.MX7 mode */
363 switch (word) {
364 case 0:
365 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
366 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
367 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
368 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
369 break;
370 case 1:
371 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1);
372 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
373 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
374 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
375 break;
376 case 2:
377 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
378 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2);
379 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
380 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
381 break;
382 case 3:
383 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
384 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
385 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3);
386 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
387 break;
388 }
389 } else {
390 /* Non-banked i.MX6 mode */
391 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
392 }
Richard Leitner0642bac2017-03-31 13:44:55 +0100393
394 /* 47.4.1.4.5
395 * Once complete, the controller will clear BUSY. A write request to a
396 * protected or locked region will result in no OTP access and no
397 * setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will
398 * be set. It must be cleared by software before any new write access
399 * can be issued.
400 */
Peng Fan226c5122020-01-09 10:40:16 +0000401 ret = imx_ocotp_wait_for_busy(priv, 0);
Richard Leitner0642bac2017-03-31 13:44:55 +0100402 if (ret < 0) {
403 if (ret == -EPERM) {
404 dev_err(priv->dev, "failed write to locked region");
Peng Fan226c5122020-01-09 10:40:16 +0000405 imx_ocotp_clr_err_if_set(priv);
Richard Leitner0642bac2017-03-31 13:44:55 +0100406 } else {
407 dev_err(priv->dev, "timeout during data write\n");
408 }
409 goto write_end;
410 }
411
412 /* 47.3.1.4
413 * Write Postamble: Due to internal electrical characteristics of the
414 * OTP during writes, all OTP operations following a write must be
415 * separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following
416 * the write.
417 */
418 udelay(2);
419
420 /* reload all shadow registers */
Peng Fan226c5122020-01-09 10:40:16 +0000421 writel(priv->params->ctrl.bm_rel_shadows,
Richard Leitner0642bac2017-03-31 13:44:55 +0100422 priv->base + IMX_OCOTP_ADDR_CTRL_SET);
Peng Fan226c5122020-01-09 10:40:16 +0000423 ret = imx_ocotp_wait_for_busy(priv,
424 priv->params->ctrl.bm_rel_shadows);
Richard Leitner0642bac2017-03-31 13:44:55 +0100425 if (ret < 0) {
426 dev_err(priv->dev, "timeout during shadow register reload\n");
427 goto write_end;
428 }
429
430write_end:
431 clk_disable_unprepare(priv->clk);
432 mutex_unlock(&ocotp_mutex);
433 if (ret < 0)
434 return ret;
435 return bytes;
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100436}
437
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100438static struct nvmem_config imx_ocotp_nvmem_config = {
439 .name = "imx-ocotp",
Richard Leitner0642bac2017-03-31 13:44:55 +0100440 .read_only = false,
Srinivas Kandagatla33e5e292016-04-24 20:28:13 +0100441 .word_size = 4,
442 .stride = 4,
Srinivas Kandagatla33e5e292016-04-24 20:28:13 +0100443 .reg_read = imx_ocotp_read,
Richard Leitner0642bac2017-03-31 13:44:55 +0100444 .reg_write = imx_ocotp_write,
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100445};
446
Bryan O'Donoghuee20d2b22017-10-24 10:54:28 +0100447static const struct ocotp_params imx6q_params = {
448 .nregs = 128,
Bryan O'Donoghueffd91152017-10-24 10:54:29 +0100449 .bank_address_words = 0,
Bryan O'Donoghue828ae7a42017-10-24 10:54:31 +0100450 .set_timing = imx_ocotp_set_imx6_timing,
Peng Fan226c5122020-01-09 10:40:16 +0000451 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
Bryan O'Donoghuee20d2b22017-10-24 10:54:28 +0100452};
453
454static const struct ocotp_params imx6sl_params = {
455 .nregs = 64,
Bryan O'Donoghueffd91152017-10-24 10:54:29 +0100456 .bank_address_words = 0,
Bryan O'Donoghue828ae7a42017-10-24 10:54:31 +0100457 .set_timing = imx_ocotp_set_imx6_timing,
Peng Fan226c5122020-01-09 10:40:16 +0000458 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
Bryan O'Donoghuee20d2b22017-10-24 10:54:28 +0100459};
460
Anson Huang6da27822018-07-11 11:20:43 +0100461static const struct ocotp_params imx6sll_params = {
462 .nregs = 128,
463 .bank_address_words = 0,
464 .set_timing = imx_ocotp_set_imx6_timing,
Peng Fan226c5122020-01-09 10:40:16 +0000465 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
Anson Huang6da27822018-07-11 11:20:43 +0100466};
467
Bryan O'Donoghuee20d2b22017-10-24 10:54:28 +0100468static const struct ocotp_params imx6sx_params = {
469 .nregs = 128,
Bryan O'Donoghueffd91152017-10-24 10:54:29 +0100470 .bank_address_words = 0,
Bryan O'Donoghue828ae7a42017-10-24 10:54:31 +0100471 .set_timing = imx_ocotp_set_imx6_timing,
Peng Fan226c5122020-01-09 10:40:16 +0000472 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
Bryan O'Donoghuee20d2b22017-10-24 10:54:28 +0100473};
474
475static const struct ocotp_params imx6ul_params = {
476 .nregs = 128,
Bryan O'Donoghueffd91152017-10-24 10:54:29 +0100477 .bank_address_words = 0,
Bryan O'Donoghue828ae7a42017-10-24 10:54:31 +0100478 .set_timing = imx_ocotp_set_imx6_timing,
Peng Fan226c5122020-01-09 10:40:16 +0000479 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
Bryan O'Donoghuee20d2b22017-10-24 10:54:28 +0100480};
481
Stefan Wahrenffbc34b2019-01-28 15:54:59 +0000482static const struct ocotp_params imx6ull_params = {
483 .nregs = 64,
484 .bank_address_words = 0,
485 .set_timing = imx_ocotp_set_imx6_timing,
Peng Fan226c5122020-01-09 10:40:16 +0000486 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
Stefan Wahrenffbc34b2019-01-28 15:54:59 +0000487};
488
Bryan O'Donoghuee20d2b22017-10-24 10:54:28 +0100489static const struct ocotp_params imx7d_params = {
490 .nregs = 64,
Bryan O'Donoghueffd91152017-10-24 10:54:29 +0100491 .bank_address_words = 4,
Bryan O'Donoghue828ae7a42017-10-24 10:54:31 +0100492 .set_timing = imx_ocotp_set_imx7_timing,
Peng Fan226c5122020-01-09 10:40:16 +0000493 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
Bryan O'Donoghuee20d2b22017-10-24 10:54:28 +0100494};
495
Anson Huangc8b63dd2019-01-28 15:54:57 +0000496static const struct ocotp_params imx7ulp_params = {
497 .nregs = 256,
498 .bank_address_words = 0,
Peng Fan226c5122020-01-09 10:40:16 +0000499 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
Anson Huangc8b63dd2019-01-28 15:54:57 +0000500};
501
Lucas Stach38e7b6e2019-04-13 11:32:47 +0100502static const struct ocotp_params imx8mq_params = {
503 .nregs = 256,
Leonard Crestez5a1c1722019-06-26 11:27:33 +0100504 .bank_address_words = 0,
505 .set_timing = imx_ocotp_set_imx6_timing,
Peng Fan226c5122020-01-09 10:40:16 +0000506 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
Lucas Stach38e7b6e2019-04-13 11:32:47 +0100507};
508
Bryan O'Donoghue4112c8532019-06-26 11:27:31 +0100509static const struct ocotp_params imx8mm_params = {
510 .nregs = 256,
511 .bank_address_words = 0,
512 .set_timing = imx_ocotp_set_imx6_timing,
Peng Fan226c5122020-01-09 10:40:16 +0000513 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
Bryan O'Donoghue4112c8532019-06-26 11:27:31 +0100514};
515
Anson Huangd93b5d42019-08-18 10:33:40 +0100516static const struct ocotp_params imx8mn_params = {
517 .nregs = 256,
518 .bank_address_words = 0,
519 .set_timing = imx_ocotp_set_imx6_timing,
Peng Fan226c5122020-01-09 10:40:16 +0000520 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
Anson Huangd93b5d42019-08-18 10:33:40 +0100521};
522
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100523static const struct of_device_id imx_ocotp_dt_ids[] = {
Bryan O'Donoghuee20d2b22017-10-24 10:54:28 +0100524 { .compatible = "fsl,imx6q-ocotp", .data = &imx6q_params },
525 { .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params },
526 { .compatible = "fsl,imx6sx-ocotp", .data = &imx6sx_params },
527 { .compatible = "fsl,imx6ul-ocotp", .data = &imx6ul_params },
Stefan Wahrenffbc34b2019-01-28 15:54:59 +0000528 { .compatible = "fsl,imx6ull-ocotp", .data = &imx6ull_params },
Bryan O'Donoghuee20d2b22017-10-24 10:54:28 +0100529 { .compatible = "fsl,imx7d-ocotp", .data = &imx7d_params },
Anson Huang6da27822018-07-11 11:20:43 +0100530 { .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params },
Anson Huangc8b63dd2019-01-28 15:54:57 +0000531 { .compatible = "fsl,imx7ulp-ocotp", .data = &imx7ulp_params },
Lucas Stach38e7b6e2019-04-13 11:32:47 +0100532 { .compatible = "fsl,imx8mq-ocotp", .data = &imx8mq_params },
Bryan O'Donoghue4112c8532019-06-26 11:27:31 +0100533 { .compatible = "fsl,imx8mm-ocotp", .data = &imx8mm_params },
Anson Huangd93b5d42019-08-18 10:33:40 +0100534 { .compatible = "fsl,imx8mn-ocotp", .data = &imx8mn_params },
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100535 { },
536};
537MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
538
539static int imx_ocotp_probe(struct platform_device *pdev)
540{
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100541 struct device *dev = &pdev->dev;
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100542 struct ocotp_priv *priv;
543 struct nvmem_device *nvmem;
544
545 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
546 if (!priv)
547 return -ENOMEM;
548
Richard Leitner4cefb742017-03-31 13:44:49 +0100549 priv->dev = dev;
550
Anson Huang3b26cd82019-04-13 11:32:59 +0100551 priv->base = devm_platform_ioremap_resource(pdev, 0);
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100552 if (IS_ERR(priv->base))
553 return PTR_ERR(priv->base);
554
Richard Leitner4cefb742017-03-31 13:44:49 +0100555 priv->clk = devm_clk_get(dev, NULL);
Peng Fandeb31972016-06-02 12:05:11 +0100556 if (IS_ERR(priv->clk))
557 return PTR_ERR(priv->clk);
558
Bryan O'Donoghuee20d2b22017-10-24 10:54:28 +0100559 priv->params = of_device_get_match_data(&pdev->dev);
560 imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100561 imx_ocotp_nvmem_config.dev = dev;
Srinivas Kandagatla33e5e292016-04-24 20:28:13 +0100562 imx_ocotp_nvmem_config.priv = priv;
Richard Leitner0642bac2017-03-31 13:44:55 +0100563 priv->config = &imx_ocotp_nvmem_config;
Richard Leitner0642bac2017-03-31 13:44:55 +0100564
Peng Fan226c5122020-01-09 10:40:16 +0000565 clk_prepare_enable(priv->clk);
566 imx_ocotp_clr_err_if_set(priv);
567 clk_disable_unprepare(priv->clk);
568
569 nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100570
Andrey Smirnova8302742018-03-09 14:46:59 +0000571 return PTR_ERR_OR_ZERO(nvmem);
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100572}
573
574static struct platform_driver imx_ocotp_driver = {
575 .probe = imx_ocotp_probe,
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100576 .driver = {
577 .name = "imx_ocotp",
578 .of_match_table = imx_ocotp_dt_ids,
579 },
580};
581module_platform_driver(imx_ocotp_driver);
582
583MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
Bryan O'Donoghueaef9a4d2017-10-24 10:54:33 +0100584MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver");
Philipp Zabel3edba6b2015-09-30 13:55:47 +0100585MODULE_LICENSE("GPL v2");