Thomas Gleixner | ec8f24b | 2019-05-19 13:07:45 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Alexandre Belloni | 4114112 | 2015-03-13 22:57:18 +0100 | [diff] [blame] | 2 | menuconfig ARCH_AT91 |
Nicolas Ferre | ed08b63 | 2018-02-28 15:56:43 +0100 | [diff] [blame] | 3 | bool "AT91/Microchip SoCs" |
Szemző András | 2d4c44e | 2017-05-31 03:06:21 +0200 | [diff] [blame] | 4 | depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M |
Arnd Bergmann | dbeb0c8 | 2017-08-23 16:46:15 +0200 | [diff] [blame] | 5 | select ARM_CPU_SUSPEND if PM && ARCH_MULTI_V7 |
Nicolas Ferre | ef7eda2 | 2014-11-21 17:10:06 +0100 | [diff] [blame] | 6 | select COMMON_CLK_AT91 |
Linus Walleij | 5c34a4e | 2016-06-02 14:10:16 +0200 | [diff] [blame] | 7 | select GPIOLIB |
Alexandre Belloni | 4114112 | 2015-03-13 22:57:18 +0100 | [diff] [blame] | 8 | select PINCTRL |
Alexandre Belloni | 4114112 | 2015-03-13 22:57:18 +0100 | [diff] [blame] | 9 | select SOC_BUS |
Ludovic Desroches | 8f4b479 | 2013-03-22 13:24:12 +0000 | [diff] [blame] | 10 | |
Alexandre Belloni | 4114112 | 2015-03-13 22:57:18 +0100 | [diff] [blame] | 11 | if ARCH_AT91 |
Szemző András | 2d4c44e | 2017-05-31 03:06:21 +0200 | [diff] [blame] | 12 | config SOC_SAMV7 |
| 13 | bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M |
| 14 | select COMMON_CLK_AT91 |
| 15 | select PINCTRL_AT91 |
| 16 | help |
Nicolas Ferre | ed08b63 | 2018-02-28 15:56:43 +0100 | [diff] [blame] | 17 | Select this if you are using an SoC from Microchip's SAME7, SAMS7 or SAMV7 |
Szemző András | 2d4c44e | 2017-05-31 03:06:21 +0200 | [diff] [blame] | 18 | families. |
| 19 | |
Nicolas Ferre | c268a74 | 2015-07-30 19:12:12 +0200 | [diff] [blame] | 20 | config SOC_SAMA5D2 |
Masahiro Yamada | e324654 | 2015-11-16 12:06:10 +0900 | [diff] [blame] | 21 | bool "SAMA5D2 family" |
| 22 | depends on ARCH_MULTI_V7 |
Nicolas Ferre | c268a74 | 2015-07-30 19:12:12 +0200 | [diff] [blame] | 23 | select SOC_SAMA5 |
| 24 | select CACHE_L2X0 |
Nicolas Ferre | c268a74 | 2015-07-30 19:12:12 +0200 | [diff] [blame] | 25 | select HAVE_AT91_UTMI |
| 26 | select HAVE_AT91_USB_CLK |
| 27 | select HAVE_AT91_H32MX |
| 28 | select HAVE_AT91_GENERATED_CLK |
Quentin Schulz | 0865805 | 2017-08-10 08:34:03 +0200 | [diff] [blame] | 29 | select HAVE_AT91_AUDIO_PLL |
Codrin Ciubotariu | 96e4ea8 | 2018-06-18 17:12:36 +0300 | [diff] [blame] | 30 | select HAVE_AT91_I2S_MUX_CLK |
Ludovic Desroches | 8423536 | 2015-12-01 11:44:40 +0100 | [diff] [blame] | 31 | select PINCTRL_AT91PIO4 |
Nicolas Ferre | c268a74 | 2015-07-30 19:12:12 +0200 | [diff] [blame] | 32 | help |
Nicolas Ferre | ed08b63 | 2018-02-28 15:56:43 +0100 | [diff] [blame] | 33 | Select this if ou are using one of Microchip's SAMA5D2 family SoC. |
Nicolas Ferre | c268a74 | 2015-07-30 19:12:12 +0200 | [diff] [blame] | 34 | |
Ludovic Desroches | 8f4b479 | 2013-03-22 13:24:12 +0000 | [diff] [blame] | 35 | config SOC_SAMA5D3 |
Masahiro Yamada | e324654 | 2015-11-16 12:06:10 +0900 | [diff] [blame] | 36 | bool "SAMA5D3 family" |
| 37 | depends on ARCH_MULTI_V7 |
Ludovic Desroches | 8f4b479 | 2013-03-22 13:24:12 +0000 | [diff] [blame] | 38 | select SOC_SAMA5 |
Boris BREZILLON | f090fb3 | 2013-10-11 12:22:06 +0200 | [diff] [blame] | 39 | select HAVE_AT91_UTMI |
Boris BREZILLON | a9c0688 | 2013-10-11 13:27:06 +0200 | [diff] [blame] | 40 | select HAVE_AT91_SMD |
Boris BREZILLON | c84a61d | 2013-10-17 18:55:41 +0200 | [diff] [blame] | 41 | select HAVE_AT91_USB_CLK |
Ludovic Desroches | 8423536 | 2015-12-01 11:44:40 +0100 | [diff] [blame] | 42 | select PINCTRL_AT91 |
Ludovic Desroches | 8f4b479 | 2013-03-22 13:24:12 +0000 | [diff] [blame] | 43 | help |
Nicolas Ferre | ed08b63 | 2018-02-28 15:56:43 +0100 | [diff] [blame] | 44 | Select this if you are using one of Microchip's SAMA5D3 family SoC. |
Josh Wu | 7f45716 | 2013-11-06 18:01:11 +0800 | [diff] [blame] | 45 | This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36. |
Nicolas Ferre | 2dc850b | 2014-09-15 18:15:54 +0200 | [diff] [blame] | 46 | |
| 47 | config SOC_SAMA5D4 |
Masahiro Yamada | e324654 | 2015-11-16 12:06:10 +0900 | [diff] [blame] | 48 | bool "SAMA5D4 family" |
| 49 | depends on ARCH_MULTI_V7 |
Nicolas Ferre | 2dc850b | 2014-09-15 18:15:54 +0200 | [diff] [blame] | 50 | select SOC_SAMA5 |
Nicolas Ferre | 2dc850b | 2014-09-15 18:15:54 +0200 | [diff] [blame] | 51 | select CACHE_L2X0 |
Nicolas Ferre | 2dc850b | 2014-09-15 18:15:54 +0200 | [diff] [blame] | 52 | select HAVE_AT91_UTMI |
| 53 | select HAVE_AT91_SMD |
| 54 | select HAVE_AT91_USB_CLK |
| 55 | select HAVE_AT91_H32MX |
Ludovic Desroches | 8423536 | 2015-12-01 11:44:40 +0100 | [diff] [blame] | 56 | select PINCTRL_AT91 |
Nicolas Ferre | 2dc850b | 2014-09-15 18:15:54 +0200 | [diff] [blame] | 57 | help |
Nicolas Ferre | ed08b63 | 2018-02-28 15:56:43 +0100 | [diff] [blame] | 58 | Select this if you are using one of Microchip's SAMA5D4 family SoC. |
Ludovic Desroches | 8f4b479 | 2013-03-22 13:24:12 +0000 | [diff] [blame] | 59 | |
Jean-Christophe PLAGNIOL-VILLARD | 1e3ce2b | 2012-04-06 11:51:50 +0800 | [diff] [blame] | 60 | config SOC_AT91RM9200 |
Masahiro Yamada | e324654 | 2015-11-16 12:06:10 +0900 | [diff] [blame] | 61 | bool "AT91RM9200" |
| 62 | depends on ARCH_MULTI_V4T |
Nicolas Ferre | ef7eda2 | 2014-11-21 17:10:06 +0100 | [diff] [blame] | 63 | select ATMEL_AIC_IRQ |
Alexandre Belloni | b2f0627 | 2017-05-31 03:06:22 +0200 | [diff] [blame] | 64 | select ATMEL_PM if PM |
Alexandre Belloni | b53cdd0 | 2015-03-12 13:07:31 +0100 | [diff] [blame] | 65 | select ATMEL_ST |
Russell King | c750815 | 2008-10-26 10:55:14 +0000 | [diff] [blame] | 66 | select CPU_ARM920T |
Boris BREZILLON | c84a61d | 2013-10-17 18:55:41 +0200 | [diff] [blame] | 67 | select HAVE_AT91_USB_CLK |
Ludovic Desroches | 8423536 | 2015-12-01 11:44:40 +0100 | [diff] [blame] | 68 | select PINCTRL_AT91 |
Alexandre Belloni | 4114112 | 2015-03-13 22:57:18 +0100 | [diff] [blame] | 69 | select SOC_SAM_V4_V5 |
Wenyou Yang | 896bc87 | 2015-03-09 11:44:50 +0800 | [diff] [blame] | 70 | select SRAM if PM |
Alexandre Belloni | 4114112 | 2015-03-13 22:57:18 +0100 | [diff] [blame] | 71 | help |
Nicolas Ferre | ed08b63 | 2018-02-28 15:56:43 +0100 | [diff] [blame] | 72 | Select this if you are using Microchip's AT91RM9200 SoC. |
Andrew Victor | 8fc5ffa | 2006-06-29 16:06:33 +0100 | [diff] [blame] | 73 | |
Alexandre Belloni | 2b019a4 | 2015-01-15 22:58:13 +0100 | [diff] [blame] | 74 | config SOC_AT91SAM9 |
Masahiro Yamada | e324654 | 2015-11-16 12:06:10 +0900 | [diff] [blame] | 75 | bool "AT91SAM9" |
| 76 | depends on ARCH_MULTI_V5 |
Alexandre Belloni | 2b019a4 | 2015-01-15 22:58:13 +0100 | [diff] [blame] | 77 | select ATMEL_AIC_IRQ |
Alexandre Belloni | b2f0627 | 2017-05-31 03:06:22 +0200 | [diff] [blame] | 78 | select ATMEL_PM if PM |
Alexandre Belloni | 2b019a4 | 2015-01-15 22:58:13 +0100 | [diff] [blame] | 79 | select ATMEL_SDRAMC |
Alexandre Belloni | 2b019a4 | 2015-01-15 22:58:13 +0100 | [diff] [blame] | 80 | select CPU_ARM926T |
Boris BREZILLON | a9c0688 | 2013-10-11 13:27:06 +0200 | [diff] [blame] | 81 | select HAVE_AT91_SMD |
Boris BREZILLON | c84a61d | 2013-10-17 18:55:41 +0200 | [diff] [blame] | 82 | select HAVE_AT91_USB_CLK |
Alexandre Belloni | 2b019a4 | 2015-01-15 22:58:13 +0100 | [diff] [blame] | 83 | select HAVE_AT91_UTMI |
Hong Xu | 74db4fb | 2012-04-17 14:26:31 +0800 | [diff] [blame] | 84 | select HAVE_FB_ATMEL |
Alexandre Belloni | 2b019a4 | 2015-01-15 22:58:13 +0100 | [diff] [blame] | 85 | select MEMORY |
Ludovic Desroches | 8423536 | 2015-12-01 11:44:40 +0100 | [diff] [blame] | 86 | select PINCTRL_AT91 |
Alexandre Belloni | 4114112 | 2015-03-13 22:57:18 +0100 | [diff] [blame] | 87 | select SOC_SAM_V4_V5 |
Wenyou Yang | 896bc87 | 2015-03-09 11:44:50 +0800 | [diff] [blame] | 88 | select SRAM if PM |
Hong Xu | 74db4fb | 2012-04-17 14:26:31 +0800 | [diff] [blame] | 89 | help |
Nicolas Ferre | ed08b63 | 2018-02-28 15:56:43 +0100 | [diff] [blame] | 90 | Select this if you are using one of those Microchip SoC: |
Alexandre Belloni | 2b019a4 | 2015-01-15 22:58:13 +0100 | [diff] [blame] | 91 | AT91SAM9260 |
| 92 | AT91SAM9261 |
| 93 | AT91SAM9263 |
| 94 | AT91SAM9G15 |
| 95 | AT91SAM9G20 |
| 96 | AT91SAM9G25 |
| 97 | AT91SAM9G35 |
| 98 | AT91SAM9G45 |
| 99 | AT91SAM9G46 |
| 100 | AT91SAM9M10 |
| 101 | AT91SAM9M11 |
| 102 | AT91SAM9N12 |
| 103 | AT91SAM9RL |
| 104 | AT91SAM9X25 |
| 105 | AT91SAM9X35 |
| 106 | AT91SAM9XE |
Greg Ungerer | 9f1ccef | 2007-07-30 02:39:21 +0100 | [diff] [blame] | 107 | |
Claudiu Beznea | fe7ff55 | 2019-11-29 15:51:38 +0200 | [diff] [blame] | 108 | config SOC_SAM9X60 |
| 109 | bool "SAM9X60" |
| 110 | depends on ARCH_MULTI_V5 |
| 111 | select ATMEL_AIC5_IRQ |
| 112 | select ATMEL_PM if PM |
| 113 | select ATMEL_SDRAMC |
| 114 | select CPU_ARM926T |
| 115 | select HAVE_AT91_USB_CLK |
| 116 | select HAVE_AT91_GENERATED_CLK |
| 117 | select HAVE_AT91_SAM9X60_PLL |
| 118 | select MEMORY |
| 119 | select PINCTRL_AT91 |
| 120 | select SOC_SAM_V4_V5 |
| 121 | select SRAM if PM |
| 122 | help |
| 123 | Select this if you are using Microchip's SAM9X60 SoC |
| 124 | |
Alexandre Belloni | 7803dc8 | 2019-04-26 23:47:13 +0200 | [diff] [blame] | 125 | comment "Clocksource driver selection" |
| 126 | |
| 127 | config ATMEL_CLOCKSOURCE_PIT |
| 128 | bool "Periodic Interval Timer (PIT) support" |
Claudiu Beznea | fe7ff55 | 2019-11-29 15:51:38 +0200 | [diff] [blame] | 129 | depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 |
Alexandre Belloni | 7803dc8 | 2019-04-26 23:47:13 +0200 | [diff] [blame] | 130 | default SOC_AT91SAM9 || SOC_SAMA5 |
| 131 | select ATMEL_PIT |
| 132 | help |
| 133 | Select this to get a clocksource based on the Atmel Periodic Interval |
| 134 | Timer. It has a relatively low resolution and the TC Block clocksource |
| 135 | should be preferred. |
| 136 | |
| 137 | config ATMEL_CLOCKSOURCE_TCB |
| 138 | bool "Timer Counter Blocks (TCB) support" |
Claudiu Beznea | fe7ff55 | 2019-11-29 15:51:38 +0200 | [diff] [blame] | 139 | default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 |
Alexandre Belloni | 7803dc8 | 2019-04-26 23:47:13 +0200 | [diff] [blame] | 140 | select ATMEL_TCB_CLKSRC |
| 141 | help |
| 142 | Select this to get a high precision clocksource based on a |
| 143 | TC block with a 5+ MHz base clock rate. |
| 144 | On platforms with 16-bit counters, two timer channels are combined |
| 145 | to make a single 32-bit timer. |
| 146 | It can also be used as a clock event device supporting oneshot mode. |
| 147 | |
Alexandre Belloni | 4114112 | 2015-03-13 22:57:18 +0100 | [diff] [blame] | 148 | config HAVE_AT91_UTMI |
| 149 | bool |
| 150 | |
| 151 | config HAVE_AT91_USB_CLK |
| 152 | bool |
| 153 | |
| 154 | config COMMON_CLK_AT91 |
| 155 | bool |
Boris Brezillon | 863a81c | 2014-09-05 09:54:13 +0200 | [diff] [blame] | 156 | select MFD_SYSCON |
Alexandre Belloni | 4114112 | 2015-03-13 22:57:18 +0100 | [diff] [blame] | 157 | |
| 158 | config HAVE_AT91_SMD |
| 159 | bool |
| 160 | |
| 161 | config HAVE_AT91_H32MX |
| 162 | bool |
| 163 | |
Nicolas Ferre | df70aee | 2015-07-31 11:43:12 +0200 | [diff] [blame] | 164 | config HAVE_AT91_GENERATED_CLK |
| 165 | bool |
| 166 | |
Quentin Schulz | 0865805 | 2017-08-10 08:34:03 +0200 | [diff] [blame] | 167 | config HAVE_AT91_AUDIO_PLL |
| 168 | bool |
| 169 | |
Codrin Ciubotariu | 96e4ea8 | 2018-06-18 17:12:36 +0300 | [diff] [blame] | 170 | config HAVE_AT91_I2S_MUX_CLK |
| 171 | bool |
| 172 | |
Claudiu Beznea | fc8c4c0 | 2019-11-29 15:51:37 +0200 | [diff] [blame] | 173 | config HAVE_AT91_SAM9X60_PLL |
| 174 | bool |
| 175 | |
Alexandre Belloni | 4114112 | 2015-03-13 22:57:18 +0100 | [diff] [blame] | 176 | config SOC_SAM_V4_V5 |
| 177 | bool |
| 178 | |
| 179 | config SOC_SAM_V7 |
| 180 | bool |
| 181 | |
| 182 | config SOC_SAMA5 |
| 183 | bool |
| 184 | select ATMEL_AIC5_IRQ |
Alexandre Belloni | b2f0627 | 2017-05-31 03:06:22 +0200 | [diff] [blame] | 185 | select ATMEL_PM if PM |
Alexandre Belloni | 4114112 | 2015-03-13 22:57:18 +0100 | [diff] [blame] | 186 | select ATMEL_SDRAMC |
| 187 | select MEMORY |
| 188 | select SOC_SAM_V7 |
| 189 | select SRAM if PM |
| 190 | |
Alexandre Belloni | b2f0627 | 2017-05-31 03:06:22 +0200 | [diff] [blame] | 191 | config ATMEL_PM |
| 192 | bool |
| 193 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 194 | endif |