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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 2040cf9f59037aa8aec749363e69ead165b67b43 / . / arch / arm64 / boot / dts / marvell / armada-80x0.dtsi
blob: ee67c70bf02efc2396b3a02065b719d7cf68816e [file] [log] [blame]
Gregory CLEMENT292816a2018-02-14 13:17:20 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
Gregory CLEMENTae701b62017-06-12 17:34:58 +0200[diff] [blame]2/*
3 * Copyright (C) 2017 Marvell Technology Group Ltd.
4 *
Gregory CLEMENTae701b62017-06-12 17:34:58 +0200[diff] [blame]5 * Device Tree file for the Armada 80x0 SoC family
6 */
7
Gregory CLEMENT63dac0f2017-06-12 17:35:00 +0200[diff] [blame]8/ {
9 aliases {
Thomas Petazzoni91f1be92018-01-02 15:55:58 +0100[diff] [blame]10 gpio1 = &cp1_gpio1;
11 gpio2 = &cp0_gpio2;
12 spi1 = &cp0_spi0;
13 spi2 = &cp0_spi1;
14 spi3 = &cp1_spi0;
15 spi4 = &cp1_spi1;
Gregory CLEMENT63dac0f2017-06-12 17:35:00 +0200[diff] [blame]16 };
17};
18
Thomas Petazzoni72a37132018-01-02 15:55:57 +0100[diff] [blame]19/*
20 * Instantiate the master CP110
21 */
Miquel Raynal47cf40a2019-10-04 16:27:29 +0200[diff] [blame]22#define CP11X_NAME cp0
23#define CP11X_BASE f2000000
Miquel Raynal5f07b262019-10-04 16:27:31 +0200[diff] [blame]24#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
25#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
Miquel Raynal47cf40a2019-10-04 16:27:29 +0200[diff] [blame]26#define CP11X_PCIE0_BASE f2600000
27#define CP11X_PCIE1_BASE f2620000
28#define CP11X_PCIE2_BASE f2640000
Thomas Petazzoni72a37132018-01-02 15:55:57 +0100[diff] [blame]29
30#include "armada-cp110.dtsi"
31
Miquel Raynal47cf40a2019-10-04 16:27:29 +0200[diff] [blame]32#undef CP11X_NAME
33#undef CP11X_BASE
Miquel Raynal5f07b262019-10-04 16:27:31 +0200[diff] [blame]34#undef CP11X_PCIEx_MEM_BASE
35#undef CP11X_PCIEx_MEM_SIZE
Miquel Raynal47cf40a2019-10-04 16:27:29 +0200[diff] [blame]36#undef CP11X_PCIE0_BASE
37#undef CP11X_PCIE1_BASE
38#undef CP11X_PCIE2_BASE
Thomas Petazzoni72a37132018-01-02 15:55:57 +0100[diff] [blame]39
40/*
41 * Instantiate the slave CP110
42 */
Miquel Raynal47cf40a2019-10-04 16:27:29 +0200[diff] [blame]43#define CP11X_NAME cp1
44#define CP11X_BASE f4000000
Miquel Raynal5f07b262019-10-04 16:27:31 +0200[diff] [blame]45#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
46#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
Miquel Raynal47cf40a2019-10-04 16:27:29 +0200[diff] [blame]47#define CP11X_PCIE0_BASE f4600000
48#define CP11X_PCIE1_BASE f4620000
49#define CP11X_PCIE2_BASE f4640000
Thomas Petazzoni72a37132018-01-02 15:55:57 +0100[diff] [blame]50
51#include "armada-cp110.dtsi"
52
Miquel Raynal47cf40a2019-10-04 16:27:29 +0200[diff] [blame]53#undef CP11X_NAME
54#undef CP11X_BASE
Miquel Raynal5f07b262019-10-04 16:27:31 +0200[diff] [blame]55#undef CP11X_PCIEx_MEM_BASE
56#undef CP11X_PCIEx_MEM_SIZE
Miquel Raynal47cf40a2019-10-04 16:27:29 +0200[diff] [blame]57#undef CP11X_PCIE0_BASE
58#undef CP11X_PCIE1_BASE
59#undef CP11X_PCIE2_BASE
Thomas Petazzoni72a37132018-01-02 15:55:57 +0100[diff] [blame]60
Gregory CLEMENT63dac0f2017-06-12 17:35:00 +0200[diff] [blame]61/* The 80x0 has two CP blocks, but uses only one block from each. */
Thomas Petazzoni91f1be92018-01-02 15:55:58 +0100[diff] [blame]62&cp1_gpio1 {
Gregory CLEMENT63dac0f2017-06-12 17:35:00 +0200[diff] [blame]63 status = "okay";
64};
65
Thomas Petazzoni91f1be92018-01-02 15:55:58 +0100[diff] [blame]66&cp0_gpio2 {
Gregory CLEMENT63dac0f2017-06-12 17:35:00 +0200[diff] [blame]67 status = "okay";
68};
69
Thomas Petazzoni91f1be92018-01-02 15:55:58 +0100[diff] [blame]70&cp0_syscon0 {
71 cp0_pinctrl: pinctrl {
Gregory CLEMENTf9a0c272018-01-12 11:00:02 +0100[diff] [blame]72 compatible = "marvell,armada-8k-cpm-pinctrl";
Gregory CLEMENTae701b62017-06-12 17:34:58 +0200[diff] [blame]73 };
74};
75
Thomas Petazzoni91f1be92018-01-02 15:55:58 +0100[diff] [blame]76&cp1_syscon0 {
77 cp1_pinctrl: pinctrl {
Gregory CLEMENTf9a0c272018-01-12 11:00:02 +0100[diff] [blame]78 compatible = "marvell,armada-8k-cps-pinctrl";
Miquel Raynal7b31e3a2017-10-30 14:31:07 +0100[diff] [blame]79
80 nand_pins: nand-pins {
81 marvell,pins =
82 "mpp0", "mpp1", "mpp2", "mpp3",
83 "mpp4", "mpp5", "mpp6", "mpp7",
84 "mpp8", "mpp9", "mpp10", "mpp11",
85 "mpp15", "mpp16", "mpp17", "mpp18",
86 "mpp19", "mpp20", "mpp21", "mpp22",
87 "mpp23", "mpp24", "mpp25", "mpp26",
88 "mpp27";
89 marvell,function = "dev";
90 };
91
92 nand_rb: nand-rb {
93 marvell,pins = "mpp13", "mpp12";
94 marvell,function = "nf";
95 };
Gregory CLEMENTae701b62017-06-12 17:34:58 +0200[diff] [blame]96 };
97};
Thomas Petazzoni72a37132018-01-02 15:55:57 +0100[diff] [blame]98
Thomas Petazzoni91f1be92018-01-02 15:55:58 +0100[diff] [blame]99&cp1_crypto {
Thomas Petazzoni72a37132018-01-02 15:55:57 +0100[diff] [blame]100 /*
101 * The cryptographic engine found on the cp110
102 * master is enabled by default at the SoC
103 * level. Because it is not possible as of now
104 * to enable two cryptographic engines in
105 * parallel, disable this one by default.
106 */
107 status = "disabled";
108};